DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-14 in the reply filed on 6/26/26 is acknowledged.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the limitations of claims 7,11, reciting: “a metal layer …underlying the metallic barrier liner” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3,6,8-10,12,14 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kim et al., (Kim) US 2024/0008274.
Regarding claim 1, Kim shows in FIG. 2-12, a semiconductor structure, comprising: an alternating stack of insulating layers (220)[0031] and electrically conductive layers (230)[0031] that alternate along a vertical direction, wherein a bottommost layer of the alternating stack comprises a bottommost electrically conductive layer (203); a memory opening (CH) vertically extending through the alternating stack; a memory opening fill structure (245,240)[0033] located in the memory opening and comprising a vertical semiconductor channel (240) and a vertical stack of memory elements (245,247); and a source layer (205) contacting a bottom surface of the bottommost electrically conductive layer (203) and a bottom surface of the vertical semiconductor channel (240).
Regarding claim 2, Kim shows in FIG. 2-12, a semiconductor structure, wherein each electrically conductive layer (230) within the alternating stack consists of a same set of at least one metallic material.
Regarding claim 3, Kim shows in FIG. 2-12, a semiconductor structure, wherein: all electrically conductive layers (230) within the alternating stack except the bottommost electrically conductive layer (203) have a first vertical thickness; and the bottommost electrically conductive layer (203) has a second vertical thickness that is less than the first vertical thickness.
Regarding claim 6, Kim shows in FIG. 2-12, a semiconductor structure, wherein: the memory opening fill structure (CH) comprises a dielectric core (247) that is laterally surrounded by the vertical semiconductor channel (240); and an interface between the source layer (205) and the dielectric core (247) is vertically offset toward a topmost layer of the alternating stack relative to a horizontal interface between the source layer (205) and the bottommost electrically conductive layer [0033].
Regarding claim 8, Kim shows in FIG. 2-12, a semiconductor structure, a semiconductor structure, comprising: an alternating stack of insulating layers (220) and electrically conductive layers (230) that alternate along a vertical direction; a memory opening (CH) vertically extending through the alternating stack; a memory opening fill structure (245,240) located in the memory opening and comprising a vertical semiconductor channel (240) and a vertical stack of memory elements (245,247); a semiconductor material layer underlying the alternating stack, contacting an outer sidewall of the memory film (245) and not directly contacting the vertical semiconductor channel (240); and a source layer (205) underlying and contacting a bottom surface of the semiconductor material layer and contacting a bottom surface of the vertical semiconductor channel (240).
Regarding claim 9, Kim shows in FIG. 2-12, a semiconductor structure, a semiconductor structure wherein the source layer (205) contacts an annular planar horizontal surface of the vertical semiconductor channel (240) located within a horizontal plane including a bottom surface of the semiconductor material layer.
Regarding claim 10, Kim shows in FIG. 2-12, a semiconductor structure, a semiconductor structure wherein the memory film comprises: the outer sidewall that contacts a cylindrical surface segment of the semiconductor material layer (240); and an annular planar bottom surface that contacts the source layer (205), wherein the source layer (205) contacts a cylindrical surface segment of an inner sidewall of the memory film (242).
Regarding claim 12, Kim shows in FIG. 2-12, a semiconductor structure, wherein an annular bottom surface of the vertical semiconductor channel (240) located within a horizontal plane including a bottom surface of the semiconductor material layer.
Regarding claim 14, Kim shows in FIG. 2-12, a semiconductor structure, wherein an annular bottom surface of the memory film (245) contacts the source layer (205) within a horizontal plane including a bottom surface of the semiconductor material layer.
Allowable Subject Matter
Claims 4,5,7,11,13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. As for claims 7,11, the Applicant is advised to fix the drawing issue.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARC-ANTHONY ARMAND whose telephone number is (571)272-5178. The examiner can normally be reached 8am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven B Gauthier can be reached at 571-270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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MARC - ANTHONY ARMAND
Primary Examiner
Art Unit 2813
/MARC-ANTHONY ARMAND/ Primary Examiner, Art Unit 2813
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