DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, claims 1-14 in the reply filed on 04/16/2026 is acknowledged.
Claims 15-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim.
Claims 1-14 have been fully considered in Examination.
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 02/01/2024, 02/19/2025, and 04/16/2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement(s) is/are being considered by the examiner.
Claim Objections
Claims 5, 7, and 9 are objected to because of the following informalities
Claim 5, line 2: “and bottom portion that contacts…” should read --- and a bottom portion that contacts… ---
Claim 7, line 9: “additional source layer strips in second memory block…” should read --- additional source layer strips in a second memory block…
Claim 9, line 2: “located above horizontal plane” should read --- located above the horizontal plane ---
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-4, 6, 11, and 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Ryu (U.S. PG Pub No US2022/0344244A1) in view of Zhao (U.S. PG Pub No US2021/0159169A1).
Regarding claim 1, Ryu teaches a semiconductor structure (100d) fig. 5B [0061] (see also fig. 2A [0020]), comprising:
an alternating stack of insulating layers (120 above 120U) fig. 5B [0028] and electrically conductive layers (130b) fig. 5B [0028, 0035] (formed of conductive metal such as Ti [0035]) overlying an etch-stop dielectric layer (120U) fig. 5B [0030, 0068] (120 material offers some etch selectivity /stopping [0068]) (see perspective of annotated fig. 5B below);
a memory opening (gap in 110, 120 filled by CHe) fig. 8B [0058-0059] vertically extending through the alternating stack (110, 120) and at least partly through the etch-stop dielectric layer (120U);
a memory opening fill structure (CHe) [0058-0059] located in the memory opening (gap filled by CHe) and comprising a vertical semiconductor channel (140) fig. 5B [0058] (polysilicon semiconductor [0041]), a core (147a) fig. 5B [0060] (formed of “insulating” material [0005-0007, 0060]) that is laterally surrounded by the vertical semiconductor channel (140), and a memory film (145) fig. 5B [0042, 0058] that laterally surrounds the vertical semiconductor channel (140);
a metal capping layer (200) fig. 5B [0030] (may be formed of tungsten W [0030]) (directly) contacting an end (bottom) portion of the vertical semiconductor channel (140) and a bottom portion of the core (147) (see annotated fig. 5B below); and
a source layer (205) fig. 2A [0054] (positioned atop 205) (thermally) contacting the metal capping layer (200) and a bottom surface of the etch-stop dielectric layer (120U) (120U considered in thermal contact with 205 through adjoined, conductive 200, 110 [0030, 0058] materials) (see flipped perspective annotated fig. 5B below).
[AltContent: arrow][AltContent: oval][AltContent: arrow][AltContent: oval][AltContent: arrow][AltContent: ][AltContent: connector][AltContent: connector][AltContent: connector][AltContent: textbox (At least 90 ° of azimuthal angle not covered by extent of 103 around this center point of CHe, in plane as defined; therefore, azimuthal extent of 103 not greater than 3π/2 radians /270°)][AltContent: textbox (At least 90 ° of azimuthal angle not covered by extent of 110 around center point of CHe, in plane as defined; therefore, azimuthal extent of 110 not greater than 3π/2 radians /270°)][AltContent: oval][AltContent: connector][AltContent: connector][AltContent: connector]
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Annotated fig. 5B of Ryu
However, Ryu does not explicitly disclose wherein the core (147a) (formed of ‘insulating’ material [0005-0007, 0060]) is a dielectric core (specific insulating material of core and whether it is a “dielectric” material not explicitly disclosed).
Zhao teaches a semiconductor structure [see fig. 15] wherein the core (62 formed of 62L) fig. 15 [0074] is a dielectric core (62-core explicitly formed of dielectric material such as silicon oxide [0074] insulating dielectric material [0034, 0040]).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the semiconductor structure of Ryu such that the insulating core of the channel pillars is formed of a dielectric material such as silicon oxide [0074, 0034] because of the material’s specifically art recognized suitability for said purpose because of favorable deposition-fill [0074] and etch selectivity properties [0075] during formation, as evidenced by Zhao.
Regarding claim 2, Ryu in view of Zhao teaches the semiconductor structure (100d) fig. 5B [0061] (see also fig. 2A [0020]) of claim 1. Ryu also teaches further comprising an insulating spacer (110) fig. 5B [0058] (may be formed of insulator like silicon oxide [0058, 0053]) located (vertically) between the metal capping layer (200) fig. 5B [0030] and a combination of the etch-stop dielectric layer (120U) fig. 5B [0030, 0068] and a bottommost electrically conductive layer (bottommost 130b) fig. 5B [0028, 0035] within the alternating stack (120, 130b) (see annotated fig. 5B above).
Regarding claim 3, Ryu in view of Zhao teaches the semiconductor structure (100d) fig. 5B [0061] (see also fig. 2A [0020]) of claim 2. Ryu also teaches wherein the insulating spacer (110) fig. 5B [0058] has a tubular configuration [0058-0059] (110 surrounds tubular CH structures [0058], assuming tubular shape therearound; see also fig. 1 perspective) and laterally surrounds [0058] the metal capping layer (200) fig. 5B [0030] (portion of 200 between 140).
Regarding claim 4, Ryu in view of Zhao teaches the semiconductor structure (100d) fig. 5B [0061] (see also fig. 2A [0020]) of claim 2. Ryu also teaches wherein:
the insulating spacer (110) fig. 5B [0058] has a first azimuthal extent around a vertical axis passing through a geometrical center of the memory opening fill structure (CHe) [0058-0059], the first azimuthal extent being not greater than 3π/2 (as defined in annotated fig. 5B above); and
the memory film (145) fig. 5B [0042, 0058] contacts sidewalls of the insulating spacer (110) (see annotated fig. 5B above).
Regarding claim 6, Ryu in view of Zhao teaches the semiconductor structure (100d) fig. 5B [0061] (see also fig. 2A [0020]) of claim 1. Ryu also teaches wherein a vertically-extending portion (in boxed area) annotated fig. 5B above) of the metal capping layer (200) fig. 5B [0030] has a first azimuthal extent around a vertical axis passing through a geometrical center (center point, as defined in annotated fig. 7 above) of the memory opening fill structure (CH) fig. 7 [0053], the first azimuthal extent being not greater than 3π/2 (as defined in annotated fig. 7 above).
Regarding claim 11, Ryu in view of Zhao teaches the semiconductor structure (100d) fig. 5B [0061] (see also fig. 2A [0020]) of claim 1. Ryu also teaches wherein the metal capping layer (200) fig. 5B [0030] (may be formed of tungsten W [0030]) comprises tungsten [0030] and the source layer (205) fig. 2A [0054] comprises tungsten [0054].
Regarding claim 13, Ryu in view of Zhao teaches the semiconductor structure (100d) fig. 5B [0061] (see also fig. 2A [0020]) of claim 1. Ryu also teaches wherein:
each of the electrically conductive layers (130b) fig. 5B [0028, 0035] is embedded within a respective outer blocking dielectric layer (130a) fig. 5B [0035] (high-k dielectric physical blocking embedded 130b) [0035]; and
the etch-stop dielectric layer (120U) fig. 5B [0030, 0568] is in direct contact with a horizontally-extending portion of a bottommost outer blocking dielectric layer (bottommost 130a) of the outer blocking dielectric layers (see annotated fig. 5B above).
Regarding claim 14, Ryu in view of Zhao teaches the semiconductor structure (100d) fig. 5B [0061] (see also fig. 2A [0020]) of claim 13. Ryu also teaches further comprising an insulating spacer (110) fig. 5B [0058] (may be formed of insulator like silicon oxide [0058, 0053]) in contact with (in thermal contact with through physically adjoined layers each in thermal exchange/contact) the metal capping layer (200) fig. 5B [0030], the bottommost outer blocking dielectric layer (bottommost 130a) fig. 5B [0035], a bottommost insulating layer (bottommost 120 above 120U) fig. 5B [0028] within the alternating stack (120, 130) fig. 5B [0028], the vertical semiconductor channel (140) fig. 5B [0058], and the memory film (145) fig. 5B [0042, 0058].
Claims 1, 5, 8, and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (U.S. PG Pub No US2023/0403854A1) in view of Ryu (U.S. PG Pub No US2022/0344244A1).
Regarding claim 1, Kim teaches a semiconductor structure [see figs. 6-7, 0106], comprising:
an alternating stack of insulating layers (112s above lowermost 112) fig. 7 [0062] and electrically conductive layers (ECL, GSL) fig. 7 [0107] (formed of electrically connective gate electrode material [0107-0108, 0062]) overlying an etch-stop dielectric layer (lowermost 112) fig. 7 [0030, 0068] (112 material [0062] must offer some degree of physical etch-stoppage towards covered layers) (see perspective of annotated fig. 7 below);
a memory opening (gap in 112, ECL, GSL filled by CH) fig. 7 [0053] vertically extending through the alternating stack (112, ECL, GSL) and at least partly through the etch-stop dielectric layer (lowermost 112);
a memory opening fill structure (CH) [0053] located in the memory opening (gap filled by CH) and comprising a vertical semiconductor channel (130) fig. 7 [0067], a dielectric core (134) fig. 7 [0074] (silicon oxide [0074] – see further discussion about silicon oxide being a ‘dielectric’ below) that is laterally surrounded by the vertical semiconductor channel (130), and a memory film (132) fig. 7 [0070] that laterally surrounds the vertical semiconductor channel (130) (see also fig. 3 perspective);
a capping layer (103) fig. 7 [0051] (thermally) contacting [0068] an end (bottom) portion of the vertical semiconductor channel (130) and a bottom portion of the dielectric core (134) (plug 103 in thermal contact / exchange with both 130 and 134 - separated by 130) (see annotated fig. 7 below); and
a source layer (101 with 104) fig. 7 [0054] (see also fig. 4 for layer 104) (semiconductor layer 101 in direct contact with/effectively extending source layer 104 [0054-0057]) (directly) contacting the capping layer (103) and a bottom surface of the etch-stop dielectric layer (lowermost 112) (101 in direct contact with both 103 and bottommost surface in flipped perspective of annotated fig. 7 of Kim below).
Although Kim does not explicitly disclose that the core material 134 is a “dielectric” material, [0074] of Kim discloses that core 134 may be formed of insulating silicon oxide material. [0122] of the instant application’s specification discloses that “a dielectric core layer 62L comprising a dielectric fill material, such as silicon oxide, can be deposited”, that is, both [0074] of Kim and [0122] of instant application disclose that the core may be formed of silicon oxide material. Therefore, the silicon oxide material of Kim’s core is considered to inherently be a “dielectric” core material, in view of [0122] of the instant application’s disclosure. (See MPEP 2112.01, II).
[AltContent: arrow][AltContent: arrow][AltContent: textbox (Top of 103)][AltContent: textbox (HP)][AltContent: textbox (Bottom of 103)][AltContent: arrow][AltContent: rect][AltContent: rect][AltContent: rect][AltContent: arrow][AltContent: textbox (Etch protection )][AltContent: textbox (Stack )][AltContent: ]
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Annotated fig. 7 of Kim
However, Kim does not explicitly teach wherein the capping layer (3) is formed of metal (material of conductive 3 [0051, 0068] not explicitly disclosed).
Ryu teaches a semiconductor structure (100d) fig. 5B [0061]
wherein the capping layer (200) fig. 5B [0030] is formed of metal (may be formed of metal such as tungsten W [0030] – and/or doped semiconductor [0030] and/or other conductive materials).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the semiconductor structure of Kim such that the conductive capping layer disposed at the end(s) of the channel pillar(s) is/are formed of a conductive material such as tungsten metal [0030] because of a variety of metal materials’ [0030] art recognized suitability as a conductive material for the formation of electrical connections with circuitry at the end of the memory stack [0030], as taught by Ryu.
Regarding claim 5, Kim in view of Ryu teaches the semiconductor structure [see figs. 6-7, 0106] of claim 1. Kim in view of Ryu also teaches wherein the metal capping layer (103) fig. 7 [0051] comprises a tubular portion (“plug”-shaped 103 laterally surrounds tubular CH extending partially therethrough [0068]; see also fig. 3 perspective) that laterally surrounds the dielectric core (134) fig. 7 [0074], and a bottom portion that contacts (thermally contacts through 130 [0067]) a bottom surface of the dielectric core (134) (see annotated fig. 7 above).
Regarding claim 8, Kim in view of Ryu teaches the semiconductor structure [see figs. 6-7, 0106] of claim 1. Kim in view of Ryu also teaches wherein:
a bottom surface (103) fig. 7 [0051] of the metal capping layer (103) is located below a horizontal plane including a horizontal interface between the source layer (comprising 101) fig. 7 [0054] and the etch-stop dielectric layer (lowermost 112) fig. 7 [0030, 0068]; and
a top surface of the metal capping layer (103) is located above the horizontal plane (see annotated fig. 7 above).
Regarding claim 10, Kim in view of Ryu teaches the semiconductor structure [see figs. 6-7, 0106] of claim 1. Kim also teaches wherein:
the source layer (101 with 104) fig. 7 [0054] (see also fig. 4 for layer 104) is embedded (partially laterally embedded) within the etch-stop dielectric layer (comprising lowermost 112 with WLC with DCH) (WLC, DCH physically adjoined to lowermost 112 and also formed of physical etch-stopping insulating material [0081]); and
a bottommost surface of the etch-stop dielectric layer (bottommost surface of WLC/DCH in 101) is coplanar with a bottom surface of the source layer (local bottom of 101 bordering WLC/DCH bottommost surface) (see annotated fig. 4 of Kim below).
[AltContent: oval][AltContent: arrow][AltContent: textbox (Embedded portion of 101)][AltContent: textbox (Outline of etch protection layer as defined in claim 10 )][AltContent: arrow][AltContent: ]
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Annotated fig. 4 of Kim
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Ryu (U.S. PG Pub No US2022/0344244A1) modified by Zhao (U.S. PG Pub No US2021/0159169A1), as applied in claim 11 above, and further in view of Hinoue (U.S. PG Pub No US2019/0287982A1).
Regarding claim 12, Ryu in view of Zhao teaches the semiconductor structure (100d) fig. 5B [0061] (see also fig. 2A [0020]) of claim 11. However, Ryu does not explicitly disclose wherein the metal capping layer (200) fig. 5B [0030] comprises tungsten [0030] containing residual silicon atoms at a variable atomic concentration that decreases with a distance (in thickness direction) from an interface with the dielectric core (147a) fig. 5B [0060].
Hinoue teaches a semiconductor structure [see fig. 15A, 0134] wherein the metal capping layer (represented by 146A material) fig. 14B [0102-0105] comprises tungsten (in graded WSiN [0104, 0106-0107]) containing residual silicon atoms (Si [0104]) at a variable atomic concentration (graded [0104]) [see fig. 11B, 0104, 0137] that decreases with a distance (in thickness direction) from an interface with the dielectric core (positionally represented by 44 material) fig. 11B [0139-0140] (concentration of Si of nearly zero at an upper portion [0140] to non-zero at a lower interface of 146A/46A with core material positionally represented by 44 of Hinoue – therefore, silicon concentration of W-based material decreases in thickness direction [0102] away from dielectric core [0104, 0140]).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the tungsten metal capping layer above the dielectric core of Ryu to comprise a vertically-graded concentration of silicon dopant throughout [0104, 0137, 0140] in order to enhance diffusion barrier properties of the contact structure [0035] and improve adhesion strength of the metal contact with adjacent dielectric materials [0035], as taught by Hinoue.
Allowable Subject Matter
Claims 7 and 9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 7 is considered to contain allowable subject matter because the prior art of record neither anticipates nor renders obvious the claimed limitation(s) “the source layer comprises a source layer strip which contacts two rows of metal capping layers which contact two rows of memory opening fill structures in a first memory block” in the context of claim 7, dependent upon claim 6, dependent upon claim 1.
Claim 9 is considered to contain allowable subject matter because the prior art of record neither anticipates nor renders obvious the claimed limitation(s) “the vertical semiconductor channel and the memory film are located entirely above the horizontal plane” in the context of claim 9, dependent upon claim 8, dependent upon claim 1.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Remaining references made available on the PTO-892 form are considered relevant to the present disclosure because they all feature memory devices with metal and source layer(s) in ‘contact’ with channel pillar structures.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEAN AYERS WINTERS whose telephone number is (571)270-3308. The examiner can normally be reached Monday - Friday 10:30 am - 7:00 pm (EST).
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/SEAN AYERS WINTERS/Examiner, Art Unit 2892 07/04/2026
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