DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
2. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
3. Claim(s) 1-4, 6-8, 10-12, 15-16, is/are rejected under 35 U.S.C. 103 as being unpatentable over MATSUDA, US 2017/0365571 A1.
Claim 1. MATSUDA discloses a method (such as the steps from fig. 5), comprising:
-plating a first conductive layer (item 24, as [0017] disclose the plating process) on a second conductive layer (item 22), the second conductive layer coupled to a device side of a semiconductor die (item 11, [0015]);
-using a vapor deposition technique to deposit a silicon nitride layer (item 12/16/18) physically contacting the first conductive layer (this limitation would read through [0022] wherein is disclosed insulating layers may be formed by CVD technique,
-and plating a third conductive layer (item 26/28/32) physically contacting the first conductive layer, the third conductive layer contacting a solder ball (item 21, fig. 5).
MATSUDA appears to not specifically indicate a thickness of the silicon nitride layer less than a thickness of the first conductive layer. However, in the structure in fig. 2b, 5, for example, it is shown that the thickness of (item 12/16) is lesser than the thickness of item 24. Thus, MATSUDA meets this limitation.
Therefore, to form a semiconductor package structure for the use in packaging integrated circuit products, such as microprocessors, storage circuits, three-dimensional (3D) chips, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to use a thickness of the silicon nitride layer less than a thickness of the first conductive layer. In addition, it ensures the conductive layer remains intact, minimizes stress and parasitic, and allows for precise planarization and patterning, all while maintaining the nitride’s protective and insulating properties.
Claim 10. MATSUDA disclose a method of forming a semiconductor package (such as the steps from fig. 5), comprising:
-forming a first conductive layer (item 24) on a portion of a second conductive layer (item 22), the second conductive layer part of a device side of a semiconductor die (item 11);
-forming a silicon nitride layer (item 12/16/18) physically contacting the first conductive layer, the silicon nitride layer contacting a first portion of a top surface of the first conductive layer and side surfaces of the first conductive layer (this limitation would read through [0021] wherein is disclosed for example, depositing the first to third insulating films, 12, 14 and 16, on the semiconductor stack 11 and the ohmic electrode 22, where the first and third insulating films, 12 and 16, may be formed by the chemical vapor deposition (CVD) technique),
-forming under bump metallization (UBM) layer, with a portion of the UBM layer contacting a second portion of the top surface of the first conductive layer (this limitation would read through [0035] wherein is disclosed for example, applying a solder paste on the surface of the cover metal 32 and performing the reflow soldering, the process may form the solder bump 21 on the cover metal 32. Thus, the process of forming the electrode 20 is completed).
MATSUDA appears to not specifically indicate a thickness of the silicon nitride layer less than a thickness of the first conductive layer. However, in the structure in fig. 2b, 5, for example, it is shown that the thickness of (item 12/16) is lesser than the thickness of item 24. Thus, MATSUDA meets this limitation.
Therefore, to form a semiconductor package structure for the use in packaging integrated circuit products, such as microprocessors, storage circuits, three-dimensional (3D) chips, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to use a thickness of the silicon nitride layer less than a thickness of the first conductive layer. In addition, it ensures the conductive layer remains intact, minimizes stress and parasitic, and allows for precise planarization and patterning, all while maintaining the nitride’s protective and insulating properties.
Claims 2, 11. MATSUDA disclose the method of claims 1, 10, wherein the silicon nitride layer has a thickness ranging between 300 Angstroms and 3000 Angstroms (this limitation would read through [0044] wherein is disclosed for example, the mound metal preferably has a thickness of 1 to 4 μm).
Claim 3. MATSUDA disclose the method of claim 1, wherein the vapor deposition technique includes a physical vapor deposition technique (this limitation would read through [0022] wherein is disclosed for example, the first and third insulating films, 12 and 16, may be formed by the chemical vapor deposition (CVD) technique).
Claim 4. MATSUDA disclose the method of claim 1, wherein the vapor deposition technique includes a plasma enhanced chemical vapor deposition technique (this limitation would read through [0022] wherein is disclosed for example, the first and third insulating films, 12 and 16, may be formed by the chemical vapor deposition (CVD) technique).
Claims 6, 7 and 15. MATSUDA disclose the method of claims 1 and 10, further comprising forming a polyimide layer abutting the silicon nitride layer and further comprising etching a gap in the silicon nitride layer (this limitation would read through [0022] wherein is disclosed for example, while the second insulating film 14 is made of polyimide with a thickness of about 2 μm).
Claim 8. MATSUDA disclose the method of claim 7, further comprising coupling the first and second conductive layers through the gap in the silicon nitride layer such that the third conductive layer contacts the first conductive layer. This limitation would read through [0032] wherein is disclosed second interconnection 28 extends from the surface of the seed layer 26 within the opening 19a vertically and laterally; however, the lateral extension of the second interconnection 28 may be prevented by the mound metal 30. That is, the mound metal 30 may operate as a barrier to interrupt the second interconnection 28 extending laterally on the top insulating film 19.
Claim 12. MATSUDA disclose the method of claim 10, wherein forming a silicon nitride layer includes using a vapor deposition technique to deposit the silicon nitride layer (this limitation would read through [0022] wherein is disclosed for example, the first and third insulating films, 12 and 16, may be formed by the chemical vapor deposition (CVD) technique).
Claim 16. MATSUDA disclose the method of claim 10, wherein the semiconductor package is a wafer-level chip scale package (WCSP), (this limitation would read through [0049] wherein is disclosed for example, the first and second embodiment thus described concentrate on the arrangement of the BGA).
4. Claim(s) 5, 9, 13-14, is/are rejected under 35 U.S.C. 103 as being unpatentable over MATSUDA, US 2017/0365571 A1, in view of Chen et al., US 6,566,183 B1.
Claims 5 and 14. MATSUDA, disclose the method of claims 1 and 10, above. MATSUDA appears to not specify “wherein depositing the silicon nitride layer includes providing a temperature range of 325 degrees Celsius to 425 degrees Celsius”. However, in a similar process col. 4, In 32+ of Chen discloses that the wafer’s temperature while depositing the second silicon nitride layer 50 may be between 400 and 800.degree. C. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the process of Chen et al., with the invention of MATSUDA, as the use of the process of Chen et al., would help to create a barrier, which prevents diffusion from layers formed on top of the silicon nitride layer. Therefore, MATSUDA with Chen et al., together further teach and/or suggest as obvious to one of ordinary skill in the art.
Claims 9 and 13. MATSUDA, disclose the method of claims 1 and 10, above. MATSUDA appears to not specify “wherein using the vapor deposition technique to deposit the silicon nitride layer comprising depositing the silicon nitride layer at a pressure lower than 100 Torr”.
However, in a similar process col. 4, In 28+ of Chen discloses that partial pressure of the SiH.sub.4 while depositing the second silicon nitride layer 50 may be between 1.5 and 100 Torr. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the process of Chen et al., with the invention of MATSUDA, as the use of the process of Chen et al., would help to create a barrier, which prevents diffusion from layers formed on top of the silicon nitride layer. Therefore, MATSUDA, and Chen et al., together further teach and/or suggest as obvious to one of ordinary skill in the art.
Response to Arguments
5. Applicant's arguments filed 01/26/2026 have been fully considered but they are not persuasive.
Applicant contends that Matsuda fails to teach all of the limitations of Claim 1. Specifically, Matsuda fails to teach the limitation "plating a first conductive layer on a second conductive layer, the second conductive layer coupled to a device side of a semiconductor die; using a vapor deposition technique to deposit a silicon nitride layer physically contacting the first conductive layer" as required by Claim 1.
In response, it is noted that Matsuda clearly disclose the invention, for example, [0017] the plating process of the structure of fig. 5, wherein: item 24 would be interpreted as a first conductive, item 22, as second conductive that physically a semiconductor die, and [0016] disclose that items 12, 16 and 18, may be made of silicon nitride (SiN) with a thickness of 0.1 to 0.5μm; and [0021] disclose the chemical vapor deposition (CVD) technique. Similarly, to claim 10, as apply to claim 1, Matsuda meets this limitation. Therefore, it is urged that the pending claims (2-9 and 11-16) are not in condition for allowance.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILNER JEAN BAPTISTE whose telephone number is (571)270-7394. The examiner can normally be reached M-T 8:00-6:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 571-270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/W.J/ Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
Prosecution Insights