DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) filed on January 17th, 2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Election/Restrictions
Applicant's election without traverse of Invention I, corresponding to claims 1-19, drawn to EDMOS FET structures, classified in H10D 30/65, H10D 30/67 and H10D 62/10 in the reply filed on June 8th, 2026 is acknowledged.
The requirement is made FINAL, claims 1-19 are being examined on their merits and all non-elected claims (i.e. claim 20) are withdrawn from consideration at this time.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-8 and 10-11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cortes Mayol et al. (US10497803B2)
Regarding claim 1;
Cortes Mayol et al. teaches A structure comprising: a semiconductor on insulator (SOI) material including a first portion with a first thickness and a second portion with a second thickness (e.g. Fig. 1 ref 20 34, see examiner markup); a gate structure on the SOI material over the first portion with the first thickness (e.g. Fig. 1 ref 30, Detail description “A gate structure 30 is located on the fully depleted semiconductor layer 20.”); and sidewall spacers adjacent to the gate structure, with at least one sidewall spacer extending over both the first portion with the first thickness and the second portion with the second thickness (e.g. Fig. 1 ref 30c,40).
PNG
media_image1.png
557
883
media_image1.png
Greyscale
Regarding claim 2;
Cortes Mayol et al. further teaches that the sidewall spacers comprise two sidewall spacers with different thicknesses (e.g. Fig. 1, See examiner markup).
PNG
media_image2.png
557
883
media_image2.png
Greyscale
Regarding claim 3;
Cortes Mayol et al. further teaches that the at least one sidewall spacer extends to a drain side of the gate structure (e.g. Fig. 1, see examiner markup).
PNG
media_image3.png
557
883
media_image3.png
Greyscale
Regarding claim 4;
Cortes Mayol et al. further teaches that the at least one sidewall spacer is an outer sidewall spacer that is thicker than an inner sidewall spacer (e.g. Fig. 1, see examiner markup in claim 2 rejection).
Regarding claim 5;
Cortes Mayol et al. further teaches that the first thickness is thinner than the second thickness (e.g. Fig. 1, see examiner markup in claim 1 rejection).
Regarding claim 6;
Cortes Mayol et al. further teaches that the SOI material comprising the first portion with the first thickness comprises fully depleted SOI material (e.g. Detailed description “…the fully depleted semiconductor layer 20 may be composed of any suitable material including, but not limited to, Si, SiGe, SiGeC, SiC, GaAs, InAs, InP, and other III/V or II/VI compound semiconductors.”).
Regarding claim 7;
Cortes Mayol et al. further teaches that the second portion comprises a drain side of the gate structure. (e.g. Fig. 1 ref 24; Detailed description “…the drain region 24…”).
Regarding claim 8;
Cortes Mayol et al. further teaches the second thickness comprises about 8 nm to about 25 nm (e.g. Detailed description “The drift region 32 includes an undoped epitaxial material 34 which extends (increases) the thickness of the drift region 32 (e.g., fully depleted semiconductor layer 20) to an additional 5 nm to about 15 nm, and preferably about 10 nm.”).
Regarding claim 10;
Cortes Mayol et al. further teaches that the second portion comprises a drift region on the drain side (e.g. Fig. 1 ref 32, Detailed description “A drift region 32 extends between the edge of the gate structure 30 and the drain region 24.”).
Regarding claim 11;
Cortes Mayol et al. further teaches that the first thickness comprises about 6 nm (e.g. Detailed description “the fully depleted semiconductor layer 20 will have an initial thickness of about 3 nm to about 15 nm, extending between a source region 22 and a drain region 24 (remote from a gate structure 30).”).
Claims 12-15, and 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhu et al. (US6939751B2)
Regarding claim 12;
Zhu et al. teaches a structure comprising: a semiconductor on insulator (SOI) layer comprising a first thickness (e.g. Fig. 1C ref 14) and a second thickness (Fig. 1C ref 14+16”), the first thickness being less than the second thickness (e.g. Detailed description “…the device 10″ of FIG. 1C is formed on an SOI (Silicon on Oxide) substrate composed of a thick BOX layer 12 upon which a thin silicon layer 14 has been formed, and the silicon layer 14 has been coated with a thin SiGe film 16″ and the set of RSD″ regions RS″/RD″ have been formed over the SiGe film 16″.”); a gate structure on the SOI layer over the first thickness (e.g. Fig. 1C ref 32, Detailed description “The trench has been filled with a gate conductor 32 which will serve as the gate electrode of the MOS FET device which is isolated from the silicon layer 14 by the gate dielectric layer GD…”); and a source region on a first side of the gate structure over the first thickness (e.g. Fig. 1C ref RS”, see examiner markup); a drain region on a second side of the gate structure over the second thickness (e.g. Fig. 1C ref RD”, see examiner markup); and at least one sidewall spacer on sidewalls of the gate structure and extending to the drain region (e.g. Fig. 1C ref 36”, Detailed description “The external sidewall spacers 36′, which cover the RSD′ regions 18′D, reach down into contact with the top surface of the SiGe layer 16 between the internal etch stopping film 28 on the inside and the RSD′ regions 18′ on the outside.”).
PNG
media_image4.png
376
920
media_image4.png
Greyscale
Regarding claim 13;
Zhu et al. further teaches that the at least one sidewall spacer comprises two sidewall spacers (e.g. Fig. 1C ref 30+36”, see examiner markup).
PNG
media_image5.png
376
920
media_image5.png
Greyscale
Regarding claim 14;
Zhu et al. further teaches that the two sidewall spacers comprise different dimensions (e.g. Fig. 1C, see examiner markup in claim 13 rejection).
Regarding claim 15;
Zhu et al. further teaches that the at least one sidewall spacer extends over both the first thickness and the second thickness of the SOI layer (e.g. Fig. 1C ref 36”, see examiner markup).
PNG
media_image6.png
376
920
media_image6.png
Greyscale
Regarding claim 18;
Zhu et al. further teaches that the second thickness comprises two layers of SOI layer. (e.g. Fig. 1C, see examiner markup in claim 12 rejection).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Cortes Mayol et al. (US10497803B2) for the following reasons:
Regarding claim 9;
Cortes Mayol et al. teaches the structure of claims 1 and 8 (see 102 rejections of claims 1 and 8).
Cortes Mayol et al. is silent to the second thickness comprises about 20 nm as claimed.
However, at the effective time of filing, it would have been obvious to someone having ordinary skill in the art to form the second thickness (e.g. Fig. 1 ref 32,24) taught in Cortes Mayol et al. to be the about 20nm thickness claimed because a prima facie case of obviousness exists where the claimed about 20nm thickness and prior art about 10nm to about 15nm thickness do not overlap but are close enough that one skilled in the art would have expected them to have the same properties (see MPEP § 2144.05 and Titanium Metals Corp. of America v. Banner, 778 F.2d 775, 227 USPQ 773 (Fed. Cir. 1985)).
In the absence of any indication of the criticality of the about 20nm thickness as disclosed in claim 9, it will be taken that the teaching of Cortes Mayol et al. reads on the instant claim.
Claims 16 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Zhu et al. (US6939751B2) in view of Cortes et al. (US11245032B2) for the following reasons:
Regarding claim 16;
Zhu et al. teaches the structure of claims 12, 13, and 15 wherein a second of the two sidewall spacers comprises an inner sidewall spacer over the first thickness and the at least one sidewall is an outer sidewall (e.g. see claim 12, 13, and 15 rejections).
Zhu et al. is silent to the outer sidewall extending over a drift region as claimed.
However, Cortes et al. teaches a multilayer drain-spacer structure extending over a drift region (e.g. Fig. 6 ref 108b,110,112; Detailed description “The multilayer drain spacer 126 may include at least three spacer layers that are substantially overlying the drift region 158.”).
At the effective time of filing, it would have been obvious to someone having ordinary skill in the art to modify the gate spacer structure taught in Zhu et al. to include the multi-layer drain-spacer structure extending over a drift region taught in Cortes et al. because it predictably spreads the field over a larger region leading to improved device operation properties (e.g. breakdown voltage, leakage current, hot-carrier reliability, dielectric reliability, etc.).
Regarding claim 19;
Zhu et al. teaches the structure of claim 12 (see claim 12 rejection).
Zhu et al. is silent to the first thickness comprising about 6 nm as claimed.
However, Cortes Mayol et al. teaches asymmetric FET structure for FDSOI devices with a fully depleted SOI layer with a thickness of about 6 nm (e.g. Detailed description “the SOI layer 106 has a thickness in the range of about 4 nm to about 12 nm.”).
At the effective time of filing, it would have been obvious to someone having ordinary skill in the art to form the first thickness of the SOI layer taught in Zhu et al. to be the about 6 nm thickness encompassed by the thickness range of the fully depleted SOI layer taught in Cortes et al. because it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Claim 17 is rejected under 35 U.S.C. 102(a)(1) as anticipated by Zhu et al. (US6939751B2) or, in the alternative, under 35 U.S.C. 103 as obvious over Zhu et al. (US6939751B2) in view of Cortes et al. (US11245032B2) for the following reasons:
Regarding claim 17;
Zhu et al. teaches the structure of claim 12 wherein that the first thickness comprises fully depleted semiconductor on insulator material (e.g. Detailed description “…SOI (Silicon on Oxide) substrate composed of a thick BOX layer 12 upon which a thin silicon layer 14 has been formed…”).
In the alternative, even though Zhu et al. does not explicitly teach that the first thickness comprises fully depleted semiconductor on insulator material, Cortes et al. teaches an asymmetric FET structure for FDSOI devices with a fully depleted SOI layer (e.g. Fig. 6 ref 106, Detailed description “The SOI layer 106 described herein may be a fully depleted SOI layer. The SOI layer 106 may be made of any semiconductor material, such as silicon (Si), germanium (Ge), silicon germanium (SiGe), or Si/SiGe.”).
At the effective time of filing, it would have been obvious to one having ordinary skill in the art to form the SOI layer taught in Zhu et al. from the fully depleted SOI material as taught in Cortes et al., since it has been held to be within the general skill of worker in the art to select known material on the basis of its suitability for the intended use (e.g. controlling channel thickness, threshold and carrier mobility properties, suppressing short channel effects, etc.) as a matter of obvious design variation and choice. In re Leshin, 125 USPQ 416.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM ROBERT MANN whose telephone number is (571)270-0210. The examiner can normally be reached Monday thru Thursday 0800-1800 EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at (469) 295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/WILLIAM ROBERT MANN/Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
Prosecution Insights