Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restriction
Applicant’s election without traverse of Species I in the reply filed on 6/22/2026 is acknowledged.
Claims 9-20 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 6/22/2026.
Foreign Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d) to foreign application KR 10-2023-0030408 filed on 03/08/2023 The foreign application is not in English. The certified copy of the foreign priority application has been received. Filing Dates for the Claims — All Claims Not Entitled to Priority DateTo be entitled to the filing date of the foreign priority application KR 10-2023-0030408 that is not in English, an English translation of the non-English language foreign application and a statement that the translation is accurate in accordance with 37 CFR 1.55 is required to perfect the claim for priority under 35 U.S.C. 119 (a)-(d). The foreign application must adequately support the claimed subject matter, meaning satisfy the written description and enablement requirements of 35 U.S.C. 112(a). See MPEP §§ 215 and 216. 37 C.F.R. 1.55(g)(3)(ii)-(iii). To demonstrate compliance with 35 U.S.C. 112(a), applicant should point to support for their claimed subject matter in their translations.
Claim Rejections 35 U.S.C. § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 5 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 5 states, in part “a width in the second direction of the second portion increases as a distance from the upper surface of the substrate in the vertical direction increases “in reference to the second fence portion (410 in Figs. 2 and 28). This directly contradicts para. 48 of the specification, which reads “a second width in the second direction of the second portion of the first fence pattern may decrease as a distance from the substrate 100 in the vertical direction increases.”
For examination purposes, this limitation is being interpreted to read “a width in the second direction of the second portion decreases as a distance from the upper surface of the substrate in the vertical direction increases.”
This rejection may be overcome by amending claim 5 by replacing increases with decreases in the relevant portion of the claim.
Claims 6-7 are also rejected under 112(b)
Appropriate correction is required.
Claim Rejections 35 U.S.C. § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3 and 8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sasaki (US20150060970A1), hereinafter referred to as Sasaki.
Regarding claim 1, Sasaki teaches a semiconductor device, comprising: a substrate (Sasaki, 2, Fig. 1B, para. 32); active patterns on the substrate (Sasaki, KM, Fig. 1A, 1B, para. 28); an isolation pattern on the substrate (Sasaki, I, Fig. 1B, para. 28), the isolation pattern covering sidewalls of the active patterns (Sasaki, Fig. 1B, each isolation pattern I separates an instance of the active region KM); gate structures (Sasaki, WL, Fig. 1A, 1B, paras. 30-31) extending in a first direction through upper portions of the active patterns and the isolation pattern, the first direction being substantially parallel to an upper surface of the substrate, and the gate structures being spaced apart from each other in a second direction (X in Figs. 1A and 1B) substantially parallel to the upper surface of the substrate and substantially perpendicular to the first direction; bit line structures (Sasaki, BL, Figs. 1A, 1B, paras. 30-32) on central portions of the active patterns and the isolation pattern, each of the bit line structures extending in the second direction, and the bit line structures being spaced apart from each other in the first direction (Sasaki, Fig. 1A); lower contact plugs (Sasaki, SC, Fig. 1B, para. 31) respectively on end portions of the active patterns; and upper contact plugs (Sasaki, C, Fig. 1B, paras. 32-36, contains a conductive layer (86) equivalent to the Ohmic contact (450) of the invention, an insulating layer (87) equivalent to the barrier pattern (465) of the invention, and electrodes (88 and 89) equivalent to metal pattern (475) of the invention) respectively on the lower contact plugs, wherein the active patterns are arranged in active pattern rows spaced apart from each other in the second direction (Sasaki, Fig. 1A, 1B, para. 29), and each of the active pattern rows includes some of the active patterns spaced apart from each other in the first direction and aligned with each other in the first direction (Sasaki, Fig. 1A), wherein each of the active patterns extends in a third direction at an acute angle with respect to each of the first direction and the second direction (Sasaki, Fig. 1A), and wherein a distance between lower surfaces of adjacent ones of the lower contact plugs in the second direction is not constant, and a distance between upper surfaces of the adjacent ones of the lower contact plugs in the second direction is substantially constant (Sasaki, Fig. 1A, 1B).
Regarding claim 2, Sasaki teaches the semiconductor device as claimed in claim 1, wherein opposite sidewalls in the second direction of each of the lower contact plugs have a positive slope or a negative slope with respect to the upper surface of the substrate (Sasaki, Fig. 1B).
Regarding claim 3, Sasaki teaches the semiconductor device as claimed in claim 1, wherein opposite sidewalls of a first one of two of the lower contact plugs adjacent to each other in the second direction have a positive slope with respect to the upper surface of the substrate (Sasaki, Fig. 1B), and opposite sidewalls of a second one of the two of the lower contact plugs have a negative slope with respect to the upper surface of the substrate (Sasaki, Fig. 1B).
Regarding claim 8, Sasaki teaches the semiconductor device as claimed in claim 1, wherein each of the lower contact plugs includes polysilicon doped with n-type impurities or p-type impurities (Sasaki, SC, 53, Fig. 43B, Para. 74, 53 is the lowest portion of the plug, SC, and is composed of a polysilicon film doped with N-impurities).
Claim rejections 35 U.S.C. § 102
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Sasaki as applied to claim 1 above, and further in view of Yokomichi (US Pub. 20150255465), hereinafter referred to as Yokomichi.
Regarding claim 4, Sasaki teaches the semiconductor device as claimed in claim 1, but does not teach wherein: a first fence pattern and a second fence pattern are alternately and repeatedly arranged between the lower contact plugs in the second direction, and the first fence pattern is on a first portion of the isolation pattern between central portions of ones of the active patterns adjacent to each other in the first direction, and the second fence pattern is on a second portion of the isolation pattern between end portions of ones of the active patterns adjacent to each other in the third direction.
Sasaki does teach a silver nitride film (Sasaki, 56, Fig. 1B, para. 34) on top of the isolation pattern (Sasaki, I, Fig. 1B) which is the equivalent to the second fence portion.
Furthermore, Yokomichi teaches a groove (Yokomichi, 14, Fig. 7B, para. 61) filled with a cap insulating film (Yokomichi, 17, Fig. 7B, para. 61) covering the word lines (Yokomichi, WL10a, Wl10b, Fig. 7B) with a groove (Yokomichi, 25, Fig. 7B, para. 10) which is filled with a spun on dielectric heated to turn it to a solid film.
Therefore it would have been obvious to one having ordinary skill in the art before the filing date of the invention to combine the device of Sasaki with the filled grooves of Yokomichi in order to depress contact resistance (Yokomichi, para. 72).
Claims 6 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Sasaki and Yokomichi as applied to claim 4 above, and further in view of Min et al.(US Pub. 20060068540) hereinafter referred to as Min.
Regarding claim 6, modified Sasaki teaches the semiconductor device as claimed in claim 4, but does not explicitly teach wherein each of the first fence pattern and the second fence pattern includes oxide or nitride.
Sasaki teaches as equivalent to the second fence pattern (Sasaki 56, Fig. 1B, para. 34) made up of a nitride film.
Yokomichi teaches a spun-on dielectric filling a groove which is equivalent to the first fence pattern, but is mute on the particular material.
However, Min teaches a spin-in dielectric which after curing can be converted fully to an oxide (Min, paras. 40-45).
Therefore it would have been obvious to one having ordinary skill in the art before the filing date of the invention to have combined the nitride film of Sasaki with the spun on dielectric of Yokomichi and the curing process of Min in order to provide good electrical isolation (Min, para. 12).
Regarding claim 7, modified Sasaki teaches the semiconductor device as claimed in claim 6, wherein the first fence pattern and the second fence pattern include different materials from each other (First fence pattern is an oxide as described by Yokomichi and Min above and the second fence pattern is a nitride film as described by Sasaki above).
Allowable Subject Material
Claim 5 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance:
Regarding claim 5, modified Sasaki teaches the semiconductor device as claimed in claim 4, but does not teach, nor does the prior art of record suggest wherein: the first fence pattern includes a first portion, a second portion, and a third portion sequentially stacked in a vertical direction substantially perpendicular to the upper surface of the substrate, a width in the second direction of the first portion increases as a distance from the upper surface of the substrate in the vertical direction increases, a width in the second direction of the second portion increases as a distance from the upper surface of the substrate in the vertical direction increases, and a width in the second direction of the third portion is substantially constant in the vertical direction, and a width in the second direction of the second fence pattern increases and then is substantially constant as a distance from the upper surface of the substrate in the vertical direction increases
Modified Sasaki does teach the semiconductor device as claimed in claim 4, wherein a width in the second direction of the second fence pattern increases (Sasaki, 56, Fig. 1B) and then decrease at a lesser rate than it increased as a distance from the upper surface of the substrate in the vertical direction increases, however the width is not substantially constant.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Park et al. (US Pub. 20220037251) teaches a semiconductor device with isolation structures on the gate structures.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIERAN M CUNNINGHAM whose telephone number is (571)272-9654. The examiner can normally be reached Mon-Fri 8:30-5:30.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at 5712703042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KIERAN M. CUNNINGHAM/Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893
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