DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim 12 has been amended.
Claims 1-20 have been examined.
The specification and claim objections in the previous Office Action have been addressed and are withdrawn, except as otherwise indicated below.
The § 112 rejections in the previous Office Action have not been addressed and are maintained.
Information Disclosure Statement
The Applicant has not submitted an Information Disclosure Statement.
Specification
The disclosure is objected to because of the following informalities.
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Appropriate correction is required. The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which Applicant may become aware in the specification.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the Applicant regards as the invention.
Claim 4 recites, at line 4, “the accelerator manager.” There is insufficient antecedent basis for this limitation in the claim. Claims 7, 9, and 10 include similar language and are similarly rejected.
Claims 5-10 are rejected as depending from rejected base claims and failing to cure the indefiniteness of those base claims.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 4, 11, 12, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over US Publication No. 2013/0160016 by Gummaraju et al. (hereinafter referred to as “Gummaraju”) in view of Non-patent literature “PIXEL: Photonic Neural Network Accelerator” by Shiflett et al. (hereinafter referred to as “Shiflett”).
Regarding claim 1, Gummaraju discloses:
an apparatus, comprising: a first accelerator of a first type, the first accelerator operable to perform operations …(Gummaraju discloses, at Figure 1 and related description, a heterogeneous computing system, which discloses an apparatus. Gummaraju also discloses, at Figure 1 and related description, CPU cores and GPU cores, which discloses a first accelerator of a first type operable to perform operations.);
a second accelerator of a second type, the second accelerator operable to perform the operations … (Gummaraju discloses, at Figure 1 and related description, CPU cores and GPU cores, which discloses a second accelerator of a second type operable to perform the operations.); and
a memory configured to store input data of a task … (Gummaraju discloses, at Figure 1 and related description, a memory hierarchy, which discloses memory configured to store input data of a task.).
Gummaraju does not explicitly disclose multiply and accumulate operations.
However, in the same field of endeavor (e.g., accelerators) Shiflett discloses:
multiply and accumulate operations (Shiflett discloses, at § 1, p. 474, multiply and accumulate operations.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Gummaraju to include multiply and accumulate operations, as disclosed by Shiflett, because multiply and accumulate operations are fundamental to a number of common and useful operations, such as matrix and vector multiplications.
Regarding claim 2, Gummaraju, as modified, discloses the elements of claim 1, as discussed above. Gummaraju also discloses:
an accelerator manager configured to: receive a request to perform the task (Gummaraju discloses, at Figure 1 and related description, a unified kernel scheduler, which schedules kernels, which discloses receiving a request to perform the task.);
analyze the input data to determine characteristics of the input data (Gummaraju discloses, at Figure 2 and related description, the unified kernel scheduler analyzes the kernel to be executed, which discloses analyze the input data to determine characteristics of the input data.);
assign the task to one of the first accelerator and the second accelerator based on the characteristics … (Gummaraju discloses, at Figure 2 and related description, the unified kernel scheduler assigns the kernel to the best suited processor, which discloses assign the task to one of the first accelerator and the second accelerator based on the characteristics.).
Gummaraju does not explicitly disclose wherein accelerators of the first type are configured with microring resonators as computing elements.
However, in the same field of endeavor (e.g., accelerators) Shiflett discloses:
microring resonators (Shiflett discloses, at § 1, p. 475, microring resonators.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Gummaraju to include microring resonators, as disclosed by Shiflett, because microring resonators can provide high power-efficiency. Id.
Regarding claim 4, Gummaraju, as modified, discloses the elements of claim 1, as discussed above. Gummaraju also discloses:
a third accelerator of a third type, the third accelerator operable to perform operations… (Gummaraju discloses, at Figure 1 and related description, CPU cores and GPU cores, which discloses a third accelerator of a third type. See, e.g., ¶ [0028], which discloses CPU cores and GPU cores that can include scalar, vector, and other special purpose units.);
wherein the accelerator manager is configured to rank energy efficiency of the first accelerator, the second accelerator, the third accelerator based on the characteristics to assign the task to one of the first accelerator, the second accelerator, and the third accelerator (Gummaraju discloses, at Figure 2 and related description, assigning kernels to processors based on determining the best match between compute kernels and processors based on performance and or energy consumption, which discloses wherein the accelerator manager is configured to rank energy efficiency of the first accelerator, the second accelerator, and the third accelerator based on the characteristics to assign the task to one of the first accelerator, the second accelerator, and the third accelerator.).
Gummaraju does not explicitly disclose the aforementioned third accelerator is operable to perform the operations of multiplication and accumulation.
However, in the same field of endeavor (e.g., accelerators) Shiflett discloses:
multiply and accumulate operations (Shiflett discloses, at § 1, p. 474, multiply and accumulate operations.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Gummaraju to include multiply and accumulate operations, as disclosed by Shiflett, because multiply and accumulate operations are fundamental to a number of common and useful operations, such as matrix and vector multiplications.
Regarding claim 11, Gummaraju discloses:
a method, comprising: performing, by an apparatus using a first accelerator of a first type, first operations …(Gummaraju discloses, at Figure 1 and related description, a heterogeneous computing system, which discloses an apparatus. Gummaraju also discloses, at Figure 1 and related description, CPU cores and GPU cores, which discloses a first accelerator of a first type operable to perform operations.);
performing, by the apparatus using a second accelerator of a second type, second operations … (Gummaraju discloses, at Figure 1 and related description, CPU cores and GPU cores, which discloses a second accelerator of a second type operable to perform the operations.);;
receiving, in a memory of the apparatus, input data of a task …; and receiving, in the apparatus, a request to perform the task (Gummaraju discloses, at Figure 1 and related description, a memory hierarchy, which discloses memory configured to store input data of a task and receiving the task.).
Gummaraju does not explicitly disclose multiply and accumulate operations.
However, in the same field of endeavor (e.g., accelerators) Shiflett discloses:
multiply and accumulate operations (Shiflett discloses, at § 1, p. 474, multiply and accumulate operations.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Gummaraju to include multiply and accumulate operations, as disclosed by Shiflett, because multiply and accumulate operations are fundamental to a number of common and useful operations, such as matrix and vector multiplications.
Regarding claim 12, Gummaraju, as modified, discloses the elements of claim 11, as discussed above. Gummaraju also discloses:
analyzing, by the apparatus, the input data to determine characteristics of the input data (Gummaraju discloses, at Figure 2 and related description, the unified kernel scheduler analyzes the kernel to be executed, which discloses analyze the input data to determine characteristics of the input data.);
assigning, by the apparatus, the task to one of the first accelerator and the second accelerator based on the characteristics … (Gummaraju discloses, at Figure 2 and related description, the unified kernel scheduler assigns the kernel to the best suited processor, which discloses assign the task to one of the first accelerator and the second accelerator based on the characteristics.);
performing, by the apparatus using a third accelerator of a third type, third operations … (Gummaraju discloses, at Figure 1 and related description, CPU cores and GPU cores, which discloses a third accelerator of a third type performing operations. See, e.g., ¶ [0028], which discloses CPU cores and GPU cores that can include scalar, vector, and other special purpose units.); and
ranking, by the apparatus, energy efficiency of the first accelerator, the second accelerator, and the third accelerator based on the characteristics to assign the task to one of the first accelerator, the second accelerator, and the third accelerator (Gummaraju discloses, at Figure 2 and related description, assigning kernels to processors based on determining the best match between compute kernels and processors based on performance and or energy consumption, which discloses wherein the accelerator manager is configured to rank energy efficiency of the first accelerator, the second accelerator, and the third accelerator based on the characteristics to assign the task to one of the first accelerator, the second accelerator, and the third accelerator.).
Gummaraju does not explicitly disclose the aforementioned third accelerator is operable to perform the operations of multiplication and accumulation.
However, in the same field of endeavor (e.g., accelerators) Shiflett discloses:
multiply and accumulate operations (Shiflett discloses, at § 1, p. 474, multiply and accumulate operations.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Gummaraju to include multiply and accumulate operations, as disclosed by Shiflett, because multiply and accumulate operations are fundamental to a number of common and useful operations, such as matrix and vector multiplications.
Regarding claim 18, Gummaraju discloses:
a non-transitory computer storage medium storing instructions which, when executed in a computing apparatus, cause the computing apparatus to perform a method, comprising: performing, using a first accelerator of a first type, first operations …(Gummaraju discloses, at Figure 1 and related description, a heterogeneous computing system, which discloses an apparatus. Gummaraju also discloses, at Figure 1 and related description, CPU cores and GPU cores, which discloses a first accelerator of a first type operable to perform operations. Gummaraju also discloses, at ¶ [0034], a computer readable medium embodiment.);
performing, using a second accelerator of a second type, second operations … (Gummaraju discloses, at Figure 1 and related description, CPU cores and GPU cores, which discloses a second accelerator of a second type operable to perform the operations.);
receiving, in a memory of the computing apparatus, input data of a task…; and receiving a request to perform the task (Gummaraju discloses, at Figure 1 and related description, a memory hierarchy, which discloses memory configured to store input data of a task and receiving the task.).
Gummaraju does not explicitly disclose multiply and accumulate operations.
However, in the same field of endeavor (e.g., accelerators) Shiflett discloses:
multiply and accumulate operations (Shiflett discloses, at § 1, p. 474, multiply and accumulate operations.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Gummaraju to include multiply and accumulate operations, as disclosed by Shiflett, because multiply and accumulate operations are fundamental to a number of common and useful operations, such as matrix and vector multiplications.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Gummaraju in view of Non-patent literature Accelerating “Deep Neural Network In-Situ Training With Non-Volatile and Volatile Memory Based Hybrid Precision Synapses” by Luo et al. (hereinafter referred to as “Luo”).
Regarding claim 3, Gummaraju, as modified, discloses the elements of claim 2, as discussed above. Gummaraju does not explicitly disclose accelerators of the second type are configured with synapse memory cells as computing elements.
However, in the same field of endeavor (e.g., accelerators) Luo discloses:
synapses (Luo discloses, at § 1.2, p. 1114, synapses, which discloses synapse memory cells.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Gummaraju to include synapses, as disclosed by Luo, because synapses can provide high computing accuracy and energy efficiency. See Luo, § 1.1, p. 1114.
Claims 5, 13, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Gummaraju in view of Shiflett in view of Luo in view of Non-patent literature “PUMA: A Programmable Ultra-efficient Memristor-based Accelerator for Machine Learning Inference” by Ankit et al. (hereinafter referred to as “Ankit”).
Regarding claim 5, Gummaraju, as modified, discloses the elements of claim 4, as discussed above. Gummaraju also discloses:
the first type, the second type, and the third type are different types from: … digital accelerators … (Gummaraju discloses, at Figure 1 and related description, CPU cores and GPU cores, which discloses different types of digital accelerators.).
Gummaraju does not explicitly disclose the aforementioned types are photonic accelerators, analog computing modules, and memristor accelerators.
However, in the same field of endeavor (e.g., accelerators) Shiflett discloses:
photonic accelerators (Shiflett discloses, at § 1, p. 475, microring resonators, which discloses photonic accelerators.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Gummaraju to include photonic accelerators, as disclosed by Shiflett, because photonic accelerators can provide high power-efficiency. Id.
Also, in the same field of endeavor (e.g., accelerators) Luo discloses:
analog computing modules (Luo discloses, at § 2.1., p. 1115, obtaining and converting analog output, which discloses analog computing modules.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Gummaraju to include analog computing modules, as disclosed by Luo, because analog processing can provide high energy efficiency and throughput. Id.
Also, in the same field of endeavor (e.g., accelerators) Ankit discloses:
memristor accelerators (Ankit discloses, at Abstract, a memristor crossbar accelerator.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Gummaraju to include memristors, as disclosed by Ankit, because memristor crossbars can provide high energy efficiency. Id.
Regarding claim 13, Gummaraju, as modified, discloses the elements of claim 12, as discussed above. Gummaraju also discloses:
the first type, the second type, and the third type are different types from: … digital accelerators … (Gummaraju discloses, at Figure 1 and related description, CPU cores and GPU cores, which discloses different types of digital accelerators.).
Gummaraju does not explicitly disclose the aforementioned types are photonic accelerators, analog computing modules, and memristor accelerators.
However, in the same field of endeavor (e.g., accelerators) Shiflett discloses:
photonic accelerators (Shiflett discloses, at § 1, p. 475, microring resonators, which discloses photonic accelerators.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Gummaraju to include photonic accelerators, as disclosed by Shiflett, because photonic accelerators can provide high power-efficiency. Id.
Also, in the same field of endeavor (e.g., accelerators) Luo discloses:
analog computing modules (Luo discloses, at § 2.1., p. 1115, obtaining and converting analog output, which discloses analog computing modules.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Gummaraju to include analog computing modules, as disclosed by Luo, because analog processing can provide high energy efficiency and throughput. Id.
Also, in the same field of endeavor (e.g., accelerators) Ankit discloses:
memristor accelerators (Ankit discloses, at Abstract, a memristor crossbar accelerator.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Gummaraju to include memristors, as disclosed by Ankit, because memristor crossbars can provide high energy efficiency. Id.
Regarding claim 19, Gummaraju, as modified, discloses the elements of claim 18, as discussed above. Gummaraju also discloses:
analyzing the input data to determine characteristics of the input data (Gummaraju discloses, at Figure 2 and related description, the unified kernel scheduler analyzes the kernel to be executed, which discloses analyze the input data to determine characteristics of the input data.);
assigning the task to one of the first accelerator and the second accelerator based on the characteristics … (Gummaraju discloses, at Figure 2 and related description, the unified kernel scheduler assigns the kernel to the best suited processor, which discloses assign the task to one of the first accelerator and the second accelerator based on the characteristics.)
performing, using a third accelerator of a third type, third operations … (Gummaraju discloses, at Figure 1 and related description, CPU cores and GPU cores, which discloses a third accelerator of a third type performing operations. See, e.g., ¶ [0028], which discloses CPU cores and GPU cores that can include scalar, vector, and other special purpose units.); and
ranking energy efficiency of the first accelerator, the second accelerator, and the third accelerator based on the characteristics to assign the task to one of the first accelerator, the second accelerator, and the third accelerator (Gummaraju discloses, at Figure 2 and related description, assigning kernels to processors based on determining the best match between compute kernels and processors based on performance and or energy consumption, which discloses wherein the accelerator manager is configured to rank energy efficiency of the first accelerator, the second accelerator, and the third accelerator based on the characteristics to assign the task to one of the first accelerator, the second accelerator, and the third accelerator.);
the first type, the second type, and the third type are different types from: … digital accelerators … (Gummaraju discloses, at Figure 1 and related description, CPU cores and GPU cores, which discloses different types of digital accelerators.).
Gummaraju does not explicitly disclose the aforementioned third accelerator is operable to perform the operations of multiplication and accumulation and the aforementioned types are photonic accelerators, analog computing modules, and memristor accelerators..
However, in the same field of endeavor (e.g., accelerators) Shiflett discloses:
multiply and accumulate operations (Shiflett discloses, at § 1, p. 474, multiply and accumulate operations.);and
photonic accelerators (Shiflett discloses, at § 1, p. 475, microring resonators, which discloses photonic accelerators.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Gummaraju to include multiply and accumulate operations, as disclosed by Shiflett, because multiply and accumulate operations are fundamental to a number of common and useful operations, such as matrix and vector multiplications.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Gummaraju to include photonic accelerators, as disclosed by Shiflett, because photonic accelerators can provide high power-efficiency. Id.
Also, in the same field of endeavor (e.g., accelerators) Luo discloses:
analog computing modules (Luo discloses, at § 2.1., p. 1115, obtaining and converting analog output, which discloses analog computing modules.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Gummaraju to include analog computing modules, as disclosed by Luo, because analog processing can provide high energy efficiency and throughput. Id.
Also, in the same field of endeavor (e.g., accelerators) Ankit discloses:
memristor accelerators (Ankit discloses, at Abstract, a memristor crossbar accelerator.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Gummaraju to include memristors, as disclosed by Ankit, because memristor crossbars can provide high energy efficiency. Id.
Allowable Subject Matter
Claims 6-10 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Claims 14-17 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Assigning tasks to accelerators based on characteristics of input data is known, as discussed above. However, doing so based on the particular characteristics recited in claims 6, 14, and 20 is not disclosed in a single reference. Nor would it have been obvious to combine references to arrive at the claimed invention absent impermissible hindsight. Accordingly, claims 6, 14, and 20 are allowable over the prior art. Claims 7-10, 15-17, and 20 are allowable over the prior art by virtue of their dependence.
Response to Arguments
On page 1 of the response filed July 29, 2026 (“response”), the Applicant argues, “The title has been amended to be more clearly indicative of the invention to which the claims are directed.”
Though fully considered, the Examiner respectfully disagrees. The amended title, “HETEROGENEOUS ACCELERATOR SUB-SYSTEM,” is not sufficiently descriptive of the claimed invention. Heterogeneous accelerator subsystems encompasses an entire field of invention. Accordingly, the Applicant’s arguments are deemed unpersuasive. The Examiner suggests, “REDUCING ENERGY EXPENDITURE IN A HETEROGENEOUS ACCELERATOR SUB-SYSTEM BY USING DYNAMIC ASSIGNMENT BASED ON DETERMINED CHARACTERISTICS OF INPUT DATA,” or something similar.
On page 11 of the response the Applicant argues, “he prior art references, Gummaraju (2013/0160016) and Shiflett (“PIXEL: Photonic Neural Network Accelerator”), fail to teach or disclose techniques of reducing the energy expenditure in computations of multiplication and accumulation, as claimed by Applicant. For example, Gummaraju (2013/0160016) is limited to disclosing allocating compute kernels to different types of processors, such as CPUs and GPUs, in a heterogeneous computer system. These include comparing a kernel profile of a compute kernel to respective processor profiles of a plurality of processors in a heterogeneous computer system, selecting at least one processor from the plurality of processors based upon the comparing, and scheduling the compute kernel for execution in the selected at least one processor. The prior art reference Shiflett (“PIXEL: Photonic Neural Network Accelerator”), fails to rectify the shortcomings of Gummaraju. Shiflett is limited to disclosing a mixed-signal hardware accelerator designed to execute Deep Neural Network (DNN) inferences by leveraging silicon photonics to replace power-hungry, traditional electronic circuits. As disclosed in Shiflett, by using light instead of electricity to transmit data and perform calculations, PIXEL improves computing performance-per-Watt and reduces data distribution bottlenecks. Accordingly, the prior art references, Gummaraju (2013/0160016) and Shiflett (“PIXEL: Photonic Neural Network Accelerator”), fail to teach or disclose techniques of reducing the energy expenditure in computations of multiplication and accumulation, as claimed by Applicant.”
Though fully considered, the Examiner respectfully disagrees. The Applicant is arguing features that are not claimed. The claims do not recite reducing energy expenditure. Furthermore, both Gummaraju and Shiflett explicitly disclose reducing energy consumption, Gummaraju at ¶ [0062] and Shiflett at the Abstract. Accordingly, the Applicant’s arguments are deemed unpersuasive.
Conclusion
THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAWN DOMAN whose telephone number is (571)270-5677. The examiner can normally be reached on Monday through Friday 8:30am-6pm Eastern Time.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached on 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHAWN DOMAN/
Primary Examiner, Art Unit 2183
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