DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 10-11 are objected to because of the following informalities:
Claim 10 recites the limitation "the second capacitor" in line 1. There is insufficient antecedent basis for this limitation in the claim.
Claims 10 and 11 recite the limitation "the second transistor" in line 3 and line 1, 3. respectively. There is insufficient antecedent basis for this limitation in the claim. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 11-15 and 19-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Jiang et al. Patent No. US 11,411,396.
Regarding claim 19, Jiang discloses a trigger circuit for controlling an electrostatic discharge (ESD) protection switch; the trigger circuit [Fig. 4] comprising:
an input terminal [Fig. 4, terminal S] arranged to be connected with a first conduction terminal of the ESD protection switch [Fig. 2, source of the protection switch 30];
an output terminal [Fig. 4, G terminal] arranged to control a control terminal of the ESD protection switch [Fig. 4, gate terminal of 30];
a first diode function biased from the output terminal to the input terminal [Fig. 4, parasitic diode of transistor 113];
a second diode function biased from the input terminal to the output terminal and connected in series with the first diode function [Fig. 4, parasitic diode of transistor 114; two parasitic diodes of 113 and 114 would be connected in series];
a first transistor [Fig. 4, 113] having two conduction terminals and a control terminal; wherein the two conduction terminals of the first transistor are arranged in parallel with the first diode function [Fig. 4, drain source terminals of 113 are inherently connected in parallel with the parasitic diode of the transistor], and wherein the control terminal of the first transistor is configured to control a conduction path between the two conduction terminals of the first transistor;
a first timer circuit [Fig. 4, resistor 111, capacitor 112] comprising a first resistor connected in series between the control terminal of the first transistor and the output terminal [Fig. 4, 111 is connected in series between the gate of 113 and the output terminal at G]; and
a first capacitor [Fig. 4, 112] connected in series between the control terminal of the first transistor and the input terminal;
wherein the second diode function is connected in series between the input terminal and one of the two conduction terminals of the first transistor; wherein the control terminal of the first transistor is coupled via the first capacitor to the input terminal, so that a rising voltage at the input terminal due to an ESD event triggers the control terminal of the first transistor to activate the conduction path between the two conduction terminals of the first transistor; and wherein the first capacitor is arranged to be discharged through the first resistor to the output terminal so that, when the first capacitor is discharged below a first threshold of the first transistor, the control terminal of the first transistor deactivates the conduction path between the two conduction terminals of the first transistor [col. 5 lines 65 – col. 6 lines 45].
Regarding claim 11, Jiang discloses that the second transistor is an NMOS transistor. However, Jiang does not disclose that the second transistor is a laterally-diffused metal oxide semiconductor or an extended drain field-effect transistor. It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to replace a NMOS transistor with a LDMOS transistor, for the known benefits of higher breakdown voltage and enhanced power handling and efficiency in applications requiring high voltage and high-power capabilities.
Regarding claim 12, Jiang discloses that the first diode function is implemented using a parasitic diode of the first transistor [Fig. 4, transistor 113 has an inherent parasitic diode].
Regarding claim 13, Jiang discloses that the second transistor is an NMOS transistor. However, Jiang does not disclose that the second transistor is a laterally-diffused metal oxide semiconductor or an extended drain field-effect transistor. It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to replace a NMOS transistor with a LDMOS transistor, for the known benefits of higher breakdown voltage and enhanced power handling and efficiency in applications requiring high voltage and high-power capabilities.
Regarding claim 14, 15, Jiang discloses that the first transistor is an NMOS transistor. However, Jiang does not disclose that the first transistor is a laterally-diffused metal oxide semiconductor or an extended drain field-effect transistor. It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to replace a NMOS transistor with a LDMOS transistor, for the known benefits of higher breakdown voltage and enhanced power handling and efficiency in applications requiring high voltage and high-power capabilities.
Regarding claim 20, Jiang discloses that the second diode function is implemented using a parasitic diode of the second transistor [Fig. 4, transistor 114 has an inherent parasitic diode].
Allowable Subject Matter
Claims 1-6, 8-9, and 16-18 are allowed.
The following is an examiner’s statement of reasons for allowance of claim 1: The prior art does not disclose that the second diode function is implemented using a separate second diode, and wherein the first capacitor is connected to a cathode of the separate second diode. This feature in combination with the rest of the claim limitations is not anticipated or rendered obvious by the prior art of record.
Response to Arguments
Applicant's arguments filed 11/21/2025 have been fully considered but they are not persuasive.
The Applicant comments on page 8 of the REMARKS that claim 19 includes the recitations of allowed dependent claim 9 and independent base claim 1. The Examiner points out that newly added claim 19 is same as previously rejected claim 1.
Claims 10 and 11 are still objected due to insufficient antecedent basis as shown above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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DHARTI PATEL
Primary Examiner
Art Unit 2836
/DHARTI H PATEL/ Primary Examiner, Art Unit 2838