DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions Acknowledged
Applicant’s election, with traverse, of Species 4 (shown in Figs. 14-22) of Species Group I (where a capacitor is used as a storage element) in the Response to Restriction Requirements filed 05/11/26 has been acknowledged. Traversal was based on an intention of the Applicant to have initially non-examined claims (due to the choice in the Response) to be considered for rejoinder, upon allowance claims directed to the chosen Species of the Species Group.
Applicant wrote that Claims 1-13 and 15-20 belong to the chosen invention, and slightly amended Claims 8 and 20, together with the Response. However, the limitations of Claim 14: “the shielding pattern includes a conductive material, and the shielding insulation layer has the air gap” - is read on Fig. 16 belonging to the chosen species (see paragraphs 0158-160 of the published application US 2025/0081441), but limitations of Claim 16 and 17 are read on Species 5 and 6 (Figs. 23-24 and 25-26, accordingly).
Status of Claims
Claims 16-17 are withdrawn from further consideration as being drawn to a nonelected invention.
Claims 1-15 and 18-20 are examined on merits herein.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 8, 11-15, and 18-19 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
In re Claim 8: Claim 8 recites: “an extension portion between the bit lines and extending in the second direction”. The recitation is rejected for a lack of antecedent bases, e.g., for using article “the” with words: “bit lines”, since earlier Claim 8, or Claim 1, on which Claim 8 depends, do(es) not recite: “bit lines”, but recite: “a/the bit line”. Appropriate correction is required.
In re Claim 11: Lines 14-15 of Claim 11 recite: “a second activation pattern placed the back gate electrode and the second word line”. The recitation is unclear, and appropriate correction is required.
For this Office Action, based on the specification of the application, the recitation was interpreted as: “a second activation pattern placed between the back gate electrode and the second word line”.
In re Claims 12-15 and 18-19: Claims 12-15 and 18-19 are rejected under 35 U.S.C. 112(b) due to dependency on Claim 11.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
As far as Claim 11 is understood, Claims 1, 2, 9, and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2023/0363143).
In re Claim 1, Lee teaches a semiconductor memory device (Abstract) comprising (Figs. 1-2):
a substrate 200 (paragraph 0024);
a bit line BL (paragraph 0024) on the substrate, and extending in a second direction D2 different from a first direction D1 (as in Fig. 1A);
a shielding structure 171/173/175 (paragraphs 0030, 0031) on the substrate, adjacent to the bit line BL (Fig. 1A), and extending in the second direction D2;
a back gate electrode BG (paragraph), with its capping pattern 115 (Fig. 1C, Figs. 2, paragraph 0032) on the bit line BL and the shielding structure 171/173/175 (Fig. 1B) and extending in the first direction D1 (Fig. 1A);
a first word line WL1 (Figs. 1B, 2A, paragraph 0039) on the bit line BL and the shielding structure 171/173/175, extending in the first direction D1 (Fig. 1A) and on one side (a left side) of the back gate electrode BG (with its capping layer 115) in the second direction (Fig. 1A),
and a second word line WL2 (Figs. 1B, 2A, paragraph 0039) on the bit line BL and the shielding structure 171.173.175 and on another side of the back gate electrode BG; and
a first activation pattern AP1 (Figs. 1B, 2A, paragraph 0034) on the bit line BL and between the back gate electrode BG and the first word line WL and
a second activation pattern AP2 (Figs. 1B, 2A, paragraph 0034) between the back gate electrode BG and the second word line WL2,
wherein the shielding structure 171/173/175 includes a low-dielectric material 173 (paragraph 0170)
In the embodiment of Figs. 1-2, Lee does not teach a peripheral gate structure disposed on the substrate such that the bit line and the shielding structure are disposed on the peripheral gate structure. But in an embodiment of Fig. 8, Lee teaches a memory device comprised a peripheral circuit PS (paragraph 0104) at least partially disposed on substrate 200, where a part of the substrate 200 under portions belonging to the peripheral circuit may be called a substrate and an upper part of the substrate with a remaining part of PS may be called a peripheral gate, as clearly comprising peripheral gates. Lee further teaches that in the structure of Fig. 8, bit lines BL and a shielding structure 171/173/175 are disposed on the peripheral circuit.
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the structure of Figs. 1-2 by disposing the peripheral gate structure on the substrate and under the bit line and the shielding structure when it is desirable to incorporate a peripheral circuit under the memory device.
In re Claim 2, Lee teaches the semiconductor memory device of Claim 1 as cited above, including the low-dielectric material, but does not explicitly teach that a dielectric constant of the low-dielectric material is less than that of silicon oxide (SiO₂). However, there are more than thousands of applications in the USPTO database alone identified a low-dielectric material (with a more common name –a low-k dielectric) as a dielectric having a dielectric constant lower than that of silicon oxide – see at least paragraph 0049 of Bae et al. (US 2013/0026439) as a common knowledge in the art on the subject.
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to use a low-dielectric material 173 in the Lee device with a dielectric constant being less than that of the silicon oxide, based on the common knowledge in the art.
In re Claim 9, Lee teaches the semiconductor memory device of Claim 1 as cited above, wherein (Figs. 1-2) the first activation pattern AP1 and the second activation pattern AP2 include a monocrystalline semiconductor material (paragraph 0035).
In re Claim 11, Lee teaches a semiconductor memory device (Abstract) comprising (Figs. 1-2):
a substrate 200 (paragraph 0024);
a bit line BL (paragraph 0024) on the substrate 200, and extending in a second direction D2 different from a first direction Da (as in Fig. 1A);
a shielding structure 171/173/175 (paragraphs 0030-0031) adjacent to the bit line (as in Fig. 1A) on the substrate 200 and extending in the second direction D2;
a back gate electrode BG (paragraph 0034) on the bit line BL and the shielding structure 171/173/175 and extending in the first direction D1 (Fig. 1A);
a first word line WL1 (Figs. 1A, 1B, 2A, paragraph 0039) on the bit line BL and the shielding structure 171/173/175, extending in the first direction and on one side of the back gate electrode in the second direction D2 (Fig. 1A),
and a second word line WL2 (Figs. 1A, 1B, 2A, paragraph 0039) on the bit line BL and the shielding structure 171/173/175 and on another side of the back gate electrode BG; and
a first activation pattern AP1 (Figs. 1B, 2A, paragraph 0034) on the bit line BL between the back gate electrode BG and the first word line WL1 and
a second activation pattern AP2 (Figs. 1B, 2A, paragraph 0034) placed (“between” – as interpreted) the back gate electrode BG and the second word line WL2,
wherein the shielding structure 171/173/175 has an air gap (paragraph 0030).
In the embodiment of Figs. 1-2, Lee does not teach a peripheral gate structure disposed on the substrate such that the bit line and the shielding structure are disposed on the peripheral gate structure. But in an embodiment of Fig. 8, Lee teaches a memory device comprised a peripheral circuit PS (paragraph 0104) at least partially disposed on substrate 200, where a part of the substrate 200 under portions belonging to the peripheral circuit may be called a substrate and an upper part of the substrate with a remaining part of PS may be called a peripheral gate, as clearly comprising peripheral gates. Lee further teaches that in the structure of Fig. 8, bit lines BL and a shielding structure 171/173/175 are disposed on the peripheral circuit.
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the structure of Figs. 1-2 by disposing the peripheral gate structure on the substrate and under the bit line and the shielding structure when it is desirable to incorporate a peripheral circuit under the memory device.
Claims 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Jain et al. (US 2003/0036280).
In re Claim 3, Lee teaches the semiconductor memory device of Claim 2 as cited above, including the low-dielectric material, but does not teach that the low-dielectric material includes a hydrocarbon compound, carbide, carbon, or a combination thereof.
Jain teaches such low-dielectric material as including carbon – e.g., carbon-doped silicon oxide (paragraph 0017).
Lee and Jain teach analogous arts directed to low-k materials, and one of ordinary skill in the art before the effective date of filing the application would have had a reasonable expectation of success in modifying the Lee device in view of the Jain teaching, since they are from the same field of endeavor as related to low-k dielectrics, and Jain low-k dielectric successfully functions.
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the Lee device by substituting his not fully disclosed low-dielectric material with carbon-doped silicon oxide of Jain, in order to enabling this material. In addition, See MPEP 2144.05 and MPEP 2143 on a Conclusion of Obviousness: KSR Rational (B): Simple Substitution of One Known Element for Another to Obtain Predictable Results.
In re Claim 4, Lee teaches the semiconductor memory device of Claim 2 as cited above, including the low-dielectric material, but does not teach that the low-dielectric material includes at least one of carbon doping silicon oxide (SiOC) or porous silicon oxide.
Jain teaches such low-dielectric material as carbon-doped silicon oxide (paragraph 0017).
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the Lee device by substituting his not fully disclosed low-dielectric material with carbon-doped silicon oxide of Jain, in order to enabling this material. In addition, See MPEP 2144.05 and MPEP 2143 on a Conclusion of Obviousness: KSR Rational (B): Simple Substitution of One Known Element for Another to Obtain Predictable Results.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Hwang et al. (US 2020/0135699).
In re Claim 10, Lee teaches the semiconductor memory device of Claim 1, further comprising (Fig. 8): a bonding layer – of bonding pads (paragraph 0105) between the peripheral gate structure 0 being a part of PS) - and the bit line BL.
Lee does not teach that the bonding layer is an insulation bonding layer.
Hwang teaches (Fig. 2, paragraphs 0028, 0031, 0050) a hybrid bonding comprised a bonding interface in which metal pads 152 and 154 are bond together as well as insulation layers 162 and 164 are bond together.
Lee and Hwang teach analogous arts related to bonding two layers and one of ordinary skill in the art before the effective date of filing the application would have had a reasonable expectation of success in modifying the Lee device in view of the Hwang teaching, since they are from the same field of endeavor (as directed to bonding), and Hwang created a successfully operated device.
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the Lee device by using a hybrid bonding and bonding together not only metal pads but also interfacing insulating layers, where a more reliable bonding is desirable.
Allowable Subject Matter
Claim 20 is allowed.
Claims 5, 8, 12, and 19 contain allowable subject matter, while Claims 6-7 depend on Claim 5, and Claims 13, 15, and 18 depend on Claim 12. Accordingly, this Office Action objects Claims 5-7. The claims would be allowed if Claim 5 incorporates all limitations of Claim 1, while Claim 6-7 would depend on the amended Claim 5.
Reason for Identification of Allowable Subject Matter
Re Claim 20: The prior arts of record, alone or in combination, fail(s) to anticipate or render obvious such limitation of Claim 20 as: “shielding insulation layer placed between the shielding pattern and the bit line”, in combination with other limitations of the claim.
Re Claim 5: The prior arts of record, alone or in combination, fail(s) to anticipate or render obvious such limitation of Claim 5 as: “a shielding insulating layer between the shielding pattern and the bit line”, in combination with all limitations of Claim 1, on which Claim 5 depends.
Re Claim 8: The prior arts of record, alone or in combination, fail(s) to anticipate or render obvious such limitation of Claim 8 as: “an extension portion between bit lines and extending in the second direction”,
Re Claim 12: The prior arts of record, alone or in combination, fail(s) to anticipate or render obvious such limitation of Claim 12 as: “a shielding insulation layer between the shielding pattern and the bit line”, in combination with all limitations of Claim 11, as interpreted.
Re Claim 19: 1 The prior arts of record, alone or in combination, fail(s) to anticipate or render obvious such limitation of Claim 19 as: “the air gap extends in the third direction and overlaps the metal pattern in the first direction”, in combination with other limitations of Claim 19 and with all limitations of Claim 11 as interpreted.
The prior arts of record, in addition to the prior arts cited by the current Office Action above, also include: Karda et al. (US 2019/0067298), Lee et al. (US 2022/0102352), and Lee et al. (US 2023/0055147).
Conclusion
Any inquiry concerning this communication should be directed to GALINA G YUSHINA whose telephone number is 571-270-7440. The Examiner can normally be reached between 8 AM - 7 PM Pacific Time (Flexible).
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The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
A fax phone number of Galina Yushina is 571-270-8440.
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/GALINA G YUSHINA/Primary Patent Examiner, Art Unit 2811, TC 2800,
United States Patent and Trademark Office
E-mail: galina.yushina@USPTO.gov
Phone: 571-270-7440
Date: 06/17/26
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