DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Amendment
The following office action is in response to the amendment and remarks filed on 7/20/26.
Applicant’s amendment to claims 1 is acknowledged.
Applicant’s cancellation of claims 11 is acknowledged.
Claims 1-10 and 12-17 are pending and subject to examination at this time.
Relevant Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Inayoshi, US Patent No. 4803543 (e.g. See fig. 4, protective film 11 helps to prevent corrosion.)
Response to Arguments
Applicant's arguments filed 7/20/26 have been fully considered but they are not persuasive.
MPEP § 2141, Examination Guidelines for Determining Obviousness Under 35 U.S.C. 103 indicates:
“A person of ordinary skill in the art is also a person of ordinary creativity, not an automaton.” KSR, 550 U.S., 82 USPQ2d at 1397. “[I]n many cases a person of ordinary skill will be able to fit the teachings of multiple patents together like pieces of a puzzle.” Office personnel may also take into account “the inferences and creative steps that a person of ordinary skill in the art would employ.”, 82 USPQ2d at 1396. (Emphasis added.)
MPEP 2123, Rejection Over Prior Art’s Broad Disclosure Instead of Preferred Embodiments indicates:
I. Patents Are Relevant As Prior Art For All They Contain:
"The use of patents as references is not limited to what the patentees describe as their own inventions or to the problems with which they are concerned. They are part of the literature of the art, relevant for all they contain." In re Heck, 699 F.2d 1331, 1332-33, 216 USPQ 1038, 1039 (Fed. Cir. 1983)
II. Nonpreffered And Alternative Embodiments Constitute Prior Art:
Disclosed examples and preferred embodiments do not constitute a teaching away from a broader disclosure or nonpreferred embodiments. In re Susi, 440 F.2d 442, 169 USPQ 423 (CCPA 1971).
Saitoh teaches at col 2, ln 27–39, :
In order to prevent a plastic package from a crack, Japanese Patent Publication of Unexamined Application (JPA) No. 5-275598 proposes to coat the die pad with a thin inorganic film. The inorganic thin film is formed of aluminum oxide, silicon oxide, titanium oxide or chromium oxide, and enhances the adhesion between the die pad and a plastic package. The inorganic thin film prevents the die pad and the plastic package from separation, and, accordingly, is effective against the crack. However, the inorganic thin film is insufficient to a lead-frame for a large semiconductor chip, because the wide die pad is causative of large thermal stress. This is the first problem inherent in the prior art semiconductor device. (Emphasis added.)
Saitoh’s teaching that the inorganic thin film (e.g. aluminum oxide) is “insufficient to a lead-frame for a large semiconductor chip” does not constitute a teachings away from preferred embodiments. For example, claim 1 does not require a specific size of the semiconductor chip. With the goal towards further minituarization of semiconductor devices, it would be obvious to one of ordinary skill in the art, who is also a person of ordinary creativity, to apply the inorganic thin film (e.g. aluminum oxide) to increasingly smaller semiconductor chips. One of ordinary skill in the art has motivation to apply the inorganic thin film (e.g. aluminum oxide) to smaller semiconductor chips because Saitoh teaches it is “effective against the crack”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 12, 15 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Saitoh, US Patent No. 5,883,439.
Saitoh teaches:
1. A semiconductor device comprising (see fig. 4):
a die pad (11a);
a semiconductor element (10) which is disposed on the die pad;
an element joining layer (12) which is formed between the die pad and the semiconductor element and joins the semiconductor element to the die pad;
a sealing resin (15) which covers the die pad, the semiconductor element, and the element joining layer; and
a barrier layer (21) which is formed at a boundary portion between the sealing resin and the element joining layer…See Saitoh at col 1-5, ln 1–67, figs. 1-7.
Regarding claim 1:
In the embodiment shown in fig. 4, Saitoh is silent the barrier layer blocks corrosive ions derived from the sealing resin.
However, it would have been obvious to one of ordinary skill in the art that in Saitoh’s fig. 4, the barrier layer “blocks corrosive ions derived from the sealing resin” because Saitoh teaches in the Background of the Invention in fig. 2C that water vapor can penetrate along the crack (6c) in the sealing resin (3). See Saitoh at col 2, ln 1–20.
Further regarding claim 1:
In the embodiment shown in fig. 4, Saitoh does not expressly teach:
wherein the barrier layer includes an aluminum oxide layer.
However, it would have been obvious to one of ordinary skill in the art to form “wherein the barrier layer includes an aluminum oxide layer” because Saitoh teaches in the Background of the Invention that aluminum oxide is effective against the crack. See Saitoh at col 2, ln 28–39.
Furthermore, it is within the general skill of a worker in the art to select known material on the basis of its suitability for the intended purpose as a matter of obvious design choice. In re Leshin, 125 USPQ 416. See MPEP § 2144.07, Art Recognized Suitability for an Intended Purpose.
Saitoh further teaches:
12. The semiconductor device according to claim 1, wherein the element joining layer includes an element joining layer which contains a solder alloy, col 6, ln 15–17.
15. The semiconductor device according to claim 1, wherein the die pad includes a die pad which contains Cu, col 3, ln 32–47.
Regarding claim 17:
Saitoh is silent wherein the barrier layer has a thickness of not less than 50 nm and not more than 10 μm.
Saitoh teaches the barrier layer addresses cracking in the sealing layer under heat cycling in fig. 6. One of ordinary skill in the art would find it obvious to optimize the thickness of the barrier in order to discover the optimum or workable ranges by routine experimentation to minimize cracking in the sealing layer.
See MPEP § 2144.05, Obviousness of Ranges:
[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)
“Generally, differences in concentration or temperature will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such concentration or temperature is critical.” (Emphasis added.)
In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969)…Claimed elastomeric polyurethanes which fell within the broad scope of the references were held to be unpatentable thereover because, among other reasons, there was no evidence of the criticality of the claimed ranges of molecular weight or molar proportions. (Emphasis added.)
Claim(s) 2-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Saitoh, as applied to claim 1 above, in view of Yoshinaga et al., US Publication No. 2015/0364587 A1.
Regarding claim 2:
Saitoh teaches all the limitations of claim 1 above, and further teaches:
the sealing resin (15) has an end surface which forms a peripheral outer shape of the sealing resin, fig. 4.
Saitoh does not expressly teach:
the die pad includes a protruding portion which protrudes outside the sealing resin, with the end surface of the sealing resin given as a starting point.
In an analogous art, Yoshinaga teaches:
(see fig. 8) the sealing resin (MR) has an end surface which forms a peripheral outer shape of the sealing resin, and
the die pad (DP) includes a protruding portion (e.g. see fig. 8 annotated below) which protrudes outside the sealing resin (MR), with the end surface of the sealing resin given as a starting point, para. [0074] – [0088].
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Saitoh further teaches:
3. The semiconductor device according to claim 2, wherein (see fig. 7 annotated below)
the sealing resin (15) has an inner surface which faces the semiconductor element (10), the element joining layer (12), and the die pad (11a),
a gap (30a, 30b) which extends from…the sealing resin (15) toward the semiconductor element (10) is formed at least between the inner surface of the sealing resin (16) and the die pad, (11a) and a part of the barrier layer (22) is held such that the part of the barrier layer is in close contact with the inner surface of the sealing resin in a state of floating from the die pad (11a) via the gap.
Saitoh does not expressly teach “the end surface”
Yoshinaga teaches “the end surface” as applied to claim 2 above.
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Saitoh further teaches:
4. The semiconductor device according to claim 3, wherein (see fig. 4 and fig. 7 annotated above)
the gap (30a) extends from…the sealing resin (15) along the die pad (11a) and the element joining layer (12) and has an end portion on the element joining layer (12), and
the barrier layer (22) includes a separation portion in a state of floating from the die pad (11a) and the element joining layer (12) via the gap (30a) and a holding portion (e.g. proximate the right bottom corner of the chip) which is held between the sealing resin and the element joining layer at a portion between a lower edge corner of the semiconductor element and the end portion of the gap.
Saitoh does not expressly teach “the end surface”
Yoshinaga teaches “the end surface” as applied to claim 2 above.
Saitoh further teaches:
5. The semiconductor device according to claim 4, wherein (see fig. 4 and fig. 7 annotated above)
the element joining layer (14) includes integrally a main body portion (e.g. central portion in fig. 4) which is held between the die pad (11a) and the semiconductor element (10) and a peripheral portion (e.g. edge portion in fig. 7) which is formed around the semiconductor element, the peripheral portion having an inclined surface (e.g. see angle labeled in fig. 7 above) which is inclined with respect to the die pad, and
the gap (30a) is formed such that the gap bends upward along a front surface of the die pad (11a) and the inclined surface of the element joining layer in a cross-sectional view.
Regarding claim 6:
Saitoh is silent on a numerical value for the angle labeled in fig. 7 above.
However, it would have been obvious to one of ordinary skill in the art “wherein the inclined surface of the element joining layer is inclined at an angle of not less than 5° and not more than 45° in relation to the front surface of the die pad” because the drawing teaches or suggests the angle is an acute angle not less than 5° and not more than 45°.
MPEP § 2125, Drawings as Prior Art, indicates:
” Drawings and pictures can anticipate claims if they clearly show the structure which is claimed. In re Mraz, 455 F.2d 1069, 173 USPQ 25 (CCPA 1972)…When the reference is a utility patent, it does not matter that the feature shown is unintended or unexplained in the specification. The drawings must be evaluated for what they reasonably disclose and suggest to one of ordinary skill in the art. In re Aslanian, 590 F.2d 911, 200 USPQ 500 (CCPA 1979). See MPEP § 2121.04 for more information on prior art drawings as “enabled disclosures.”
Regarding claim 7:
Saitoh is silent the semiconductor element includes a power semiconductor.
Yoshinaga further teaches:
7. The semiconductor device according to claim 1, wherein (see fig. 8)
the semiconductor element (CP) includes a power semiconductor which has a first principal surface (e.g. top surface) and a second principal surface (e.g. bottoms surface) at the opposite side thereof and in which a gate electrode (PDG) and a source electrode (PDE) are formed in the first principal surface and a drain electrode (BE) which is electrically connected to the die pad (DP) via the element joining layer (BD1) is formed in the second principal surface, para. [0074] – [0088].
Yoshinaga further teaches:
8. The semiconductor device according to claim 7, wherein
the die pad (DP) has a loading surface which is loaded with the semiconductor element (CP) and a mounting surface (e.g. see protruding portion annotated in fig. 8 above; also see protruding portion of DP on right side in fig. 5) which is exposed from the sealing resin (MR) as a drain terminal (e.g. BE is a collector electrode) at the opposite side of the loading surface,
the semiconductor device further comprising:
a source lead terminal (LD2) which is electrically connected to the source electrode (PDE) inside the sealing resin and exposed from the sealing resin; and
a gate lead (LD1_ terminal which is electrically connected to the gate electrode (PDG) inside the sealing resin and exposed from the sealing resin, para. [0074] – [0088], figs. 5 and 8.
Saitoh further teaches:
9. The semiconductor device according to claim 7, wherein the semiconductor element is formed in a quadrilateral shape, one side of which is not less than 3.0 mm and not more than 8.0 mm (e.g. 5.94 mm), col 6, ln 1–5.
Regarding claim 9:
Yoshinaga also teaches the semiconductor element (CP) is formed in a quadrilateral shape in fig. 5.
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Saitoh with the teachings of Yoshinaga because “…the current flowing between a pad provided on the main surface side and a back surface electrode provided on the back surface side can be controlled by the power semiconductor elements formed in the semiconductor chip. For this reason, such a semiconductor chip can be used for a switching element through which a large current flows.” See Yoshinaga at para. [0003], also see para. [0070] – [0071].
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Saitoh, as applied to claim 1 above, in view of Hashizume et al., US Publication No. 2018/0096961 A1.
Regarding claim 10:
Saitoh teaches all the limitations of claim 1 above, but is silent:
wherein the die pad has a thickness of not less than 1.0 mm and not more than 2.0 mm.
In an analogous art, Hazhizume teaches:
wherein the die pad has a thickness of not less than 1.0 mm and not more than 2.0 mm, (e.g. about 400 μm to about 2 mm at para. [0126]).
In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). “[A] prior art reference that discloses a range encompassing a somewhat narrower claimed range is sufficient to establish a prima facie case of obviousness." In re Peterson, 315 F.3d 1325, 1330, 65 USPQ2d 1379, 1382-83 (Fed. Cir. 2003). See MPEP § 2144.05, Obviousness of Ranges
Referring to MPEP § 2144.05, “…the applicant must show that the particular range is critical, generally by showing that the claimed range achieves unexpected results over the prior art range.” (See also MPEP § 716.02 for a discussion of criticality and unexpected results.)
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Saitoh with the teachings of Hashizume because art recognized suitable thicknesses for the die pad are well known. See MPEP § 2144.07, Art Recognized Suitability for an Intended Purpose.
Claim(s) 13 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Saitoh, as applied to claim 1 above, in view of Ikezawa et al., US Publication No. 2009/0143511 A1.
Regarding claims 13 and 14:
Saitoh teaches all the limitations of claim 1 above, and further teaches the sealing resin comprises epoxy resin col 3, ln 50–57.
Saitoh does not expressly teach:
the sealing resin includes a thermosetting base resin, a silane coupling agent, and a hardening accelerator;
the thermosetting base resin includes an epoxy resin, and the hardening accelerator includes a phosphorus-based hardening accelerator.
In an analogous art, Ikezawa teaches:
the sealing resin includes a thermosetting base resin, a silane coupling agent, and a hardening accelerator;
the thermosetting base resin includes an epoxy resin, and the hardening accelerator includes a phosphorus-based hardening accelerator, para. [0016], [0027], [0129].
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Saitoh with the teachings of Ikezawa because “…an encapsulated epoxy-resin molding compound superior in flame resistance moldability and also in reliability such as reflow resistance, moisture resistance, high-temperature storage stability, and thus, favorable for sealing VLSI, and an electronic component device carrying an element sealed with the molding compound.” See Ikezawa at Abstract.
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Saitoh, as applied to claim 1 above, in view of Hosokawa, US Publication No. 2005/0046021 A1.
Regarding claim 16:
Saitoh is silent wherein the element joining layer has a thickness of not less than 50 μm and not more than 200 μm.
In an analogous art, Hosokawa teaches “In conventional semiconductor devices, …the thickness of the adhesive layer for fixing and bonding a semiconductor element is generally from 10 to 50 μm.”, para. [0073]. The disclosed range overlaps the claimed range.
In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). “[A] prior art reference that discloses a range encompassing a somewhat narrower claimed range is sufficient to establish a prima facie case of obviousness." In re Peterson, 315 F.3d 1325, 1330, 65 USPQ2d 1379, 1382-83 (Fed. Cir. 2003). See MPEP § 2144.05, Obviousness of Ranges
Referring to MPEP § 2144.05, “…the applicant must show that the particular range is critical, generally by showing that the claimed range achieves unexpected results over the prior art range.” (See also MPEP § 716.02 for a discussion of criticality and unexpected results.)
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Saitoh with the teachings of Hosokawa because an element joining layer thickness of 50 μm is conventional in semiconductor devices. See Saitoh at para. [0073].
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Michele Fan whose telephone number is 571-270-7401. The examiner can normally be reached on M-F from 7:30 am to 4 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Jeff Natalini, can be reached on (571) 272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Michele Fan/
Primary Examiner, Art Unit 2818
23 September 2026
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