DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is a response to the amendment filed 7/08/2026. Claims 1-3, 5, 7-14, 16-23 are pending and are under examination.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 19-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al (US 2019/0253044).
Regarding claim 19, A driver comprising: a first circuit (130) configured to provide a first reference voltage (VLS_H), wherein the first reference voltage is an output of a capacitor node (C2); a second circuit (140) configured to provide a second reference voltage (VLS_L) different from the first reference voltage; and a plurality of transistors (NM3 to NM10), wherein a first or second voltage (VLS_H; VLS_L), each of which is substantially equivalent to a respective one of the first or second reference voltage, facilitates selective operation of a transistor of the plurality of transistors to output a third voltage (provided at the terminals TXP/TXN), wherein at least one of the transistors (NM8/NM10) has a first terminal connecting to an output node outputting the third voltage and a second terminal non-capacitively connecting to an electrical ground; and wherein the plurality of transistors is configured to selectively output one of the first voltage, the second voltage, a supply voltage, and an electrical ground voltage at the output node as the third voltage (the terminals TXP/TXN assume one of the first voltage (VLS_H), the second voltage (VLS_L), a supply voltage (VDDTX), and an electrical ground voltage (ground) at the output node (TXP/TXN) as the third voltage) as called for in claim 19.
Regarding claim 20, wherein the third voltage that is a non-transient voltage (figures 6 and 7).
Allowable Subject Matter
Claims 1-3, 5, 7-14, 16-18, 21-23 are presently allowed.
The following is a statement of reasons for the indication of allowable subject matter: Kim et al. (US 2019/0253044) fails to teach or fairly suggest the second buffer has a non-inverting input configured to receive a second reference voltage and an inverting input configured to receive the second voltage as called for in claims 1 and 12. Therefore, claims 1-3, 5, 7-14, 16-18, 21-23 are presently allowed.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. In this regard, applicant’s cited prior art has been considered.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUAN THIEU LAM whose telephone number is (571)272-1744. The examiner can normally be reached Monday-Friday, 8:30 am to 5:00 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Regis Betsch can be reached at 571-270-7101. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TUAN T LAM/Primary Examiner, Art Unit 2843 8/24/2026