Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
Acknowledgment is made of the information disclosure statements filed on 11 February 2025 and 11 August 2026, U.S. patents and Foreign Patents have been considered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 11, 12, and 13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US7076758B1 (Srinivasan).
In regards to claim 1, (Srinivasan) shows a method for circuit design processing, comprising:
performing, via a first processing unit, a first stage of a design process for a circuit design; Srinivasan [Column 8 Lines 25 - 30] teaches realizing the design system in a distributed fashion where different elements are spread across several interconnected computer systems, thereby providing a first processing unit and a second processing unit. Srinivasan [Column 3 Lines 12 - 14] teaches a global placer performing an initial assignment of components to physical locations on the chip as a first stage of the design process.
collecting data associated with processing at least a portion of the circuit design via the first processing unit; Srinivasan [Column 4 Lines 31 - 34] teaches loading the circuit design into the global placer, performing an initial placement, and providing the initially placed circuit design to the RAP router.
providing at least a portion of the collected data to a second processing unit to perform a second stage of the design process for at least the portion of the circuit design to yield a circuit processing result; and Srinivasan [Column 3 Lines 14 - 17] teaches the RAP router performing an initial routing of signals and determining timing information regarding routed delays for connections as a second stage that yields a circuit processing result.
providing the circuit processing result to the first processing unit to aid in performing the first stage of the design process. Srinivasan [Column 3 Lines 19 - 21] teaches the RAP router providing the determined timing information back to the RAP placer as feedback, and Srinivasan [Column 4 Lines 55 - 57] teaches the RAP placer relocating components to reduce delay and meet timing constraints, thereby aiding the first stage.
In regards to claim 11, (Srinivasan) shows the method of claim 1:
wherein the first stage of the design process comprises a first one of multiple stages of a place and route flow, and wherein the second stage of the design process comprises a second one of the multiple stages of the place and route flow. Srinivasan [Column 3 Lines 12 - 17] teaches a global placer performing placement as a first stage and a RAP router performing routing as a second stage of a place and route flow.
In regards to claim 12, (Srinivasan) shows the method of claim 11:
wherein the multiple stages comprise one or more of a placement and optimization stage, a clock-tree synthesis (CTS) stage, post-CTS optimization stage, routing stage, and post-routing optimization stage. Srinivasan [Column 3 Lines 12 - 17] teaches a global placer performing placement as a first stage and a RAP router performing routing as a second stage of a place and route flow.
In regards to claim 13, (Srinivasan) shows an apparatus for circuit design processing, comprising:
a memory; and one or more processors coupled to the memory and configured to: Srinivasan [Column 8 Lines 30 - 36] teaches a general purpose computer system with a computer program that, when loaded and executed, controls the computer system to carry out the described methods, and Srinivasan [Column 4 Lines 20 - 23] teaches the global placer, RAP router, RAP placer, and detailed router implemented as application programs executing within a suitable computer.
perform, via a first processing unit, a first stage of a design process for a circuit design; Srinivasan [Column 8 Lines 25 - 30] teaches realizing the design system in a distributed fashion where different elements are spread across several interconnected computer systems, thereby providing a first processing unit and a second processing unit. Srinivasan [Column 3 Lines 12 - 14] teaches a global placer performing an initial assignment of components to physical locations on the chip as a first stage of the design process.
collect data associated with processing at least a portion of the circuit design via the first processing unit; Srinivasan [Column 4 Lines 31 - 34] teaches loading the circuit design into the global placer, performing an initial placement, and providing the initially placed circuit design to the RAP router.
provide at least a portion of the collected data to a second processing unit to perform a second stage of the design process for at least the portion of the circuit design to yield a circuit processing result; and Srinivasan [Column 3 Lines 14 - 17] teaches the RAP router performing an initial routing of signals and determining timing information regarding routed delays for connections as a second stage that yields a circuit processing result.
provide the circuit processing result to the first processing unit to aid in performing the first stage of the design process. Srinivasan [Column 3 Lines 19 - 21] teaches the RAP router providing the determined timing information back to the RAP placer as feedback, and Srinivasan [Column 4 Lines 55 - 57] teaches the RAP placer relocating components to reduce delay and meet timing constraints, thereby aiding the first stage.
Claims 18 and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US20210287120A1 (Mamidi).
In regards to claim 18, (Mamidi) shows a method for circuit design processing, comprising:
performing a first portion of a design process for a circuit design; Mamidi [0036] teaches an EDA tool configured to run flows on a set of designs for an early stage such as place_opt, i.e., performing a first portion of a design process.
collecting data associated with processing at least a portion of the circuit design; and Mamidi [0029] teaches extracting features from partial circuits at various early design stages and providing them to the ML models, i.e., collecting data associated with processing the circuit design.
training at least one machine learning (ML) model configured to recommend one or more actions to be performed for the design process, wherein the at least one ML model is trained based on the collected data, and wherein a second portion of the design process for the circuit design is performed using the at least one trained ML model. Mamidi [0030] teaches training the ML models using the results of later design stages as ground truth, and Mamidi [0025] teaches providing the predicted metrics as feedback to improve RTL synthesis, constraints, and floorplan, thereby training an ML model that recommends actions for the design process. Mamidi [0038] teaches that in subsequent runs the EDA tool runs only through an early design stage and extracts prediction features, i.e., performing a second portion using the trained ML model.
In regards to claim 19, (Mamidi) shows the method of claim 18:
wherein the first portion of the design process comprises a first run of the design process, and wherein the second portion of the design process comprises a second subsequent run of the design process. Mamidi [0033] teaches selecting past runs based on previous implementation runs of the same design, and Mamidi [0038] teaches that subsequent runs use the trained models, thereby providing a first run and a second subsequent run.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over US7076758B1 (Srinivasan) in view of US5875117A (Jones).
In regards to claim 2, (Srinivasan) does not show: wherein the second stage of the design process is performed via the second processing unit while at least a portion of the first stage of the design process is being performed.
Jones teaches wherein the second stage of the design process is performed via the second processing unit while at least a portion of the first stage of the design process is being performed; Jones [Column 15 Line 60 through Column 16 Line 5] teaches routing groups simultaneously using parallel processors while a congestion reduction algorithm alters the placement in high-congestion areas simultaneously, such that the routing second stage is performed while the placement first stage is being performed.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Srinivasan and Jones to perform the second stage of the design process concurrently with the first stage, with a reasonable expectation of success as both references address the place and route processing of circuit designs.
In regards to claim 14, (Srinivasan) does not show: wherein the second stage of the design process is performed via the second processing unit while at least a portion of the first stage of the design process is being performed.
Jones teaches wherein the second stage of the design process is performed via the second processing unit while at least a portion of the first stage of the design process is being performed; Jones [Column 15 Line 60 through Column 16 Line 5] teaches routing groups simultaneously using parallel processors while a congestion reduction algorithm alters the placement in high-congestion areas simultaneously, such that the routing second stage is performed while the placement first stage is being performed.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Srinivasan and Jones to perform the second stage of the design process concurrently with the first stage, with a reasonable expectation of success as both references address the place and route processing of circuit designs.
Claims 3-6, 10, 15, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over US7076758B1 (Srinivasan) in view of US20090292383A1 (Bohl).
In regards to claim 3, (Srinivasan) does not show: analyzing at least a portion of the collected data; and providing a recommendation for an action to be performed when performing one of multiple steps of a place and route flow for the circuit design.
Bohl teaches analyzing at least a portion of the collected data; and providing a recommendation for an action to be performed when performing one of multiple steps of a place and route flow for the circuit design; Bohl [0083] teaches analyzing the generated data, detecting and diagnosing a symptom, and proposing one or more remedies, thereby providing a recommendation for an action to be performed in the design flow.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Srinivasan and Bohl to analyze the collected data and recommend a design action, with a reasonable expectation of success as both references address automated circuit design flows.
In regards to claim 4, (Srinivasan modified by Bohl) shows the method of claim 3:
Bohl teaches wherein the first stage of the design process is performed during a first step of the multiple steps of the place and route flow, the action being recommended to be performed during the first step; Bohl [0092] teaches proposing one or more remedies corresponding to the identified root causes for application at the current step of the design flow.
In regards to claim 5, (Srinivasan modified by Bohl) shows the method of claim 3:
Bohl teaches wherein the multiple steps are performed during each run of the place and route flow, wherein the data being collected for a first run of the place and route flow, and wherein the action is recommended to be performed during a step of a second run of the place and route flow, the second run being different than the first run; Bohl [0057] teaches gathering data by running designs and using stored success/fail information from past runs to formulate and prioritize trials in subsequent runs.
In regards to claim 6, (Srinivasan modified by Bohl) shows the method of claim 3:
Bohl teaches wherein the at least the portion of the collected data is analyzed via at least one of one or more machine learning (ML) models, action state table, or rule-based decisions; Bohl [0054] teaches a reasoner implemented as a software program that associates an observed symptom with a remedy, i.e., a rule-based decision.
In regards to claim 10, (Srinivasan modified by Bohl) shows the method of claim 3:
Bohl teaches wherein the recommendation of the action comprises at least one of: a placement recommendation based on analyzing circuit congestion; a recommendation associated with timing of signals for the circuit design; a recommendation based on design rule check (DRC) hotspots for the circuit design; or a recommendation based on identification of power-hungry logic cones of the circuit design; Bohl [0092] teaches proposed remedies including optimizing pin placement and spreading macros, i.e., a placement recommendation based on analyzing circuit congestion.
In regards to claim 15, (Srinivasan) does not show: analyze at least a portion of the collected data; and provide a recommendation for an action to be performed when performing one of multiple steps of a place and route flow for the circuit design.
Bohl teaches analyze at least a portion of the collected data; and provide a recommendation for an action to be performed when performing one of multiple steps of a place and route flow for the circuit design; Bohl [0083] teaches analyzing the generated data, detecting and diagnosing a symptom, and proposing one or more remedies, thereby providing a recommendation for an action to be performed in the design flow.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Srinivasan and Bohl to analyze the collected data and recommend a design action, with a reasonable expectation of success as both references address automated circuit design flows.
In regards to claim 16, (Srinivasan modified by Bohl) shows the apparatus of claim 15:
Bohl teaches wherein the multiple steps are performed during each run of the place and route flow, wherein the data being collected for a first run of the place and route flow, and wherein the action is recommended to be performed during a step of a second run of the place and route flow, the second run being different than the first run; Bohl [0057] teaches gathering data by running designs and using stored success/fail information from past runs to formulate and prioritize trials in subsequent runs.
Claims 7, 8, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over US7076758B1 (Srinivasan) in view of US20090292383A1 (Bohl) and US20230034736A1 (Singh).
In regards to claim 7, (Srinivasan modified by Bohl) does not show: providing an indication of whether the action is recommended to be applied during a current run of the place and route flow, whether the action is recommended to be applied during a subsequent run of the place and route flow, or whether the action is recommended for further analysis during an exploration run of the place and route flow.
Singh teaches providing an indication of whether the action is recommended to be applied during a current run of the place and route flow, whether the action is recommended to be applied during a subsequent run of the place and route flow, or whether the action is recommended for further analysis during an exploration run of the place and route flow; Singh [0028] teaches three stages including stabilization, exploration, and closure, and Singh [0105] teaches the exploration stage identifying strategies most likely to improve performance, thereby indicating an action recommended for an exploration run.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further combine Srinivasan and Bohl with Singh to indicate whether a recommended action applies to a current run, a subsequent run, or an exploration run, with a reasonable expectation of success as the references address circuit design optimization.
In regards to claim 8, (Srinivasan modified by Bohl) does not show: determining a confidence score associated with the recommendation, wherein the action is recommended based on a comparison of the confidence score with a threshold.
Singh teaches determining a confidence score associated with the recommendation, wherein the action is recommended based on a comparison of the confidence score with a threshold; Singh [0117] teaches each classification model quantifying the probability, i.e., a confidence score, that a strategy would improve the design by at least a certain percentage, and Singh [0116] teaches using a margin of at least 1% as a threshold, such that the action is recommended based on a comparison of the confidence score with the threshold.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further combine Srinivasan and Bohl with Singh to determine a confidence score for the recommendation and recommend the action based on a comparison of the confidence score with a threshold, with a reasonable expectation of success as the references address circuit design optimization.
In regards to claim 17, (Srinivasan modified by Bohl) does not show: provide an indication of whether the action is recommended to be applied during a current run of the place and route flow, whether the action is recommended to be applied during a subsequent run of the place and route flow, or whether the action is recommended for further analysis during an exploration run of the place and route flow.
Singh teaches provide an indication of whether the action is recommended to be applied during a current run of the place and route flow, whether the action is recommended to be applied during a subsequent run of the place and route flow, or whether the action is recommended for further analysis during an exploration run of the place and route flow; Singh [0028] teaches three stages including stabilization, exploration, and closure, and Singh [0105] teaches the exploration stage identifying strategies most likely to improve performance, thereby indicating an action recommended for an exploration run.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further combine Srinivasan and Bohl with Singh to indicate whether a recommended action applies to a current run, a subsequent run, or an exploration run, with a reasonable expectation of success as the references address circuit design optimization.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over US7076758B1 (Srinivasan) in view of US20090292383A1 (Bohl) and US7007247B1 (Wang).
In regards to claim 9, (Srinivasan modified by Bohl) does not show: wherein analyzing the at least the portion of the collected data comprising analyzing at least one of: power consumption associated with wiring for the circuit design; power consumption associated with data path logic of the circuit design; or power consumption associated with clock path logic of the circuit design.
Wang teaches power consumption associated with data path logic of the circuit design; Wang [Column 3 Lines 35 - 50] teaches identifying combinational functional blocks such as a multiplier and arithmetic units, i.e., data path logic, as candidates, and Wang [Column 4 Lines 40 - 50] teaches evaluating the committed modules to determine whether they save power to the circuit, thereby analyzing power consumption associated with data path logic.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further combine Srinivasan and Bohl with Wang to analyze power consumption associated with data path logic of the circuit design, with a reasonable expectation of success as the references address power-aware circuit design.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over US20210287120A1 (Mamidi) in view of US7076758B1 (Srinivasan).
In regards to claim 20, (Mamidi) shows the method of claim 18:
the at least one ML model is trained using the circuit processing result generated via the second processing unit; Mamidi [0030] teaches training the ML models using the results of later design stages as ground truth, i.e., training the ML model using the circuit processing result.
Mamidi differs from the claimed invention in that it does not explicitly disclose the first portion of the design process is performed via a first processing unit and includes a first stage of the design process; and the method further comprises providing at least a portion of the collected data to a second processing unit to perform a second stage of the design process for at least the portion of the circuit design to generate a circuit processing result.
Srinivasan teaches the first portion of the design process is performed via a first processing unit and includes a first stage of the design process; Srinivasan [Column 8 Lines 25 - 30] teaches realizing the design system in a distributed fashion where different elements are spread across several interconnected computer systems, thereby providing a first processing unit and a second processing unit. Srinivasan [Column 3 Lines 12 - 14] teaches a global placer performing an initial assignment of components to physical locations on the chip as a first stage of the design process.
Srinivasan teaches the method further comprises providing at least a portion of the collected data to a second processing unit to perform a second stage of the design process for at least the portion of the circuit design to generate a circuit processing result; Srinivasan [Column 4 Lines 31 - 34] teaches loading the circuit design into the global placer, performing an initial placement, and providing the initially placed circuit design to the RAP router. Srinivasan [Column 3 Lines 14 - 17] teaches the RAP router performing an initial routing of signals and determining timing information regarding routed delays for connections as a second stage that yields a circuit processing result.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Mamidi and Srinivasan to perform the first and second stages of the design process via first and second processing units, with a reasonable expectation of success as both references address the processing of circuit designs.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANWER AHMED ALAWDI whose telephone number is (703)756-1018. The examiner can normally be reached Monday - Friday 8:00 am - 5:30 pm.
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/ANWER AHMED ALAWDI/Examiner, Art Unit 2851 /JACK CHIANG/ Supervisory Patent Examiner, Art Unit 2851
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