DETAILED ACTION
This office action is in response to the election and amendment as filed on February 5, 2026. In accordance with this amendment, claims 1-7, 15, 18, and 20 have been amended.
Claims 1-20 remain pending (claims 1-7 are joined with claims 8-14 (based on the amendments of at least independent claim 1)), with claims 15-20 remaining withdrawn from consideration as being related to a method of manufacturing the device of Group I (now claims 1-14).
However, the Examiner notes that claims 15-20 will be considered for claim rejoinder upon allowance of features of claims 1-14. For consideration of such rejoinder, at least independent claim 15 must be amended concurrently to claims 1 / 8 during prosecution. Claims 15-20 will remain in “Withdrawn” status until allowance. Note Sections (7) – (8) in the restriction mailed on January 20, 2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Group I, claims 8-14, in the reply filed on February 5, 2026 is acknowledged. The traversal is on the grounds that because independent claims 1 and 15 have been amended concurrently to elected independent claim 8, that such claims should be joined with Group I (because this group included claim 8; and dependent claim 9-14. This is persuasive for claims 1-8 (Group III) because claim 1 is a device / apparatus claim, but is not found persuasive because Group II, claims 15-20, because at least claim 15 is a method of manufacturing.
The requirement is still deemed proper and is therefore made FINAL.
However, the Examiner respectfully notes that claims 15-20 should remain pending and in “Withdrawn” status (not “Canceled”). If claim 15 is amended concurrently to claims 1 and 8 during prosecution, the Examiner will consider fully rejoining the method claims 15-20 at allowance. Note that each device / structural / apparatus feature from (potentially) amended claims 1 and 8 must be also amended into claim 15 to maintain eligibility for rejoinder. See Sections (7) – (8) in the original restriction dated January 20, 2026.
Information Disclosure Statement
It is again noted that Applicant has not filed an Information Disclosure Statement. If Applicant becomes aware of any prior art that may be pertinent to the examination and analysis of the claimed subject matter, a PTO-1449 form should be filed.
Drawings
The original drawings (sixteen (16) pages) were received on January 17, 2024. These drawings are acknowledged.
Claim Objections
Claims 2 and 9 are objected to because of the following informalities: at the end of the preamble in each dependent claim, the language should read “which further comprises:“, or “further comprising:”, with the necessary language and a colon (“ : “). Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1 and 8 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1 and 8 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential structural cooperative relationships of elements, such omission amounting to a gap between the necessary structural connections. See MPEP § 2172.01. The omitted structural cooperative relationships are: all essential features found in the Figs. 4 and 5B, and the original specification must be included in the broadest independent claim 1 / 8 for proper clarity and the ability to function as intended as the “semiconductor structure / device” in the preambles. For example, (1), the “etching stop pattern” / “first/second etching stop layer(s)” 210a / 210b (Fig. 5B) should be found in claim 8. Such features are not optional for the overall functionality to be proper in the device, conversely they are essential. Next, (2), the “barrier layer” 250a / 250b (Fig. 5B) should be found in both claims 1 and 8. Such feature is not optional for the overall functionality to be proper in the device, conversely it is essential. Finally, (3), an “optical waveguide element” at a “protrusion” feature 205 (Fig. 5B) should be found in both claims 1 and 8. Such feature(s) is/are not optional for the overall functionality to be proper in the device, conversely they are essential. The features (1), (2), and (3) as listed above must be amended into independent claims 1 and 8 to provide a clear and definite claim, as a whole, to include all essential structural connections. Without such features, claims 1 and 8 are rejected under 35 U.S.C. 112(b) as being incomplete for omitting essential structural cooperative relationships of elements, such omission amounting to a gap between the necessary structural connections. Claims 2-7 and 9-14 are also rejected at least as being dependent from claims 1 and 8, respectfully. The Examiner also notes that independent method claim 15 should also be amended concurrently with those features (1), (2), and (3) for consideration and rejoinder.
Claim Interpretation
The Examiner respectfully notes that no “frame-of-reference” is given for either the “width” of the “first/second silicide layer” or the “first/second via”. Therefore, any of the three dimensions can be interpreted for “width” of either element. Applicant should add language that clearly outlined what is the “width” dimension in the claims 1 / 8.
Further, the multiple layered features that each comprise “semiconductor”” materials can reasonably meet a “substrate” and “semiconductor” in the prior art.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 6-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Frohberg et al. US 2011/0266638 A1.
Frohberg et al. US 2011/0266638 A1 teaches (ABS; Figs. 1a-1d; paragraphs [0020] – [0033]; Claims) a semiconductor device (resultant shown in Fig. 1d), comprising: a semiconductor substrate (120; having multiple layer(s)) having a first groove and a second groove (to the left and right of “130” in Fig. 1d are the 1st / 2nd grooves in a substrate); a dielectric layer 122, filled into the first groove and the second groove, wherein the dielectric layer has a first via in the first groove and a second via in the second groove (under “125” in each groove, the “via” or “hole” includes filled in features of 124 and 126, see Fig. 1d); a silicide pattern 124S, located in the semiconductor substrate, wherein the silicide pattern comprises a first silicide layer under the first via and a second silicide layer under the second via (multiple 124S’s shown in both grooves), wherein a width of the first silicide layer is smaller than or equal to a width of the first via (the same, see Fig. 1d), and a width of the second silicide layer is smaller than or equal to a width of the second via (the same, see Fig. 1d); and a first contact metal and a second contact metal, respectively disposed in the first via and the second via (124 and 126 are both metals, with provide “contact”, to fill the entire via(s)), which clearly, fully meets Applicant’s claimed structural limitations of independent claim 8. Regarding independent claim 1, the layer 121 in Frohberg ‘638 Fig. 1d meets the broad function of “etch stop” because this layer is capable of stopping an etch.
Regarding dependent claim 6, the substrate has a negative space or “notch” under the through hole of the etching stop layer 121 and the silicon layer 124S is found to fill this notch (as negative space is filled), which meets all structure.
Regarding claim 7, because the bottom surface of layer 121 does not touch the top surface of 124S (see Fig. 1d), there two distinct “surfaces” are “separated” in a broadest reasonable interpretation (BRI) of terms. The side surface of 121 touches a side surface of 124S, thus the structure of claim 7 is met.
Regarding dependent claim 9, because the layer 121 does not go through the entire via / groove area, it is separated from the second etch stop layer (other 121).
Regarding claim 10, element 124S is aligned with the ending sidewall of 121, which meets all structure.
Regarding claim 11, because all such features are negative space (met by the end of the element 121 as an “etch stop”), the through hole features are met by Frohberg ‘638 Fig. 1d.
Regarding claim 12, the width of 124S is equal to the negative space of the through hole of 121’s gap (Fig. 1d).
Regarding claim 13, there is a protrusion (133 / 131) to cause an increase or protruding feature between the grooves (Fig. 1d).
Regarding claim 14, portions of 122 cover the protrusion feature 133.
Claims 1 and 8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Frohberg et al. U.S. Patent No. 9,590,056 B2.
The following rejection uses the broadest reasonable interpretation (BRI) of “width” of each feature the “first/second silicide layer(s)” and the “first/second via(s)” Note that there are three dimensions to each feature 255 and the negative space / via in Frohberg US ‘056 figures 2a-2i (resultant in Fig. 2i).
Frohberg et al. U.S. Patent No. 9,590,056 B2 teaches (ABS; Figs. 2a-2i; column 8, line 39 through column 12, line 58; Claims) a semiconductor device (resultant shown in Fig. 2i), comprising: a semiconductor substrate (203 / 202 / 215; having multiple layer(s)) having a first groove and a second groove (to the left and right of “250” as the central element in Fig. 2i are the 1st / 2nd grooves in a substrate); a dielectric layer 215, filled into the first groove and the second groove, wherein the dielectric layer has a first via in the first groove and a second via in the second groove (near “211” in Fig. 2i, in each groove, the “negative space” or “via” or “hole” includes filled in features of 211 and 213; see Figs. 2f and 2h); a silicide pattern 255, located in the semiconductor substrate, wherein the silicide pattern comprises a first silicide layer under the first via and a second silicide layer under the second via (multiple 255’s shown in both grooves), wherein a width of the first silicide layer is smaller than or equal to a width of the first via (the “width” direction viewed as bottom-to-top, in Fig. 2i, feature 255 has a much smaller dimension that the via in this direction), and a width of the second silicide layer is smaller than or equal to a width of the second via (same BRI of “width” above); and a first contact metal and a second contact metal, respectively disposed in the first via and the second via (211 and 213 are both metals, with provide “contact”, to fill the entire via(s)), which clearly, fully meets Applicant’s claimed structural limitations of independent claim 8. Regarding independent claim 1, the layers 215a and 215c in Frohberg ‘056 Figs. 2a-2i meets the broad function of “etch stop” because this layer is capable of stopping an etch.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-14 are rejected under 35 U.S.C. 103 as being unpatentable over Frohberg et al. U.S. Patent No. 9,590,056 B2, and further in view of Lin et al. U.S. Patent No. 9,735,050 B2.
For this rejection, the “width” feature is viewed as left-to-right in Frohberg.
Regarding independent claims 1 and 8, Frohberg et al. U.S. Patent No. 9,590,056 B2 teaches (ABS; Figs. 2a-2i; column 8, line 39 through column 12, line 58; Claims) a semiconductor device (resultant shown in Fig. 2i), comprising: a semiconductor substrate (203 / 202 / 215; having multiple layer(s)) having a first groove and a second groove (to the left and right of “250” as the central element in Fig. 2i are the 1st / 2nd grooves in a substrate); a dielectric layer 215, filled into the first groove and the second groove, wherein the dielectric layer has a first via in the first groove and a second via in the second groove (near “211” in Fig. 2i, in each groove, the “negative space” or “via” or “hole” includes filled in features of 211 and 213; see Figs. 2f and 2h); a silicide pattern 255, located in the semiconductor substrate, wherein the silicide pattern comprises a first silicide layer under the first via and a second silicide layer under the second via (multiple 255’s shown in both grooves), wherein a width of the first silicide layer is under the via (filled with barrier 213 and metal contact element 211; Fig. 2i, feature 255 is directly under the filled via as part of a substrate), and a width of the second silicide layer under a second via (same 255 Fig. 2i); and a first contact metal and a second contact metal, respectively disposed in the first via and the second via (211 and 213 are both metals, with provide “contact”, to fill the entire via(s)). Regarding independent claim 1, the layers 215a and 215c in Frohberg ‘056 Figs. 2a-2i meets the broad function of “etch stop” because this layer is capable of stopping an etch.
Regarding independent claims 1 and 8, Frohberg ‘056 does not expressly and exactly teach that the first/second silicide pattern (255) has a width that is smaller than or equal to the width of the first/second via. Note the frame-of-reference for “width” in this interpretation is left-to-right in Fig. 4 and 5B of the current application.
Lin et al. U.S. Patent No. 9,735,050 B2 teaches (ABS; Figs. 1, 9; corresponding text; Claims) a via (Figs. 1 and 9) that is filled with a conductive metal contact feature, and a barrier layer, and a silicide pattern 104 at the bottom of the via (see Figs. 1 and 9), and in which the silicon pattern element has a width that is approximately smaller than or equal to a width of the (filled) via element, the silicide pattern 104 being in a semiconductor 102. Such features of the via, and also noting the tapering / decreasing width of the filled contact metal and barrier layer, are used for the purpose and motivation of improving electrical connectivity, but also increase ease of manufacturing because the tapering shape can be used. Such outline and shape of Figs. 1 and 9 of Lin are known to decrease the amount of contact metal for the filled via (in comparison to a rectangular shape) and also decrease the necessary amount of the silicide in the pattern. Such elements can be more expensive for fabrication (in comparison to dielectrics / semiconductors) and will decrease overall costs of manufacture.
Since Frohberg ‘056 and Lin ‘050 are both from the same field of endeavor, the purpose disclosed by Lin ‘050 would have been recognized in the pertinent art of Frohberg ‘056.
A person having ordinary skill in the art at a time before the effective filing date of the current application would have recognized the teaching of Lin ‘050, to use a via that has a decreasing / tapering shape to be filled (with contact metal and barrier layer), as well as a smaller/equal width of the silicide pattern used at the bottom of the via (the location of the silicide in a semiconductor), into the base design of the semiconductor structure / device of Frohberg ‘056, to allow for an improved via / fill shape (for the contact metal and barrier layer), and a decrease in size of the silicide material and other filling materials for the negative space of the via, for substantially decreasing the costs of manufacturing of the resultant device. Further, it would have required no undue burden or unnecessary experimentation to arrive at such feature of the tapering / decreasing shape of the (filled) via and having a smaller / equal width of the silicide layer. See KSR v. Teleflex, 127 S.Ct. 1727 (2007). For these reasons, independent claims 1 and 8 are found obvious over Frohberg ‘056 and further in view of Lin ‘050 (henceforth “COMBO”).
Regarding further dependent claims 2-7 and 9-14, all such features are either found directly within Frohberg ‘056 itself, or would have been obvious design choices that required merely common skill in the art of semiconductor fabrication. At a time before the effective filing date of the current application, it would have been an obvious matter of common skill and design choice to a person of ordinary skill in the art to use features such as outlined by dependent claims 6, 7, and 9-14, or the further selectable ranges / materials (as in claims 2-5), because Applicant has not disclosed that using such features provides an advantage, is used for a particular purpose, or solves a stated problem. One of ordinary skill in the art, furthermore, would have expected COMBO to perform equally well with such features as the optical dependencies (semiconductor selectable design choices after the base structure of claims 1 and/or 8) because these claim terms would have been easily integrated and would have also been recognized by one with common skill in the art to improve fabrication, cost, and specification tolerance for a fab. It would have required no undue burden or unnecessary experimentation to arrive at those features with a semiconductor structure / apparatus such as in COMBO. Further, the base structure of the independent claims 1 and 8 is found obvious over COMBO as discussed prior in this section. Therefore, it would have been an obvious matter of common skill and design choice to modify (and/or update) COMBO to obtain the invention as specified in claims 2-7 and 9-14. See KSR v. Teleflex, 127 S.Ct. 1727 (2007).
Inventorship
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: PTO-892 form references D-F and N (U is the English translation of reference N), which pertain to the state of the art of filled vias with silicide patterns and/or etching stop layers at the bottom of the via.
No IDS (PTO-1449) has yet been filed by Applicant during prosecution.
Applicant should add all essential structure into claims 1 and 8. The Examiner will rejoin all method of manufacturing claims if they are amended concurrently.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Daniel Petkovsek whose telephone number is (571) 272-4174. The examiner can normally be reached M-F 7:30 - 6 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Uyen-Chau Le can be reached at (571) 272-2397. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DANIEL PETKOVSEK/Primary Examiner, Art Unit 2874 May 19, 2026
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