Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 07/24/2026 has been entered.
Response to Arguments
Applicant's arguments filed 07/24/2026 have been fully considered and have been addressed as follows. Applicant’s arguments include portions “a” and “b,” each being recited below and responded briefly.
a. Applicant argued on page 9-10 of the remarks:
"However, Kwok does not disclose splitting a single codeword into separate first and second codewords for independent but coordinated decoding. Kwok appears to describe a memory system using partial codewords (e.g., "partial codeword" or "stripe codeword" portions as in Kwok' s FIG. 1 and [0051 ]), but not the particular technique of forming two codewords from one original codeword such that they can be decoded in concert to handle a single device failure." "Regarding the specific functions of each codeword type, the Examiner's cited portions of Kwok (e.g., [0039]-[0041]) do not describe any codeword having two distinct parts with separate ECC roles as claimed. Kwok is silent regarding a dual-codeword scheme where one codeword is "stronger" (random-error correcting) and the other "weaker" (erasure-correcting). Kwok simply discloses a memory system where a codeword's parts ( or a partial codeword) can be used in decoding. There is no teaching in Kwok of one codeword performing random error correction while another different codeword performs only erasure corrections."
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Georg suffers similar deficiencies. Though Georg appears to describe mathematically combining multiple codewords' syndrome information to improve error location in certain interleaved coding contexts, Georg's interleaved RS codes involve codewords that, while processed together, are not taught to be derived from a single common original codeword in the manner claimed.
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b. On Remarks page 12-13 Applicant argued that
Ilani is completely silent regarding taking one codeword and splitting it into two codewords (first and second) for parallel decoding in the manner claimed. At best, Ilani's mention of “first and second codeword" refers to using multiple codewords and parity to form new codewords, not the breaking of a single original data block into two sub-codewords with different error-correcting strengths.
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In addition, Ilani contains no teaching of two codewords with separate error vs. erasure correction roles. Ilani's disclosed technique (insofar as discernible) involves designating certain bits as erased through additional read/write operations (like writing an inverse bit string). This is a very different concept from having two codewords of different parity strengths collaborating. Ilani' s method does not partition the ECC functionality into separate codewords the way the claims require.
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However, Ilani does not provide the claimed "erasures marked based solely on error locations from another codeword". Rather, Ilani's method involves multiple operations (including writing an inverse bit pattern and reading it back) to determine erased bits, which is fundamentally different. Ilani does not suggest a scenario where the only information needed to mark erasures in a second codeword is the error location output of a first codeword's decoding. In contrast, the present claims require exactly that streamlined approach - the second codeword's erasures are determined solely by what the first codeword's decoding reveals.
Therefore, the cited references, even if theoretically combined, would still rely on additional mechanisms or multiple steps beyond just a first codeword's error locations, and thus fail to teach the straightforward, one-step marking of erasures in the second codeword as recited.
In response to Applicant’s Arguments a) and b) , Examiner would like to point out that
ILANI teaches Fig. 1, 150 & 152 ; [0023] a first correction scheme 150 (e.g., a LDPC correction scheme) and a second correction scheme 152 (e.g., a stripe correction scheme); [0039] the first correction scheme 150 may include a LDPC correction scheme, and the second correction scheme 152 may include a Reed Solomon erasure correction scheme. As indicated in final office action, [0051] teaches "a single codeword (e.g., the first codeword 160 of FIG. 1)", "the first portion 175 or the second portion 177 of the stripe parity for the first stripe codeword 191 of FIG. 1 may be used to determine the first portion 171 of the first codeword 160", examiner notes that there is first & second portion for the first stripe codeword.
In addition, examiner found a new reference Weinberg et al., US 20190132007, teaches [0073] FIG. 3B, “the special codeword 320 is divided into two sub-codewords”.
2) The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. “where the only information needed to mark erasures in a second codeword is the error location output of a first codeword's decoding. In contrast, the present claims require exactly that streamlined approach - the second codeword's erasures are determined solely by what the first codeword's decoding reveals.” is NOT reflected in present claim language, written description may not be read into claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kwok, US 20160283325, hereinafter Kwok, in view of Georg Schmidt, "Collaborative Decoding of Interleave Reed-Solomon Codes and Concatenated Code Designs," IEEE Transactions on Information Theory, Vol. 55, No. 7, July 2009, hereinafter Georg, in further view of ILANI et al., US 20180091172, hereinafter ILANI.
As per claim 1, Kwok teaches A memory system comprising:
a plurality of memory components; (FIG.1, memory device 1 110, memory device 2 112; [0018]) and
a controller in communication with the plurality of memory components and configured to: (FIG.1, controller 142; [0018])
……
respectively calculate first and second syndromes for the first and second received codewords in parallel;
(FIG.3, syndrome calculator 220)
Except
perform error correction code (ECC) decoding for detecting random errors on a plurality of first codewords and a plurality of second codewords read from the plurality of memory components, wherein each first codeword and a corresponding second codeword are sub-codewords derived from a single codeword;
wherein (i) the first codeword is configured to perform a plurality of random error corrections, (ii) the second codeword is configured to perform a plurality of erasure corrections, and (iii) erasures corresponding to a single device are marked in the second codeword based solely on error locations detected in the first codeword;
combine results of the first and second syndromes in a multiple shift register computation to generate a single error location polynomial;
produce a set of polynomial roots from the single error location polynomial;
determine whether each of the first and second codewords have non-zero syndrome values when the produced set of polynomial roots is invalid;
perform an erasure search (i) on symbols in only one the first and second codewords (ii) when only the first codeword or the second codeword has a non-zero syndrome value; and
correct each of the first and second codewords responsive to the performed erasure search.
Georg teaches
combine results of the first and second syndromes in a multiple shift register computation to generate a single error location polynomial;
(Pg. 2994, Chap. D. 1st para. combine the syndrome coefficients of the received words…...This is equivalent to synthesizing the shortest linear feedback shift-register capable of generating the syndrome sequences)
produce a set of polynomial roots from the single error location polynomial; (Pg. 2994, Chap. D. last para., However, by the definition of the error locator polynomial, A(x) is only a valid error locator polynomial, if it has exactly distinct roots)
determine whether each of the first and second codewords have non-zero syndrome values when the produced set of polynomial roots is invalid; (Pg. 2996, 1st para.)
perform an erasure search (i) on symbols in only one the first and second codewords (ii) when only the first codeword or the second codeword has a non-zero syndrome value; and
correct each of the first and second codewords responsive to the performed erasure search.
(Pg.2995-2996, Chap. E. Joint Error and Erasure Correction)
It would have been obvious to one of ordinary skill in the art before the effective filling data of the claimed invention to have modified Kwok to incorporate the teaching of the elements from Georg as indicated above, in order to efficiently decoding both homogeneous and heterogeneous IRS codes (Georg, Pg 3008).
Kwok-Georg-ILANI teaches all elements above except
perform error correction code (ECC) decoding for detecting random errors on a plurality of first and second codewords read from the plurality of memory components, wherein each first codeword and a corresponding second codeword are sub-codewords derived from a single codeword;
wherein (i) the first codeword is configured to perform a plurality of random error corrections, (ii) the second codeword is configured to perform a plurality of erasure corrections, and (iii) erasures corresponding to a single device are marked in the second codeword based solely on error locations detected in the first codeword;
ILANI teaches
perform error correction code (ECC) decoding for detecting random errors on a plurality of first and second codewords read from the plurality of memory components, wherein each first codeword and a corresponding second codeword are sub-codewords derived from a single codeword;
([0051] if a single codeword (e.g., the first codeword 160 of FIG. 1) is undecoded, the first portion 175 or the second portion 177 of the stripe parity for the first stripe codeword 191 of FIG. 1 may be used to determine the first portion 171 of the first codeword 160.)
wherein (i) the first codeword is configured to perform a plurality of random error corrections, (ii) the second codeword is configured to perform a plurality of erasure corrections, and (iii) erasures corresponding to a single device are marked in the second codeword based solely on error locations detected in the first codeword; ([0039]-[0041], [0051]-[0052])
It would have been obvious to one of ordinary skill in the art before the effective filling data of the claimed invention to have modified Kwok-Georg to incorporate the teaching of the elements from ILANI as indicated above, in order to efficiently decoding both homogeneous and heterogeneous IRS codes (Georg, Pg 3008).
As per claim 2, Kwok-Georg-ILANI teaches The memory system applied above in claim 1, Kwok further teaches wherein the erasure search is performed in accordance with Chien search principles. ([0078] . The error locator polynomial 512 is provided to a logic for a Chien search 514 to generate the roots)
As per claim 3, Kwok-Georg-ILANI teaches The memory system applied above in claim 2, Kwok further teaches wherein the search is performed on each of the symbols in the only one codeword in an iterative manner. ([0078])
As per claim 4, Kwok-Georg-ILANI teaches The memory system applied above in claim 3, Georg further teaches wherein the correcting further comprises validating roots of the identified error locations of the only one codeword. (Pg.2994, Chap.D, last para.)
As per claim 5, Kwok-Georg-ILANI teaches The memory system applied above in claim 4, Georg further teaches wherein the roots are valid if only one search attempt was performed. (Pg.2994, algorithm 1)
As per claim 6, Kwok-Georg-ILANI teaches The memory system applied above in claim 5, Georg further teaches wherein error locations of the valid roots are identified. (Pg.2994, algorithm 1)
As per claim 7, Kwok-Georg-ILANI teaches The memory system applied above in claim 6, Kwok further teaches further comprising calculating error magnitudes for each of the first and second codewords responsive to the error locations of the valid roots. (Pg.2994, algorithm 1)
Claims 8-14 are corresponding method claims of claims 1-7, they are rejected under the same reason respectively as claims 1-7.
Claims 15-20 are corresponding method claim stored as computer executable instructions in a non-transitory computer readable medium of claims 1-6, they are rejected under the same reason respectively as claims 1-6.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Berman et al., US 11855658, Efficient Hard Decision Decoding Of Generalized Reed-Solomon Codes In Presence Of Erasures And Errors Within The Singleton Bound
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/RONG TANG/ Examiner, Art Unit 2111
/MARK D FEATHERSTONE/ Supervisory Patent Examiner, Art Unit 2111
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