Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/Restrictions
Applicant's election with traverse of Species 3 (claims 1-9, 11, 16 and 20) in the reply filed on 07/02/2026 is acknowledged.
The traversal is on the ground(s) that:
The restricted inventions were not shown that they are independent or distinct.
Examination can be made without a burden, as the identified species include similar limitations.
These reasons are not found persuasive because:
Should applicant traverse on the ground that the inventions or species are not patentably distinct, applicant should submit evidence or identify such evidence now of record showing the inventions or species to be obvious variants or clearly admit on the record that this is the case. In either instance, if the examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a rejection under 35 U.S.C.103(a) of the other invention.
Restriction by species require the distinction if they are patentably independent or distinct (see MPEP § 806.04) as a burden. Each species require different and separate search strategies for their distinctiveness. Each patentable distinct species invention may have similar features, but do not share everything in common, therefore it is a burden to locate each different distinct features in each set of distinct claimed invention, a serious searching burden on the examiner. Thus, separate searches are required.
The requirement is still deemed proper and is therefore made FINAL.
Claims 10, 12-15 and 17-19 have been withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected species, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 07/02/2026.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 01/18/2024 and 05/19/2026. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-8 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2018/0174519).
As for claim 1, Kim et al. disclose in Figs. 4-6 and the related text an electronic device, comprising:
a substrate comprising at least one recess; and
at least one electronic unit disposed in the at least one recess, wherein the at least one electronic unit has N1 signal connecting points, and N1 is greater than or equal to 1.
Kim et al. do not teach in a top view direction of the electronic device, the at least one recess has a maximum size D1, the at least one electronic unit has a maximum size C1, and the maximum size D1 and the maximum size C1 satisfy:
0<D1-C1<C1/N1.
It would have been obvious to one having ordinary skill in the art at the time of the invention was made to include in a top view direction of the electronic device, the at least one recess has a maximum size D1, the at least one electronic unit has a maximum size C1, and the maximum size D1 and the maximum size C1 as claimed, in order to optimize the performance of the device. Furthermore, it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
The determination and selection of parameters including dimensions (length, width, thickness, diameter, etc.), via layout/configuration, a pitch/spacing, a total number and a shape thereof, a ratio of dimensions, etc., of a via/plug, pad, trace/wiring, maximum size D1 or C1, etc., in Semiconductor Device (SD) Packaging Technology art is a subject of routine experimentation and optimization to achieve improved metal fill, bonding strength, reliability and reduced stress.
As for claim 2, Kim et al. disclose the electronic device according to claim 1, wherein the substrate comprises:
a base 100;
a circuit layer 103/Tdr1/Tem1 disposed on the base; and
an insulating layer 110 disposed on the circuit layer, wherein the at least one recess 130a is disposed in the insulating layer (Fig. 4).
As for claim 3, Kim et al. disclose the electronic device according to claim 2, further comprising:
an encapsulation layer 160 disposed on the insulating layer and covering the at least one electronic unit 300a; and
a conductive layer AE1 disposed on the encapsulation layer, wherein the encapsulation layer comprises at least one via ECH2/ECH3, and the conductive layer AE1 is electrically connected to the at least one electronic unit through the at least one via (fig. 4).
As for claims 4-6, Kim et al. disclose the electronic device according to claim 4, further comprising a conductive layer AE1/CE disposed on the substrate, the conductive layer is electrically connected to the at least one electronic 300a unit through a first via ECH1 and a second via ECH3 adjacent to the first via.
Kim et al. do not disclose in the top view direction of the electronic device, the at least one recess is circular and has a radius R1, the at least one electronic unit is square and has at least one electrode, the at least one electrode has a width W1, wherein the width W1 satisfies:
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56
144
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wherein the width W1 satisfies:
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68
134
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; and a minimum distance W2 is included between the first via and the second via, wherein the minimum distance W2 satisfies:
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48
156
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.
It would have been obvious to one having ordinary skill in the art at the time of the invention was made to include the limitations, in order to optimize the performance of the device. Furthermore, it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
The determination and selection of parameters including dimensions (length, width, thickness, diameter, etc.), via layout/configuration, a pitch/spacing, a total number and a shape thereof, a ratio of dimensions, etc., of recess, electrode, etc., in Semiconductor Device (SD) Packaging Technology art is a subject of routine experimentation and optimization to achieve improved metal fill, bonding strength, reliability and reduced stress.
As for claim 7, Kim et al. disclose the electronic device according to claim 1, wherein the at least one electronic unit 300a comprises a light emitting diode [0045].
As for claim 8, Kim et al. disclose the electronic device according to claim 7, wherein N1 is 2 (Fig. 4).
As for claim 20, Kim et al. disclose the electronic device according to claim 1, wherein the recess 130a penetrates through (a portion of) the insulating layer 110.
Allowable Subject Matter
Claims 9, 11 and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: “the at least one electronic unit comprises: a first semiconductor layer; a second semiconductor layer; an active layer disposed between the first semiconductor layer and the second semiconductor layer; a first electrode disposed at a side of the first semiconductor layer opposite to the active layer and electrically connected to the first semiconductor layer; and a second electrode disposed at the side of the first semiconductor layer opposite to the active layer and electrically connected to the second semiconductor layer, wherein in the top view direction of the electronic device, the second electrode surrounds the first electrode” as recited in claim 9. Claims 11 and 16 depend on objected claim 9.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TRANG Q TRAN whose telephone number is (571)270-3259. The examiner can normally be reached on Monday-Thursday (9am-4pm).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached on 5712721670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TRANG Q TRAN/Primary Examiner, Art Unit 2811
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