DETAILED ACTION
This Office Action is in response to Application filed on January 18, 2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Species G, an embodiment directed to a plan view of a semiconductor device whose structure is shown in Fig. 11 and Subspecies xvi, an embodiment directed to a cross-sectional view of a semiconductor device taken along lines A-A’ whose structure is shown in Fig. 23 in the reply filed on June 9, 2026 is acknowledged. The traversal is on the ground(s) that Figs. 3 to 23 are plan views and cross-sectional views of stages in a method of manufacturing a semiconductor device according to example embodiments. Applicant’s arguments regarding the species and subspecies listed in Figs. 3-23 are persuasive. It appears that Figs. 1-23 are drawn to a single embodiment. However, there are other species present in Figs. 24-26, so the requirement is still deemed proper and is therefore made FINAL.
Claims 8-9 and 16-20 are withdrawn from examination because they are not drawn to the elected species and subspecies.
Claims 4 and 14 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected species shown in Fig. 25, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on June 9, 2026.
Drawings
The drawings are objected to under 37 CFR 1.83(a) because of the following reasons:
The limitation "the conductive spacer contacting an outer sidewall only of the first spacer structure among the first spacer structure and the second spacer structure" recited in claim 1 is not shown in Fig. 23.
The limitation "the conductive spacer contacting an outer sidewall and an upper surface of the first spacer structure" recited in claim 12 is not shown in Fig. 23.
Any structural detail that is essential for a proper understanding of the disclosed invention should be shown in the drawing. MPEP § 608.02(d). Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim 6 is objected to because of the following informalities:
On line 2 of claim 6, a typo of “selectively” instead of “selectivity” should be corrected.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-7 and 12-13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The limitation "the conductive spacer contacting an outer sidewall only of the first spacer structure among the first spacer structure and the second spacer structure" recited in claim 1 is indefinite because it is not shown in the elected embodiment (Fig. 23). It appears that the conductive spacer (element 535) is in contact with the first spacer structure (element 400), the second spacer structure (element 430), and the third spacer structure (element 450).
Claims 2-7 depend on claim 1, and therefore, claims 2-7 are also indefinite.
The limitation "a material having a high etch selectively" recited in claim 6 is rendered as indefinite because a high etch selectivity is a process dependent feature, and there are different types of etching processes. What type of etching process is used? If it’s a type of wet etching, what is the etchant used? If it’s a type of dry etching, what is being used to do the dry-etching? In other words, claim 6 does not particularly point out and distinctly define the metes and bounds of the claimed subject matter, because Applicants do not specifically claim the type of etching process, etchants or machines used, and process conditions such as a temperature, a pressure, whether an etchant is used in a wet etching, what type of a plasma is used in a dry etching, all of which would affect the etch selectivity.
Claim 7 depends on claim 6, and therefore, claim 6 is also indefinite.
Regarding claim 12, it is not clear what the outer sidewall and upper surface of the first spacer structure refer to, because it appears that the first spacer structure refers to the element 450 that is in contact with the conductive spacer 535. However, due to the round outermost surface of the first spacer structure, there would be no upper surface of the first spacer structure. In other words, for the first spacer structure 450, there is only a contiguous outer sidewall from the topmost portion to the bottommost portion of the first spacer structure 450.
Claim 13 depends on claim 12, and therefore, claim 13 is also indefinite.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 5-7, 10-13, and 15, as best understood, are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lim et al. (US 20220085025 A1) hereinafter referred to as “Lim”.
Regarding claim 1, as best understood, Lim discloses a semiconductor device (Fig. 10), comprising: an active pattern (element 105) ([0083]) on a substrate (element 100); a gate structure (element 160) ([0082]) extending through an upper portion of the active pattern (element 105) in a first direction substantially parallel to an upper surface of the substrate (element 100); a bit line structure (element 325) on a central portion of the active pattern (element 105), because the preposition “on” does not necessarily suggest “directly on”, the bit line structure (element 325) extending in a second direction substantially parallel to the upper surface of the substrate (element 100) and substantially perpendicular to the first direction; a first spacer structure (element 335) and a second spacer structure (element 365) on a first sidewall and a second sidewall of the bit line structure (element 325), respectively, the first sidewall and the second sidewall being opposite sidewalls of the bit line structure (element 325) in the first direction; a lower contact plug (element 405) ([0102]) on each of opposite end portions of the active pattern (element 105); and an upper contact plug (elements 465 and 450) ([0102]) on the lower contact plug (element 405), the upper contact plug (elements 465 and 450) including: a conductive pattern (element 465), and a conductive spacer (element 450) ([0107]) covering a lower surface of the conductive pattern (element 465).
Regarding claim 2, Lim discloses the semiconductor device as claimed in claim 1, wherein the conductive spacer (element 450) includes a metal nitride ([0107]).
Regarding claim 3, Lim discloses the semiconductor device as claimed in claim 1, wherein the first spacer structure (element 335) and the second spacer structure (element 365) are symmetrical with respect to the bit line structure (element 325).
Regarding claim 5, Lim discloses the semiconductor device as claimed in claim 1, further comprising a protection pattern (element 435) between the lower contact plug (element 405) and the upper contact plug (elements 465 and 450).
Regarding claim 6, Lim discloses the semiconductor device as claimed in claim 5, wherein the protection pattern (element 435) includes a material having a high etch selectively ([0105]) with respect to a material included in the conductive spacer (element 450, [0107]).
Regarding claim 7, Lim discloses the semiconductor device as claimed in claim 6, wherein the conductive spacer (element 450) includes a metal nitride ([0107]), and the protection pattern (element 435) includes a metal ([0105]).
Regarding claim 10, as best understood, Lim discloses a semiconductor device (Fig. 10), comprising: an active pattern (element 105) on a substrate (element 100); a gate structure (element 160) extending through an upper portion of the active pattern (element 105) in a first direction substantially parallel to an upper surface of the substrate (element 100); a bit line structure (element 325) on a central portion of the active pattern (element 105), the bit line structure (element 325) extending in a second direction substantially parallel to the upper surface of the substrate (100) and substantially perpendicular to the first direction; a spacer structure (elements 335 and 365) on each of opposite sidewalls of the bit line structure (element 325) in the first direction; a lower contact plug (element 405) on each of opposite end portions of the active pattern (element 105); and an upper contact plug (elements 465 and 450) on the lower contact plug (elements 405), the upper contact plug (elements 465 and 450) including: a conductive pattern (element 465), and a conductive spacer (element 450) covering a lower surface of the conductive pattern (element 465), the conductive spacer (element 450) being on the spacer structure (elements 335 and 365) and the lower contact plug (element 405), and a cross-section in the first direction of the conductive spacer (element 450) having a shape of a staircase.
Regarding claim 11, Lim discloses the semiconductor device as claimed in claim 10, wherein the conductive spacer (element 450) includes a metal nitride ([0107]).
Regarding claim 12, Lim discloses the semiconductor device as claimed in claim 10, wherein the spacer structure (elements 335 and 365) includes a first spacer structure (element 335) and a second spacer structure (element 365) on the opposite sidewalls of the bit line structure (element 325).
Regarding claim 13, Lim discloses the semiconductor device as claimed in claim 12, wherein the first spacer structure (element 335) and the second spacer structure (element 365) are symmetrical with respect to the bit line structure (element 325).
Regarding claim 15, Lim discloses the semiconductor device as claimed in claim 10, further comprising a protection pattern (element 435) between the lower contact plug (element 405) and the upper contact plug (element 465 and 450).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANGELICA ROSE E. GALVAN whose telephone number is (571)270-0122. The examiner can normally be reached Monday - Friday 8:30am - 6:00pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at (571) 270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JAY C KIM/Primary Examiner, Art Unit 2815
/ANGELICA ROSE GALVAN/Examiner, Art Unit 2815
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