Detailed Office Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restriction
Applicant’s election without traverse of claims 1-10, 12-17, and 20-23 in the reply filed on 18 February 2026 is acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 5-10, and 12-15
Claims 1, 5-10, and 12-15 are rejected under 35 U.S.C. 103 as being unpatentable over
Brusberg et al. (2021/0041649; “Brusberg”) in view of Kwok et al. (2013/0108211; “Kwok”).
1. A package comprising: an interposer comprising: a first waveguide; and a first reflector that is optically coupled to the first waveguide; an optical package attached to the interposer, wherein the optical package comprises: an electronic die; a second waveguide; and a second reflector that is optically coupled to the second waveguide, wherein the second reflector is vertically aligned with the first reflector.
Regarding claim 1, Brusberg discloses in figures 2A and 4, and related figures and text, for example, Brusberg Selected Text, embodiments of integrated circuit packages: “[T]he integrated circuit package 200 includes a structured glass article 220 having a glass substrate 222. The glass substrate 222 includes a glass core layer 226 coupled to a first or upper glass cladding layer 228 and a second or lower glass cladding layer 230. The glass substrate 222 also includes cavities 224 that extend through the first glass cladding layer 228 to the glass core layer 226.” Brusberg, paragraph [0031]
Brusberg – Figures 2A and 4, and Selected Text
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[0031] Referring now to FIG. 2A, another embodiment of an integrated circuit package 200 is depicted. In the depicted embodiment, the integrated circuit package 200 includes a structured glass article 220 having a glass substrate 222. The glass substrate 222 includes a glass core layer 226 coupled to a first or upper glass cladding layer 228 and a second or lower glass cladding layer 230. The glass substrate 222 also includes cavities 224 that extend through the first glass cladding layer 228 to the glass core layer 226.
[0032] The structured glass article 220 further includes an optical channel 232 and dielectric layers 234 that are selectively positioned on the glass substrate 222. In the depicted embodiment, the dielectric layers 234 are positioned along the bottom of the cavities 224, along the surface of the glass core layer 226, and also along the opposing second glass cladding layer 230. The optical channel 232 is positioned along the first glass cladding layer 228.
[0033] Referring now to FIG. 2B, the optical channel 232 may include an integrated glass waveguide 340 that is embedded within the optical channel 232 itself. In various embodiments, the glass waveguide 210 may be formed integrally in the glass of the optical channel 232, such that the glass waveguide 340 has a different index of refraction than the remaining portions 342 of the optical channel 232.
[0034] The glass waveguide 340 may be formed in the surrounding optical channel 232 using a laser waveguide writing process, in which a laser introduces pulses that are tightly focused inside the bulk of the optical channel 232, and the laser pulses locally deposit energy in a small volumetric area around the laser focal point to induce local modification of the refractive index inside the optical channel 232.
[0052] Referring now to FIG. 4, another embodiment of an integrated circuit package 500 is depicted. In the depicted embodiment, the integrated circuit package 500 includes a structured glass article 520 having a glass substrate 522. The glass substrate 522 includes a glass core layer 526 coupled to a first or upper glass cladding layer 528 and a second or lower glass cladding layer 530. The glass substrate 522 also includes cavities 524 that extend through the first glass cladding layer 528 to the glass core layer 526.
[0053] The structured glass article 520 further includes an optical channel 532 and dielectric layers 534 that are selectively positioned on the glass substrate 522. In the depicted embodiment, the dielectric layers 534 are positioned along the bottom of the cavities 524, along the surface of the glass core layer 526, and also along the opposing second glass cladding layer 530. The optical channel 532 is positioned along the first glass cladding layer 528. The optical channel 532 is optically coupled to at least one optical connector 580, which may, in turn, be connected to optical cables to carry optical signals to desired locations external to the integrated circuit package 500.
[0054] The integrated circuit package 500 includes a plurality of integrated circuit chips 560, for example, an application specific integrated circuit 562 and a plurality of photonic integrated circuits 570. The application specific integrated circuit 562 and the plurality of photonic integrated circuits 570 are coupled to the glass core layer 526 though the dielectric layer 534. The structured glass article 520 also includes a plurality of optical interfaces 538 that place integrated optical ports 572 of the photonic integrated circuits 570 into optical communication with the optical channel 532 of the structured glass article 520.
[0055] The structured glass article 520 further includes a plurality of electrical bumps 540 that provide attachment and electrical continuity between the application specific integrated circuit 562 and the structured glass article 520 and between the plurality of photonic integrated circuits 570 and the structured glass article 520. The structured glass article 520 also includes redistribution layers 536 that provide electrical continuity throughout the structured glass article 520.
[0056] The electrical bumps 540 and the redistribution layers 536 place the application specific integrated circuit 562 and the plurality of photonic integrated circuits 570 into electrical continuity and into communication with one another. The integrated circuit package 500 also includes a plurality of optical interfaces 538 that place the photonic integrated circuits 570 into optical communication with the optical channel 532 of the structured glass article.
[0057] Placing the integrated optical ports in the photonic integrated circuits 570 may allow for more accurate positioning of the optical ports relative to the interfacing components of the integrated circuit package 500. In one example, the photonic integrated circuits 570 may be positioned with a high degree of accuracy relative to the optical channels 532 of the structured glass article 520. In various embodiments, the photonic integrated circuits 570 may be held in position by assembly tooling that locates the photonic integrated circuits 570 according to surfaces having known positional orientations relative to the optical ports. For example, tooling may contact the photonic integrated circuits 570 along one locating face and at two positions at faces oriented in transverse directions to the locating face. The tooling, therefore, maintains the proper location and orientation of the photonic integrated circuit 570 relative to the optical channel 532. The tooling may maintain the photonic integrated circuit 570 in such an orientation throughout melting and resolidification of the electrical bumps.
Further regarding claim 1, Kwok discloses in figures 1 and 7A-F, and related figures and text, for example, Kwok Selected Text, embodiments of integrated photonics comprising silicon photonic layers 102, 104, and 105 optically connected by vertical waveguides 112 and micromirrors 116. Kwok, figures 1 and 7A-F, and related figures and text, for example, Kwok Selected Text.
Kwok - Figures 1 and 7A-F, and Selected Text
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[0043] FIG. 1 illustrates an integrated circuit 100 with an optical bus 130 defining an optical path 126 passing through a three-layer stack 100 comprising three layers 102, 104, 106. The three layers 102, 104, 106 are stacked one upon another (from bottom to the top of the drawing), and each comprise a semiconductor substrate. As shown in FIG. 1, the layers 102 are elongated in cross-section. While three layers 102, 104, 106 are depicted in FIG. 1, more or fewer layers may be practiced without departing from the scope of the invention.
[0044] Six vias 110A, 110B, 110C, 110D, 110E, 110F, by way of example, are depicted in vertical arrangements through the thickness dimension of the relevant layers 102, 104, 106. The vias 110A-110F are elongated cavities through the layers and are filled by polymer waveguides 112A-112F, respectively. As depicted in FIG. 1, each polymer waveguide comprises a vertical waveguide component and a horizontal waveguide component. To simplify the drawing, only the horizontal waveguide component 128 of the polymer waveguide 112F through layer 102 is so labelled.
[0045] The optical bus 130 comprises polymer waveguides 112 in the vias 110, micromirrors 112, and polymer material (e.g. silica) 120, as an optical coupler, across the semiconductor substrate in an orientation that is out of plane with the polymer waveguides 112. Furthermore, the polymer waveguide material 112 in the vias 110 is injected in the by-pass channel beside the optical coupler 120, but is not a waveguide since light travels along the silica waveguide 120. Each die layer may comprise an active circuit (not shown in FIG. 1) formed in the relevant semiconductor substrate 102, 104, 106. If the optical bus 130 is not to be coupled to an active circuit of any layer, the relevant bypass channel 118 may omit an optical coupler 120 and be filled only with polymer waveguide 112, forming part of the optical bus 130. In layers, where the optical coupler 120 is present, the optical coupler 120 forms part of the optical bus 130.
[0046] Rear 45.degree. micromirrors 114A-114F are each disposed adjacent the top of the respective vias 110A-110F and optically coupled to the polymer waveguides 112A-112F and the optical couplers 120, where a layer has such an optical coupler, and polymer waveguides in the bypass channels 118, where a layer does not have an optical coupler. As shown for layer 102, the optical couplers 120A and 120E are butt coupled to the horizontal components of polymer waveguides 112A and 112F in the vias 110A and 110F, respectively. Similar connections apply to the other layers 104 and 106. The optical bus 130 also comprises a number of front 45.degree. micromirrors 116A-114D in layers 102 and 104 of FIG. 1.
[0047] In any layer 102, 104, 106, the optical bus 130 can comprise polymer waveguides 112 in vias 110, the micromirrors 114 and 116, and optical coupler 120 defining an optical path 126 through the integrated circuit 100. In the embodiment of FIG. 1, the substrates 102, 104, 106 are preferably silicon substrates; the vias 110 are through-silicon vias; and the optical couplers are silica-to-silicon couplers.
[0048] The optical axis of each of the optical coupler 120 is disposed orthogonally or substantially orthogonally to the longitudinal axis of the polymer waveguides 112 in the vias 110. The optical couplers 120 are fabricated from a material reducing optical mismatch between the polymer waveguide 112 and the semiconductor material of the active device. A top layer 108 overlays the die layer 106 (e.g., for experimental purposes, this might be glass). The bypass channel 118 is situated adjacent to the optical coupler 120.
[0049] The micromirrors 116 are face-up micromirrors, and the micromirrors 114 are face-down micromirrors. Fabrication of the micromirrors 116 and 114 is described in greater detail hereinafter. In die layer 106, the optical bus 130 comprises a pair of vias 110C and 110D formed in the die layer 106. The vias 110C and 110D of the layer 106 are separated from one another. The same applies to the vias 110 in the other layers 102 and 104. Micromirrors 114C and 114D of the layer 106 are formed adjacent the through silicon vias 110C and 110D. An optical coupler 120C is coupled to the polymer waveguide 112C and the active circuit (not shown) of the layer 106.
[0050] More particularly, as shown in FIG. 1, the optical path 126 is formed through silicon stack layers 102, 104, and 106. The stack 100 has self-written polymer waveguides 112 formed in TSVs 110 through the layers 102, 104, 106. A light beam 126 enters the stack at port X on the left, traverses the stack both vertically and horizontally so as to exit port Y on the right side of the stack through the bottom surface, as depicted in FIG. 1. A bonding material 124 is used between die layers 102, 104, 106 and layer 108 to adhere or fasten the layers in the stack. A layer of bonding material is approximately 1-2 um thick, and could be an Au--Sn eutectic bond, for example.
[0051] The optical bus 130 aims to establish a low-loss single mode optical link between the silicon photonics in the stack 102, 104, 106 of integrated circuits 100 and the polymer interconnects on the PCB (not shown in FIG. 1). The cross sectional schematic of the optical link as illustrated in FIG. 1 comprises at each level: (i) through silicon vias (TSV) 110 with a monolithically integrated 45.degree. rear (facing down) micro-mirror 114 at the top of the TSV; (ii) planar silica waveguide coupler 120, and (iii) 45.degree. front (facing-up) micro-mirror 114. The through silicon hole 110 is connected to the facing up 45.degree. micro-mirror 116 by a micro-machined by-pass channel 118 that runs along side of the silica waveguide coupler. This is shown in greater detail in FIG. 2. The optical link and the micro-machined by-pass channel are sealed by Au/Sn eutectic bonding after alignment and lock has been established.
[0063] FIGS. 7A to 7F illustrate the fabrication of a rear 45.degree. micromirror. FIG. 8 is a flow diagram illustrating the method 800 to fabricate the micromirror of FIG. 7. Processing commences at step 810. In step 810, (an ultra smooth) front 45.degree. micromirror 720 is formed on the (100) silicon substrate 710 (P-type substrate), as shown in FIG. 7A. The bottom surface of the substrate 710 has a SiO.sub.2 layer 730 formed therein. In step 812, phosphorous diffusion is carried out to form the N+ diffused layer 740 over the top surface of the substrate 710, including the face up micromirror 720, as shown in FIG. 7B. The electrochemical etch stop is a technique to stop the etching process from the back side of the wafer--determined by the thickness of the diffused layer on the front side. In step 814, chromium (Cr) film deposition and photolithographical patterning is applied, which acts as the etch mask (FIG. 7C) for rear 45.degree. micromirror membrane when reactive ion etching is conducted from the front side of the wafer, as shown in FIG. 7D. Chromium is deposited all across the wafer; the photolithographic patterning as determined by the mask design leaves the Cr where Cr is required.
[0064] In step 816, a backside etching Window is opened in the SiO2 layer 730 and is followed by electrochemical TMAH etch of the silicon substrate 710 beneath the mesa structure of the N+ diffused layer 740 and overlying Cr layer 750, as depicted in FIG. 7D. The portion of the silicon substrate beneath the mesa structure N+ diffused layer 740 is entirely etched away.
[0065] In step 818, the micromirror membrane 740 is RIE etched from the front, removing the N+ diffused layer 740 from the top surface of the substrate and between the substrate portions 710 except where the Cr layer 750 overlays the remaining portion of layer 740, as depicted in FIG. 7E. In step 820, the Cr layer 750 is removed leaving behind the reversed-Z structure of layer 740 projecting over the lip or edge of left side of the substrate 710, and a thin film of gold (Au) is deposited on the lower surface of layer 740 as a reflective layer on the rear 45.degree. micromirror surface, as shown in FIG. 7F. Processing then terminates
Consequently, in light of Kwok’s 3D optical interconnects, it would have been obvious to one of ordinary skill in the art to modify Brusberg’s embodiments to disclose: an interposer comprising: a first waveguide; and a first reflector that is optically coupled to the first waveguide; an optical package attached to the interposer, wherein the optical package comprises: an electronic die; a second waveguide; and a second reflector that is optically coupled to the second waveguide, wherein the second reflector is vertically aligned with the first reflector; Kwok, figures 1 and 7A-F, and related figures and text, for example, Kwok Selected Text; Brusberg, figures 2A and 4, and related figures and text, for example, Brusberg Selected Text; because the resulting configuration would facilitate ‘establishing low-loss single mode optical links between silicon photonics.’ Kwok, paragraph [0051].
Regarding claims 5-8, as dependent upon claim 1, independent claim 9 and claims 10 and 12-15, as dependent upon claim 9, it would have been obvious to one of ordinary skill in the art to modify Brusberg in view of Kwok’s embodiments to disclose:
5. The package of claim 1, wherein the optical package is attached to the interposer by solder bumps. Kwok, figures 1 and 7A-F, and related figures and text, for example, Kwok Selected Text; Brusberg, figures 2A
6. The package of claim 1, wherein the optical package further comprises a photonic component and an electronic die, wherein the photonic component is optically coupled to the first waveguide and electrically coupled to the electronic die.
7. The package of claim 1further comprising a logic die connected to the interposer. Kwok, figures 1 and 7A-F, and related figures and text, for example, Kwok Selected Text; Brusberg, figures 2A
8. The package of claim 1, wherein the first waveguide and the second waveguide comprise silicon nitride. Kwok, figures 1 and 7A-F, and related figures and text, for example, Kwok Selected Text; Brusberg, figures 2A
9. A package comprising: a first optical structure comprising an electronic die, a plurality of conductive lines, a plurality of photonic components, a plurality of first waveguides, and a plurality of first reflective structures; and a second optical structure bonded to the first optical structure, wherein the second optical structure comprises a plurality of second waveguides and a plurality of second reflective structures, wherein individual first reflective structures of the plurality of first reflective structures respectively correspond to individual second reflective structures of the plurality of second reflective structures. Kwok, figures 1 and 7A-F, and related figures and text, for example, Kwok Selected Text; Brusberg, figures 2A
10. The package of claim 9, wherein the first reflective structures of the plurality of first reflective structures comprise a metallic layer. Kwok, figures 1 and 7A-F, and related figures and text, for example, Kwok Selected Text; Brusberg, figures 2A
12. The package of claim 9, wherein the plurality of second waveguides and the plurality of second reflective structures are within a redistribution structure of the second optical structure. Kwok, figures 1 and 7A-F, and related figures and text, for example, Kwok Selected Text; Brusberg, figures 2A
13. The package of claim 12 further comprising local interconnect structures within the redistribution structure. Kwok, figures 1 and 7A-F, and related figures and text, for example, Kwok Selected Text; Brusberg, figures 2A
14. The package of claim 9 further comprising a third optical structure comprising a plurality of third waveguides and a plurality of third reflective structures, wherein the second optical structure is bonded to the third optical structure, wherein individual third reflective structures of the plurality of the third reflective structures respectively correspond to individual second reflective structures of the plurality of second reflective structures. Kwok, figures 1 and 7A-F, and related figures and text, for example, Kwok Selected Text; Brusberg, figures 2A
15. The package of claim 14, wherein the second optical structure overlaps the first optical structure and the third optical structure. Kwok, figures 1 and 7A-F, and related figures and text, for example, Kwok Selected Text; Brusberg, figures 2A and 4, and related figures and text, for example, Brusberg Selected Text.
because the resulting configurations would facilitate ‘establishing low-loss single mode optical links between silicon photonics.’ Kwok, paragraph [0051].
Claims 2-4, 16-17, and 21-22
Claims 2-4, 16-17, and 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Brusberg et al. (2021/0041649; “Brusberg”) in view of Kwok et al. (2013/0108211; “Kwok”), as applied in the rejection of claims 1, 5-10, and 12-15, and further in view of Bowen et al. (2017/0261703; “Bowen”) .
Regarding claims 2-4, 16-17, and 21-22, Bowen discloses in figure 1, and related figures and text, for example, Bowen Selected Text, multilayer embodiments comprising interposers, reflective configurations and lenses. Bowen, figure 1, and related figures and text, for example, Bowen Selected Text.
Bowen - Figure 1, and Selected Text
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[0010] Referring to FIGS. 1 and 2, two embodiments of interposer 100, 200 are shown, respectively. In these embodiments, the interposer 100, 200 couples an optical component 101, 201 to an optical conduit 105, 205. To this end, the optical component 101, 201 is optically coupled to a first lens component 102, 202 having a first lens 150, 250. The interposer also comprises a second lens component 103, 203, having at least a second lens 151, 251. The first and second lenses are configured to define an expanded-beam coupling therebetween. Optically coupled to the second lens component is at least one reflective surface 104, 204. A first optical path 110, 210 is at least partially defined between said optical component and said first lens to accommodate a diverging light beam from said optical component to said first lens. A second optical path 120, 220 is at least partially defined between the second lens 151, 251 and the at least one reflective surface 104, 204 to accommodate a converging light beam from said second lens and said at least one reflective surface. The interposer comprises a separable interface 130, 230 along said second optical path. The interposers 100, 200 are described in detail below. It should be understood that the embodiment(s) disclosed herein are merely illustrative of the invention and should not be construed as limiting the invention unless expressly indicated.
[0015] Often, although not necessarily, the optical axis 160, 260 is generally perpendicular to the first optical path 110, 210. In such an embodiment, a reflective surface, grating or similar optical mode matching element 161, 261 known for changing the direction and/or mode diameter and/or convergence/divergence angles of the light beam may be used in the optical component, or a discrete component may be used to bend the light between the optical conduit and the optical component. In one embodiment, the mode matching element comprises a diffractive optical element (DOE) which is a thin phase element that operates by means of interference and diffraction to produce calculated distributions of light. DOEs are sometimes also referred to as gratings, holographic optical elements, and sub-wavelength diffraction gratings. The DOE is interfaced with a waveguide using known techniques such as an adiabatic taper waveguide transition. In one embodiment, the DOE has a refractive index close to or equal to that of the material of the waveguide 170, 270. By designing the amount of difference in refractive index between the waveguide material and that of the DOE material, the coupling efficiency of the waveguide and DOE can be optimized. For example, if the waveguide is silicon (Si), Applicants realized that a DOE comprising silicon nitride (Si.sub.3N.sub.4) has an improved coupling efficiency over a DOE formed directly in silicon. Other embodiments will be known or obvious to those of skill in the art in light of this disclosure.
[0016] In the embodiment of FIGS. 1 and 2, the waveguide 170, 270 is integral to the optical component 101, 201. It should be understood, however, that the waveguide may be discrete and freestanding from the optical component. Alternatively, the waveguide and DOE may be disposed on a second substrate (not shown). The second substrate may be for example, silicon, PCB, flex material, glass, or polyimide. In such an embodiment, the pads/pillars for alignment and thermal/electrical interconnection with the interposer as described below in connection with the substrate may be used. In this respect, it should be noted that the invention may be practiced without a fully integrated optical component.
[0017] The first and second lens components serve to couple light between the first and second optical paths. Specifically, the first lens component receives light, which is usually diverging, and through the first lens redirects the beam to the second lens and the second optical path. For example, between the first and second lenses, the beam may be collimated as shown in FIGS. 1 and 2. Therefore, when the beam is redirected by the first lens 150, 250 to the second lens 151, 251, the beam is communicated from the first optical path to the second optical path. It should be understood that the beam may travel in the opposite direction in certain embodiments of the interposer; and thus the first lens 150, 250 and the second lens 151, 251 would communicate the beam from the second optical path to the first optical path in such a configuration. If the beam is collimated by the first lens, then a second lens is used in the second lens component to focus the light as shown in FIGS. 1 and 2.
[0020] The lenses 150, 151, and 250, 251 may be integral to the respective lens components or discrete. In one embodiment, the lenses are integral with the respective lens components. For example, referring to FIGS. 1 and 2, the first lens 150, 250 is defined on the top surface 102b, 202b of the first lens component 102, 202, and the second lens 151, 251 is defined on the bottom surface 103a, 203a of the second lens component 103, 203. Alternatively, the first lens could be defined on the bottom surface 102a, 202a of the first lens component 102, 202, and/or the second lens could be defined on the top surface 103b, 203b of the second lens component 103, 203. Having the lenses integrally formed in the silicon lens components minimizes differences in the thermal expansion coefficients among the different components defining the first and second optical paths. Nevertheless, it should be understood that other embodiments exist in which the lens is discrete from the lens components. For example, the first and second lens may be discrete ball lenses of an optically clear material, such as glass or quartz, which are held in place by the first and second lens components.
[0021] The reflective surface 104, 204 serves to bend the light between the second optical path and the optical conduit 105, 205. Suitable reflective surfaces are well known and include, for example, reflective and refractive light-bending surfaces. The reflective surface may be a discrete component such as a mirror element that is attached to or disposed on the surface of the second lens component or it may be integrally formed in a component of the interposer. For example, in an alternative embodiment (not shown), the reflective surface is etched in the top surface of the second lens component along with grooves such that the reflective surface optically couples an optical conduit in the groove with the second optical path. Still other embodiments will be known or obvious to one of skill in the art in light of this disclosure.
Consequently, it would have been obvious to one of ordinary skill in the art to modify Brusberg in view of Kwok’s embodiments, as applied in the rejection of claims 1, 5-10, and 12-15, to disclose:
2. The package of claim 1 further comprising a first lens between the interposer and the optical package, wherein the first lens, the first reflector, and the second reflector are vertically aligned. . Kwok, figures 1 and 7A-F, and related figures and text, for example, Kwok Selected Text; Brusberg, figures 2A and 4, and related figures and text, for example, Brusberg Selected Text; Bowen, figure 1, and related figures and text, for example, Bowen Selected Text.
3. The package of claim 2, wherein the first lens is attached to the optical package, and further comprising a second lens between the interposer and the optical package, wherein the second lens and the first lens are vertically aligned. . Kwok, figures 1 and 7A-F, and related figures and text, for example, Kwok Selected Text; Brusberg, figures 2A and 4, and related figures and text, for example, Brusberg Selected Text; Bowen, figure 1, and related figures and text, for example, Bowen Selected Text.
4. The package of claim 2, wherein the first lens comprises a laser- written material. . Kwok, figures 1 and 7A-F, and related figures and text, for example, Kwok Selected Text; Brusberg, figures 2A and 4, and related figures and text, for example, Brusberg Selected Text; Bowen, figure 1, and related figures and text, for example, Bowen Selected Text.
16. The package of claim 9further comprising a plurality of lenses attached to the second optical structure, wherein the lenses of the plurality of lenses are between the first optical structure and the second optical structure. . Kwok, figures 1 and 7A-F, and related figures and text, for example, Kwok Selected Text; Brusberg, figures 2A and 4, and related figures and text, for example, Brusberg Selected Text; Bowen, figure 1, and related figures and text, for example, Bowen Selected Text.
17. A structure comprising: an optical interposer comprising an interconnect structure over a photonic component, wherein the interconnect structure is electrically coupled to the photonic component; an electronic die bonded to a top side of the optical interposer, wherein the electronic die is electrically coupled to the interconnect structure; forming an optical interconnect structure on a bottom side of the optical interposer, wherein the optical interconnect structure comprises a first waveguide and a first reflector, wherein the first reflector is optically coupled to the first waveguide; a lens attached to a bottom side of the optical interconnect structure, wherein the lens is optically coupled to the first reflector; conductive connectors on the bottom side of the optical interconnect structure: and a composite interposer attached to the conductive connectors, wherein the composite interposer comprises a second waveguide and a second reflector, wherein the second reflector is optically coupled to the lens. . Kwok, figures 1 and 7A-F, and related figures and text, for example, Kwok Selected Text; Brusberg, figures 2A and 4, and related figures and text, for example, Brusberg Selected Text; Bowen, figure 1, and related figures and text, for example, Bowen Selected Text.
21. The structure of claim 17, wherein the first reflector overlaps the second reflector. . Kwok, figures 1 and 7A-F, and related figures and text, for example, Kwok Selected Text; Brusberg, figures 2A and 4, and related figures and text, for example, Brusberg Selected Text; Bowen, figure 1, and related figures and text, for example, Bowen Selected Text.
22. The structure of claim 17, wherein the composite interposer comprises at least one metal line that is closer to the optical interconnect structure than the second waveguide. Kwok, figures 1 and 7A-F, and related figures and text, for example, Kwok Selected Text; Brusberg, figures 2A and 4, and related figures and text, for example, Brusberg Selected Text; Bowen, figure 1, and related figures and text, for example, Bowen Selected Text.
because the resulting configurations would facilitate ‘establishing low-loss single mode optical links between silicon photonics;’ Kwok, paragraph [0051]; while predictably controlling expanded beam coupling. Bowen, abstract.
Claim 20
Claim 20, as dependent upon claim 17, is rejected under 35 U.S.C. 103 as being unpatentable over Brusberg et al. (2021/0041649; “Brusberg”) in view of Kwok et al. (2013/0108211; “Kwok”), as applied in the rejection of claims 1, 5-10, and 12-15, and further in view of Bowen et al. (2017/0261703; “Bowen”), as applied in the rejection of claims 2-4, 16-17, and 21-22, and further in view of Jiang, Jia (2016/0109659; “Jiang”).
Regarding claim 20, Jiang discloses in figure 5 and selected text, “[B]onding the flipped silica chip 506 and the silicon chip 504 includes gluing the flipped silica chip 506 to the silicon chip 504 together by a refractive index matching glue (either organic or inorganic).” Jiang, paragraph [0038].
Jiang – Figure 5, and Selected Text
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[0038] FIG. 5 is a schematic diagram illustrating an embodiment method 500 for fabricating a chip-fiber coupler. The method 500 includes fabricating a silica chip 502 and a silicon chip 504. A flipped silica chip 506 is connected to the silicon chip 504 to produce a bonded silica-silicon chip 508. In an embodiment, connected includes stacking or otherwise combining the flipped silica chip 506 and the silicon chip 504 in a fact-to-face manner. In an embodiment, the chips are connected by bonding where bonding the flipped silica chip 506 and the silicon chip 504 includes gluing the flipped silica chip 506 to the silicon chip 504 together by a refractive index matching glue (either organic or inorganic). In an embodiment, bonding the flipped silica chip 506 and the silicon chip 504 includes affixing the flipped silica chip 506 to the silicon chip 504 by a molecular force bond using a fine and smooth surface. In an embodiment, the interface between the flipped silica chip 506 bonded to the silicon chip 504 does not have an apparent optical interface. In particular, the top cladding of the silica chip 502 is bonded to the top cladding of the silicon chip 504. In an embodiment, the top cladding of the silica chip 502 and the top cladding of the silicon chip 504 have a substantially same refractive index. However, it will be understood by those skilled in the art that it is not necessary that the silica chip 502 and the silicon chip 504 have substantially the same refractive index. In an embodiment, the ideal situation is to couple the silica chip 502 to the silicon chip 504 so that there is no optical interface between them. That means that the refractive index of both cladding (silicon chip and silica chip) is substantially the same. This allows for a simplified optical design and fabrication. However, in an embodiment, if the refractive index is different between the two claddings, both grating designs can be modified to allow the light to be coupled into the second grating at a proper angle. Thus, in this embodiment, an optical interface between the two gratings is acceptable. The silica chip 502 is fabricated to include a bottom cladding, a silica waveguide and silica grating, and a top cladding. The silicon chip 504 includes a silicon waveguide, a silicon grating, and a top cladding surrounding the silicon waveguide and the silicon grating. The flipped silica chip 506 is bonded to the silicon chip 504 such that the resulting bonded silica-silicon chip 508 is configured to couple light from the silicon chip 504 to the flipped silica chip 506 via the grating in each of the chips 504, 506. The silica chip 506 is also configured to optically couple to an optical waveguide 510, such as an optical fiber.
Consequently, it would have been obvious to one of ordinary skill in the art to modify Brusberg in view of Kwok and further in view of Bowen’s embodiments such that the lens is attached to the bottom side of the optical interconnect structure by an optical glue; Jiang, figure 5, and related figures and text; Kwok, figures 1 and 7A-F, and related figures and text, for example, Kwok Selected Text; Brusberg, figures 2A and 4, and related figures and text, for example, Brusberg Selected Text; Bowen, figure 1, and related figures and text, for example, Bowen Selected Text; because the resulting configuration would facilitate ‘establishing low-loss single mode optical links between silicon photonics;’ Kwok, paragraph [0051]; while predictably controlling expanded beam coupling; Bowen, abstract; and increasing coupling efficiency. Jiang, abstract.
Claim 23
Claim 23, as dependent upon claim 17, is rejected under 35 U.S.C. 103 as being unpatentable over Brusberg et al. (2021/0041649; “Brusberg”) in view of Kwok et al. (2013/0108211; “Kwok”), as applied in the rejection of claims 1, 5-10, and 12-15, and further in view of Bowen et al. (2017/0261703; “Bowen”), as applied in the rejection of claims 2-4, 16-17, and 21-22, and further in view of Pelley et al. (2014/0363172; “Pelley”).
Regarding claim 23, Pelley discloses in figures 5 and 6, and reflated figures and text, for example, Pelley Selected Text, “After attachment to the system board 200, the mounted plurality of die 210, 220, 230, 240, 250 are molded or encapsulated with an encapsulation packaging to form a protective packaging or housing 260 having top and side surfaces.”
Pelley – Figures 5 and 6, and Selected Text
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[0041] To illustrate the routing of light beams through the different die, reference is now made to FIG. 6 which shows a cross-sectional side view of the die stack of FIG. 5 after assembly and packaging. In selected embodiments, the die stack may be formed by assembling a stack of wafers in a wafer stack which is then singulated to form the die stack, though in other embodiments, a plurality of singulated die may be assembled as a die stack. As illustrated, the plurality of die 220, 230, 240, 250 are attached to the first optical source die 210 with appropriate alignment of any electrical and optical through silicon vias (TSVs), such as by using one or more adhesive materials, compression bonding, or any other suitable attachment mechanism. The optical source die 210 is also electrically connected via the conductor array 204 and contact pads 202 to a top surface of the system board 200, alone or in combination with additional optical routing structures (not shown) for routing optical signals to and through the system board 200. On the opposite surface of the system board 200, external conductors 270, such as copper pillars, solder balls or flip chip interconnects, are connected in a ball grid array (BGA) configuration or other suitable packaging configuration. As depicted, the thermoelectric conductor array 204 is positioned between the system board 200 and the optical source die 210 to make electrical connection with the contact pads 202 on the system board 200. In selected embodiments, the solder ball or flip chip array 204 is are soldered in place on the system board 200 in a reflow furnace, and then the stacked die assembly is placed on the solder ball or flip chip array 204 for a second reflow. In other embodiments, the thermoelectric conductor array 204 may be implemented with solder ball or flip chip arrays that are formed as reflow solder balls on the bottom of the die stacks. In yet another embodiment, the solder ball or flip chip array 204 is placed on the system board 200 with flux, followed by placing the die stacks and reflowing the entire group together. After attachment to the system board 200, the mounted plurality of die 210, 220, 230, 240, 250 are molded or encapsulated with an encapsulation packaging to form a protective packaging or housing 260 having top and side surfaces.
[0085] By now it should be appreciated that there is provided herein a die assembly apparatus and associated methods of fabrication and operation in which optical and electrical TSVs are used to distribute a single laser source to different die modulators. In the disclosed apparatus embodiments, there is provided a first die (e.g., a processor die) and one or more receiving die (e.g., one or more memory die and/or processor die). In selected embodiments, the first die and one or more receiving die are attached together in a die stack module. As formed, the first die includes with a laser source for generating a source unmodulated optical beam, and one or more first optical beam routing structures for optically transmitting the source unmodulated optical beam through the first die. In selected embodiments, the first optical beam routing structures at the first die include a first optical waveguide for receiving the source unmodulated optical beam from the laser source, and a first optical mirror structure for receiving the source unmodulated optical beam from the first optical waveguide and deflecting the source unmodulated optical beam as a deflected source unmodulated optical beam toward the receiving die. For example, the first optical mirror structure may be formed as an angled interface deflection surface that is offset by 45 degrees from the lateral plane of the first die for perpendicularly deflecting the source unmodulated optical beam. As formed, each receiving die includes one or more second optical beam routing structures for optically receiving at least a portion of the source unmodulated optical beam from the one or more first optical beam routing structures. In selected embodiments, the second optical beam routing structures on each receiving die include a second optical through silicon via structure for receiving the deflected source unmodulated optical beam from the first die: a second optical mirror structure for deflecting the deflected source unmodulated optical beam from the second optical through silicon via structure as a second deflected source unmodulated optical beam toward a modulator on said receiving die; and a second optical beam waveguide for transmitting the second deflected source unmodulated optical beam to the modulator on said receiving die. Each receiving die also includes a modulator for generating an output modulated optical beam of modulated monochromatic coherent light which is encoded at said modulator in response to electrical signal information. In addition, each receiving die includes one or more third optical beam routing structures for optically transmitting the output modulated optical beam signal through the receiving die. In selected embodiments, the third optical beam routing structures on each receiving die include a third optical beam waveguide for receiving the output modulated optical beam signal from the modulator on said receiving die, and a third optical mirror structure for receiving the output modulated optical beam signal from the third optical beam waveguide and deflecting the output modulated optical beam signal toward the first die. In addition, the disclosed apparatus may include a plurality of non-intersecting optical beam output routing structures for optically routing the output modulated optical beam signal from each receiving die to the first die. In selected embodiments, the first die and the receiving die are attached in a die stack that is connected to a conductor array and mounted on a system board. In addition, the die stack may be at least partially encapsulated by a packaging structure formed with mold compound. To provide a transparent output optical signal path from the packaging structure for an output laser beam signal generated by the one or more of receiving die, the packaging structure may be formed with a transparent mold compound or may include a transparent layer or insert formed in the mold compound.
Consequently, it would have been obvious to one of ordinary skill in the art to modify Brusberg in view of Kwok and further in view of Bowen’s embodiments to disclose an encapsulant that laterally encircles the optical interposer; Pelley, figures 5 and 6, and related figures and text; Kwok, figures 1 and 7A-F, and related figures and text, for example, Kwok Selected Text; Brusberg, figures 2A and 4, and related figures and text, for example, Brusberg Selected Text; Bowen, figure 1, and related figures and text, for example, Bowen Selected Text; because the resulting configuration would facilitate ‘establishing low-loss single mode optical links between silicon photonics;’ Kwok, paragraph [0051]; while predictably controlling expanded beam coupling; Bowen, abstract; and facilitating incorporating optical communications in die stacks. Pelley, paragraph [0023].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETER RADKOWSKI whose telephone number is (571)270-1613. The examiner can normally be reached M-Th 9-5.
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/PETER RADKOWSKI/Primary Examiner, Art Unit 2874
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