DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 5, 9, 11, 13 and 20 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Lee et al. (US 2019/0155417) hereinafter “Lee”.
Regarding claim 1, Fig. 4 of Lee teaches a display device comprising: a display module including a display panel (Paragraph 0009) and an input sensing unit (Paragraph 0039); and a circuit board connected to the display module, wherein the circuit board includes: a first signal line (Paragraph 0029 Data line or Gate line where the gate and data lines are perpendicular to each other) electrically connected to the display panel and having at least a portion extending in a first extension direction; a sensing line (Item TS) electrically connected to the input sensing unit and having at least a portion extending in a second extension direction crossing the first extension direction; and a shielding layer (Item BM) interposed between the first signal line (Either of data or gate lines) and the sensing line (Item TS) and having a first opening (One of Item H; See Picture 1 below) and a second opening spaced apart (A second of Item H; See Picture 1 below) from each other while interposing the sensing line (Item TS) in a plan view, wherein at least a portion of each of the first opening and the second opening extends in the second extension direction, wherein the sensing line crosses the first signal line (Either of the data or gate line) between the first opening and the second opening in the plan view, and wherein a distance between the first opening and the second opening is equal to a width of the sensing line in the plan view (Where the signal line TS separates the first and second opening).
PNG
media_image1.png
483
688
media_image1.png
Greyscale
Picture 1 (Labeled version of Lee Fig. 4)
Regarding claim 2, Fig. 4 of Lee further teaches where a portion of the first signal line (One of the data line or gate line) is exposed from the shielding layer (Item BM) through each of the first opening and the second opening in the plan view.
Regarding claim 3, Fig. 4 of Lee further teaches where the circuit board further includes a second signal line (Any of the data line and gate line) electrically connected to the display panel, spaced apart (Where the there is a number of data lines that extend in parallel in the same direction and a number of gate lines that extend in parallel in a same direction that is parallel to the direction of the data lines) from the first signal line, and extending in parallel to the first signal line, and where the second signal line crosses the sensing line (Item TS), between the first opening and the second opening in the plan view.
Regarding claim 5, Fig. 4 of Lee further teaches where the circuit board further includes: a second signal line (Another of the data or gate lines) electrically connected to the display panel, spaced apart from the first signal line (The data or gate line), and extending in parallel to the first signal line, wherein the shielding layer has a third opening and a fourth opening additionally defined in the shielding layer, arranged in the second extension direction from the first opening and the second opening, respectively, and spaced apart from each other while interposing the sensing line (Item TS) between the third opening and the fourth opening, wherein the second signal line crosses the sensing line (Item TS) between the third opening and the fourth opening in the plan view, and wherein a distance between the third opening and the fourth opening is equal to the width of the sensing line in the plan view.
Regarding claim 9, Fig. 4 of Lee further teaches where the first signal line (Data lines or gate lines) is configured to transmit a high-frequency signal (Where the data signals or scan signals are sent through the data lines or gate lines at a high frequency).
Regarding claim 11, Fig. 4 of Lee further teaches where the circuit board further includes: a base layer (Substrate) under the first signal line (Data line or gate line); a first insulating layer (Item ENCAP) interposed between the first signal line and the shielding layer (Item BM); and a second insulating layer (Item OC) interposed between the shielding layer (Item BM) and the sensing line (Item TS).
Regarding claim 13, Fig. 4 of Lee teaches a display device comprising: a display module including a display panel (Paragraph 0009) and an input sensing unit (Paragraph 0039); and a circuit board connected to the display module, wherein the circuit board further includes: a first signal line (Paragraph 0029 Data line or Gate line where the gate and data lines are perpendicular to each other) electrically connected to the display panel; a shielding layer (Item BM) on the first signal line and including a first extension region and a second extension region spaced apart from each other, and a peripheral region surrounding the first extension region and the second extension region; and a sensing line (Item TS) on the shielding layer, electrically connected to the input sensing unit, and including a first sensing line having a portion overlapped with the first extension region and a second sensing line having a portion overlapped with the second extension region, wherein the first sensing line crosses the first signal line (Either of data or gate lines) in a region overlapped with the first extension region, and the second sensing line crosses the first signal line in a region overlapped with the second extension region in a plan view, and wherein a width of the first extension region is equal to a width of the first sensing line (Item TS), in a region in which the first extension region is overlapped with the first sensing line (Item TS).
Regarding claim 20, Fig. 4 of Lee teaches a display device comprising: a display module configured to provide an image and to sense an external input (Paragraph 0004); and a circuit board connected to the display module, wherein the circuit board further includes: a first line (Paragraph 0029 Data line or Gate line where the gate and data lines are perpendicular to each other) electrically connected to the display module to transmit a high-frequency signal (Where data and scan signals are sent through the data and gate lines at a high frequency) and having at least a portion extending in a first extension direction; a second line (Item TS) electrically connected to the display module, and having at least a portion extending in a second extension direction crossing the first extension direction; and a shielding layer (Item BM) interposed between the first line and the second line and having a first opening and a second opening (See Fig. 1 above) spaced apart from each other while interposing the second line (Item TS), in a plan view, wherein at least a portion of each of the first opening and the second opening extends in the second extension direction, wherein the second line crosses the first line between the first opening and the second opening in the plan view, and wherein a distance between the first opening and the second opening is equal to a width of the second line (Item TS) in the plan view.
Claims 1, 10, 13, 19 and 20 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Hwang et al. (US 2018/0166507) hereinafter “Hwang”.
Regarding claim 1, Fig. 3 of Hwang teaches a display device comprising: a display module including a display panel (Paragraph 0003) and an input sensing unit (Paragraph 0010); and a circuit board connected to the display module, wherein the circuit board includes: a first signal line (Paragraph 0067 Data line or Gate line where the gate and data lines are perpendicular to each other) electrically connected to the display panel and having at least a portion extending in a first extension direction; a sensing line (Item 355) electrically connected to the input sensing unit and having at least a portion extending in a second extension direction crossing the first extension direction; and a shielding layer (Item 343) interposed between the first signal line (Either of data or gate lines) and the sensing line (Item 355) and having a first opening (Fig. 4; One of openings between respective Items 343) and a second opening (Fig. 4; A second of openings between respective Items 343) spaced apart from each other while interposing the sensing line (Item 355) in a plan view, wherein at least a portion of each of the first opening and the second opening extends in the second extension direction, wherein the sensing line crosses the first signal line (Either of the data or gate line) between the first opening and the second opening in the plan view, and wherein a distance between the first opening and the second opening is equal to a width of the sensing line in the plan view (Where the signal line Item 343 separates the first and second opening defined by spacing between respective Items 343).
Regarding claim 10, Fig. 3 of Hwang further teaches where the shielding layer (Item 343) is configured to receive a grounding voltage (Paragraph 0021).
Regarding claim 13, Fig. 3 of Hwang teaches a display device comprising: a display module including a display panel (Paragraph 0003) and an input sensing unit (Paragraph 0010); and a circuit board connected to the display module, wherein the circuit board further includes: a first signal line (Paragraph 0067 Data line or Gate line where the gate and data lines are perpendicular to each other) electrically connected to the display panel; a shielding layer (Item 343) on the first signal line and including a first extension region (One of Item 343) and a second extension region (Another of Item 343) spaced apart from each other, and a peripheral region surrounding the first extension region and the second extension region; and a sensing line (Item 353) on the shielding layer (Item 343), electrically connected to the input sensing unit, and including a first sensing line having a portion overlapped with the first extension region and a second sensing line having a portion overlapped with the second extension region, wherein the first sensing line crosses the first signal line in a region overlapped with the first extension region, and the second sensing line crosses the first signal line in a region overlapped with the second extension region in a plan view, and wherein a width of the first extension region is equal to a width of the first sensing line view (Where the signal line Item 343 separates the first and second opening defined by spacing between respective Items 343, in a region in which the first extension region is overlapped with the first sensing line.
Regarding claim 19, Fig. 3 of Hwang further teaches where the circuit board further includes: a grounding line (Paragraph 0021) spaced apart with the first signal line and extending in parallel to the first signal line.
Regarding claim 20, Fig. 3 of Hwang teaches a display device comprising: a display module configured to provide an image and to sense an external input (Paragraph 0010); and a circuit board connected to the display module, wherein the circuit board includes: a first line (Paragraph 0067 Data line or Gate line where the gate and data lines are perpendicular to each other) electrically connected to the display module to transmit a high frequency signal (Where data and scan signals are sent through the respective data and gate lines at a high frequency) and having at least a portion extending in a first extension direction; a second line (Item 355) electrically connected to the display module, and having at least a portion extending in a second extension direction crossing the first extension direction; and a shielding layer (Item 343) interposed between the first line (Either of data or gate lines) and the second line (Item 355) and having a first opening (Fig. 4; One of openings between respective Items 343) and a second opening (Fig. 4; A second of openings between respective Items 343) spaced apart from each other while interposing the second line (Item 355) in a plan view, wherein at least a portion of each of the first opening and the second opening extends in the second extension direction, wherein the second line crosses the first line (Either of the data or gate line) between the first opening and the second opening in the plan view, and wherein a distance between the first opening and the second opening is equal to a width of the second line in the plan view (Where the signal line Item 343 separates the first and second opening defined by spacing between respective Items 343).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2019/0155417) hereinafter “Lee” in view of Choi et al. (US 2021/0098749) hereinafter “Choi”.
Regarding claim 12, Lee teaches all of the elements of the claimed invention as stated above except a lower insulating interposed between the base layer and the first signal line; and a power line interposed between the base layer and the lower insulating layer.
Fig. 3 of Choi teaches where a power line (Item UPL2) is on a layer (Paragraph 0077) above a substrate and below a data line (Item DL).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have a lower insulating interposed between the base layer and the first signal line; and a power line interposed between the base layer and the lower insulating layer because the lower insulating layer electrically isolates the data line from the power line and the power line provides a voltage to a source of a driving transistor (Choi Paragraph 0088).
Allowable Subject Matter
Claims 4, 6-8, 14-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 4, none of the prior art teaches, suggests or motivates one having ordinary skill in the art to have the circuit board further includes: a grounding line interposed between the first signal line and the second signal line and extending in parallel to the first signal line, and wherein a portion of the grounding line is exposed from the shielding layer through each of the first opening and the second opening in the plan view along with all of the limitations of claims 1 and 3.
Regarding claim 6, none of the prior art teaches, suggests or motivates one having ordinary skill in the art to have the circuit board further includes: a grounding line interposed between the first signal line and the second signal line and extending in parallel to the first signal line, and wherein the grounding line is interposed between the first opening and the third opening, and between the second opening and the fourth opening in the plan view along with the limitations of claims 1 and 5.
Regarding claim 7, none of the prior art teaches, suggest or motivates one having ordinary skill in the art to have the sensing line includes: a first part extending in the second extension direction and a second part extending in a third extension direction crossing each of the first extension direction and the second extension direction, and wherein each of the first opening and the second opening includes: a first opening region extending in the second extension direction and a second opening region extending in the third extension direction from the first opening region along with the limitations in claim 7.
Claim 8 is also indicated as containing allowable subject matter as it includes all of the limitations of claim 7.
Regarding claim 14, none of the prior art teaches, suggests or motivates one having ordinary skill in the art to have the shielding layer further includes: a dummy extension region spaced apart from the first extension region, extending in parallel to the first extension region, and surrounded by the peripheral region, and wherein the dummy extension region is in a non-overlap state with the sensing line and crosses the first signal line in the plan view along with all of the limitations of claim 13.
Regarding claim 15, none of the prior art teaches, suggests or motivates one having ordinary skill in the art to have the shielding layer further includes a third extension region and a fourth extension region surround by the peripheral region, another portion of the first sensing line is overlapped with the third extension region, and another portion of the second sensing line is overlapped with the fourth extension region, along with all of the limitations of claim 13.
Claim 16 is also indicated as containing allowable subject matter as it includes all of the limitations of claim 15.
Regarding claim 17, none of the prior art teaches, suggests or motivates one having ordinary skill in the art to have the first signal line has at least a portion extending in a first extension direction in a region overlapped with the shielding layer, wherein the first sensing line: includes a first part extending in a second extension direction crossing the first extension direction and a second part extending in a third extension direction crossing each of the first extension direction and the second extension direction from the first part, and wherein the first extension region includes: a first region extending in the second extension direction and overlapped with the first part and a second region extending in the third extension direction from the first region and overlapped with the second part, along with the other limitations of claim 13.
Claim 18 is also indicated as containing allowable subject matter as it includes all of the limitations of claim 17.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC K ASHBAHIAN whose telephone number is (571)270-5187. The examiner can normally be reached 8-5:30 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at 571-272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ERIC K ASHBAHIAN/Primary Examiner, Art Unit 2891
Prosecution Insights