DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d) to foreign application TW112102633 filed on 01/19/2023. The foreign application is not in English. The certified copy of the foreign priority application TW112102633 has been received.
Filing Dates for the Claims — All Claims Not Entitled to Priority Date
To be entitled to the filing date of the foreign priority application TW112102633 that is not in English, an English translation of the non-English language foreign application TW112102633 and a statement that the translation is accurate in accordance with 37 CFR 1.55 is required to perfect the claim for priority under 35 U.S.C. 119 (a)-(d). The foreign application must adequately support the claimed subject matter, meaning satisfy the written description and enablement requirements of 35 U.S.C. 112(a). See MPEP §§ 215 and 216. 37 C.F.R. 1.55(g)(3)(ii)-(iii). To demonstrate compliance with 35 U.S.C. 112(a), applicant should point to support for their claimed subject matter in their translations.
Election/Restrictions
Applicant’s election without traverse of invention of Group I directs to a flash memory, claims 1-10 in the reply filed on 06/11/2026 is acknowledged.
Response to Amendment
Applicant’s amendment dated 06/11/2026, in which claims 1, 8-10 were amended, claims 11-20 were withdrawn, has been entered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 10 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 10, claim 10 recites “a masking layer”. It is unclear if “a masking layer” recited in claim 10 is the same or different from “a masking layer” recited in claim 1 on which claim 10 depends.
For the purpose of this Action, the limitation of “a masking layer” recited in claim 10 will be interpreted and examined as --the masking layer--.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 6-7, 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Kashimura et al. (US Pat. 9281314) in view of Fujitsuka et al. (US Pub. 20150060986).
Regarding claim 1, Kashimura et al. discloses in Fig. 8C, Fig. 8E, columns 9-10, a flash memory, comprising:
multiple gate stacks [570] arranged on a substrate [502];
a spacer structure [532 and 534] comprising multiple thin spacers [lower portions of 532] covering sidewalls of lower portions of the gate stacks [570] and multiple thick spacers [534 and upper portions of 532] covering sidewalls of upper portions of the gate stacks [570], wherein the thick spacers [534 and upper portions of 532] are located over the respective thin spacers [lower portions of 532], and the thick spacers [534 and upper portions of 532] are thicker than the thin spacers [lower portions of 532], wherein the thick spacers [534 and upper portions of 532] comprise upper portions of a first spacer layer [532] and second spacer layers [534], the thin spacers [lower portions of 532] comprise lower portions of the first spacer layer [532],;
a dielectric structure [854] disposed on the spacer structure [532 and 534]; and
an air gap [844] sealed by the dielectric structure [854] and the spacer structure [532 and 534], wherein the air gap [844] comprises a body portion between the thin spacers [lower portions of 532] and a head portion between the thick spacers [534 and upper portions of 532], and the body portion is wider than the head portion;
wherein each of the upper portions of the gate stacks [570] comprises a metal layer [528] and a masking layer [530] over the metal layer [528], and the upper portions of the first spacer layer [532] covering sidewalls of both the masking layer [530] and the metal layer [528].
Kashimura et al. fails to disclose
the lower portions of the first spacer layer are thinner than the upper portions of the first spacer layer.
Fujitsuka et al. discloses in Fig. 2
the lower portions [24a, 24b, 24c] of the first spacer layer [24] are thinner than the upper portions [24d] of the first spacer layer [24].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Fujitsuka et al. into the method of Kashimura et al. to include the lower portions of the first spacer layer are thinner than the upper portions of the first spacer layer. The ordinary artisan would have been motivated to modify Kashimura et al. in the above manner for the purpose of widening the width of the air gap and further reducing the parasitic capacitance between the memory cells [paragraph [0047] of Fujitsuka et al.].
Regarding claims 6-7, Kashimura et al. discloses in Fig. 8F, column 6, lines 39-40
wherein the first spacer layer [532] is made of different material than the second spacer layers [534][silicon oxide vs. silicon nitride].
wherein bottom surfaces of the second spacer layers [534] are exposed from the body portion of the air gap [844];
Regarding claims 9-10, Kashimura et al. discloses in Fig. 8D, Fig. 8F column 5, lines 56-67, column 6, lines 1-10
wherein each of the lower portions of the gate stacks comprises a tunnel oxide layer [520/504] over the substrate [502], a first semiconductor layer [522] over the tunnel oxide layer [520/504], an inter-gate dielectric layer [524] over the first semiconductor layer [522], and a second semiconductor layer [526] over the inter-gate dielectric layer [524];
wherein the metal layer [528] is formed over the second semiconductor layer [526] and the masking layer [530] over the metal layer [528].
Claims 2-5, and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Kashimura et al. (US Pat. 9281314) in view of Fujitsuka et al. (US Pub. 20150060986) as applied to claim 1 above and further in view of Ohno et al. (US Pub. 20130043523).
Regarding claim 2, Kashimura et al. fails to disclose
wherein the head portion of the air gap has: a first width at a middle height of the head portion; and a second width at bottoms of the thick spacers, wherein the second width is less than the first width.
Fujitsuka et al. discloses in Fig. 2
wherein the head portion of the air gap [22] has:
a first width at a middle height of the head portion; and
a second width at bottoms of the thick spacers, wherein the second width is less than the first width.
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Ohno et al. discloses in Fig. 5
wherein the head portion of the air gap [19] has:
a first width [W4] at a middle height of the head portion; and
a second width at bottoms of the head portion, wherein the second width is less than the first width [W4].
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It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Fujitsuka et al. and Ohno et al. into the method of Kashimura et al. to include wherein the head portion of the air gap has: a first width at a middle height of the head portion; and a second width at bottoms of the thick spacers, wherein the second width is less than the first width. The ordinary artisan would have been motivated to modify Kashimura et al. in the above manner for the purpose of decreasing the coupling capacitance between adjacent metal gates [paragraph [0042] of Ohno et al.]
Regarding claims 3-4, Kashimura et al. discloses in Fig. 8F
wherein the body portion of the air gap [844] has a third width at tops of the thin spacers [lower portion of 532], and the third width is greater than the first width;
wherein the body portion of the air gap [844] has a fourth width at bottoms of the thin spacers [lower portion of 532], and the fourth width is greater than the first width.
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Regarding claim 5, Kashimura et al. fails to disclose
wherein the head portion of the air gap has a pointed tip, and a width of the head portion of the air gap tapers from a middle height of the head portion upward towards the pointed tip.
Fujitsuka et al. discloses in Fig. 2
wherein the head portion of the air gap [22] has a pointed tip, and a width of the head portion of the air gap [22] tapers from a middle height of the head portion upward towards the pointed tip.
Ohno et al. also discloses in Fig. 5
wherein the head portion of the air gap [19] has a pointed tip, and a width of the head portion of the air gap [19] tapers from a middle height of the head portion upward towards the pointed tip.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Fujitsuka et al. and Ohno et al. into the method of Kashimura et al. to include wherein the head portion of the air gap has a pointed tip, and a width of the head portion of the air gap tapers from a middle height of the head portion upward towards the pointed tip. The ordinary artisan would have been motivated to modify Kashimura et al. in the above manner for the purpose of providing suitable configuration of the head portion of the air gap to decrease the coupling capacitance between adjacent control gates [paragraph [0042] of Ohno et al.]
Regarding claim 8, Kashimura et al. discloses in Fig. 8F column 5, lines 56-67, column 6, lines 1-10,
wherein each of the gate stacks comprises, in sequence stacked over the substrate [502], a tunnel oxide layer [520], a first semiconductor layer [522], an inter-gate dielectric layer [524], a second semiconductor layer [526], a metal layer [528] and a masking layer [550],
Kashimura et al. fails to disclose
a width of a bottom surface of the metal layer is greater than a width of a top surface of the second semiconductor layer.
Ohno et al. discloses in Fig. 2E
a width of a bottom surface of the metal layer [17] is greater than a width of a top surface of the second semiconductor layer [16].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Ohno et al. into the method of Kashimura et al. to include a width of a bottom surface of the metal layer is greater than a width of a top surface of the second semiconductor layer. The ordinary artisan would have been motivated to modify Kashimura et al. in the above manner for the purpose of decreasing the interconnection resistance of the control gate electrode, making the CR coefficient smaller, which prevents a delay in the propagation of a program voltage and a voltage drop and improves the write characteristic and the read characteristic [paragraph [0013] of Ohno et al.].
Response to Arguments
Applicant’s arguments with respect to claims 1-10 have been considered but are moot in view of the new ground of rejection.
As stated above, Kashimura et al. discloses in Fig. 8F
wherein each of the upper portions of the gate stacks [570] comprises a metal layer [528] and a masking layer [530] over the metal layer [528], and the upper portions of the first spacer layer [532] covering sidewalls of both the masking layer [530] and the metal layer [528].
Thus, secondary references Fujitsuka and Ohno are not cited to teach that feature and do not need to disclose that feature. Fujitsuka is cited to teach the lower portions of the first spacer layer are thinner than the upper portions of the first spacer layer. Ohno et al. is cited to teach the head portion of the air gap has: a first width at a middle height of the head portion; and a second width at bottoms of the head portion, wherein the second width is less than the first width; and a width of a bottom surface of the metal layer is greater than a width of a top surface of the second semiconductor layer.
In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Overall, Applicant’s arguments are not persuasive. The claims stand rejected and the Action is made FINAL.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/SOPHIA T NGUYEN/Primary Examiner, Art Unit 2893
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