Prosecution Insights
Last updated: July 17, 2026
Application No. 18/416,079

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES, CORRESPONDING RIBBON, APPARATUS AND DEVICE

Non-Final OA §103
Filed
Jan 18, 2024
Priority
Jan 20, 2023 — IT 102023000000849
Examiner
DINKE, BITEW A
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
STMicroelectronics N.V.
OA Round
1 (Non-Final)
73%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
85%
With Interview

Examiner Intelligence

Grants 73% — above average
73%
Career Allowance Rate
561 granted / 771 resolved
+4.8% vs TC avg
Moderate +12% lift
Without
With
+11.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
43 currently pending
Career history
810
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
91.7%
+51.7% vs TC avg
§102
3.1%
-36.9% vs TC avg
§112
1.6%
-38.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 771 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Group I, with claims 1-7 and 9-12 in the reply filed on 06/10/2026 is acknowledged. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 1-7 and 9- 12 are rejected under 35 U.S.C. 103 as being unpatentable over Torii et al. (JP 2012-146747 A, hereinafter refer to Torii) in view of Shingyoji et al. (U.S. Pat. No.5,936,492, hereinafter refer to Shingyoii). JP 2012146747 A (hereinafter refer to Torii) is relied upon solely for the English language translation of JP 2012-146747 A. Regarding Claim 1: Torii discloses a method (see Torii, Fig.1 as shown below and abstract), comprising: PNG media_image1.png 268 446 media_image1.png Greyscale PNG media_image2.png 283 451 media_image2.png Greyscale arranging a semiconductor die (1) at a die mounting location of a substrate (3), the substrate (3) comprising an array of electrically conductive leads (3a/3b) at a periphery of the substrate (3) (see Torii, Fig.1 as shown above); and electrically coupling the semiconductor die (1) and selected ones of the electrically conductive leads (3a/3b) in the array of electrically conductive leads (3a/3b) via electrically conductive ribbons (7) having a body portion with a first width as well as first and second end portions bonded to the semiconductor die (1) and to electrically conductive leads (3a) in the array of electrically conductive leads (3a), respectively (see Torii, Fig.1 as shown above). Torii is silent upon explicitly disclosing wherein at least one of the first and second end portions of the electrically conductive ribbons comprises a tapered portion having a second width smaller than the first width of the body portion. For support see Shingyoii, which teaches wherein at least one of the first and second end portions of the electrically conductive ribbons (11e) comprises a tapered portion having a second width smaller than the first width of the body portion (see Shingyoii, Fig.4C and 5B as shown below, col.2, lines 63-67, and col.3, lines 1-13). PNG media_image3.png 284 392 media_image3.png Greyscale PNG media_image4.png 179 419 media_image4.png Greyscale PNG media_image5.png 274 389 media_image5.png Greyscale PNG media_image6.png 197 592 media_image6.png Greyscale PNG media_image7.png 171 608 media_image7.png Greyscale Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Torii and Shingyoii to enable the Torii’s first and second end portions of the electrically conductive ribbons to comprises a tapered portion having a second width smaller than the first width of the body portion as taught by Shingyoii in order to reduced production costs . Regarding Claim 2: Torii as modified teaches a method as set forth in claim 1 as above. The combination of Torii and Shingyoii further teaches wherein the electrically conductive ribbons (7) have a substantially constant thickness at the first and second end portions and at the body portion (see Torii, Fig.1 as shown above). Regarding Claim 3: Torii as modified teaches a method as set forth in claim 1 as above. The combination of Torii and Shingyoii further teaches wherein dispensing electrically conductive material at the tapered portion having a second width smaller than the first width of the body portion to provide a current conduction path of substantially constant cross- sectional area extending between the first and second end portions (see Shingyoii, Fig.4C and 5B as shown above). Regarding Claim 4: Torii as modified teaches a method as set forth in claim 1 as above. The combination of Torii and Shingyoii further teaches wherein wedge-bonding the first and second end portions to the semiconductor die (1) and to electrically conductive leads (3a) in the array of electrically conductive leads (3a) (see Torii, Fig.1 as shown above). Regarding Claim 5: Torii as modified teaches a method as set forth in claim 1 as above. The combination of Torii and Shingyoii further teaches wherein electrically coupling (11e) comprises: providing a metal strip having the first width at body portions and including a plurality of tapered portions each having the second width smaller than the first width (see Shingyoii, Fig.4C and 5B as shown above); forming the ribbon (7) by (see Shingyoii, Fig.4C and 5B as shown above): bonding one of the tapered portions of the metal strip (11e) to one of the semiconductor die (11) or electrically conductive leads (17b/17z) in the array of electrically conductive leads (Fig.1. 3a) to provide the first end portion of the ribbon (7) (see Shingyoii, Fig.4C and 5B as shown above and see Torii, Fig.1 as shown above); bonding another one of the tapered portions of the metal strip (11e) to the other of the semiconductor die (11) or electrically conductive leads (17b/17z) in the array of electrically conductive leads (Fig.1, 3a) (see Shingyoii, Fig.4C and 5B as shown above and see Torii, Fig.1 as shown above); and cutting the another one of the tapered portions to provide the second end portion of the ribbon (11e) (see Shingyoii, Fig.4C and 5B as shown above). Regarding Claim 6: Torii discloses an electrically conductive ribbon (7) (see Torii, Fig.1 as shown above and abstract), comprising: a body portion having a first width as well as first and second end portions configured to be bonded to a semiconductor die (1) and to electrically conductive leads (3a) in an array of electrically conductive leads (3a/3b), respectively (see Torii, Fig.1 as shown above). Torii is silent upon explicitly disclosing wherein at least one of the first and second end portions of the electrically conductive ribbon comprises a tapered portion having a second width smaller than the first width of the body portion. For support see Shingyoii, which teaches wherein at least one of the first and second end portions of the electrically conductive ribbon (11e) comprises a tapered portion having a second width smaller than the first width of the body portion (see Shingyoii, Fig.4C and 5B as shown above, col.2, lines 63-67, and col.3, lines 1-13). Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Torii and Shingyoii to enable the Torii’s at least one of the first and second end portions of the electrically conductive ribbon to comprise a tapered portion having a second width smaller than the first width of the body portion as taught by Shingyoii in order to reduced production costs . Regarding Claim 7: Torii as modified teaches an electrically conductive ribbon (7) as set forth in claim 6 as above. The combination of Torii and Shingyoii further teaches wherein the ribbon (7) has a substantially constant thickness at the first and second end portions and at the body portion (see Torii, Fig.1 as shown above). Regarding Claim 9: Torii discloses a device (see Torii, Fig.1 as shown above and abstract), comprising: a semiconductor die (1) arranged at a die mounting location of a substrate (3), the substrate (3) comprising an array of electrically conductive leads (3a/3b) at a periphery of the substrate (3) (see Torii, Fig.1 as shown above); and electrically conductive ribbons (7) electrically coupling the semiconductor die (1) and selected ones of the electrically conductive leads (3a) in the array of electrically conductive leads (3a/3b), the electrically conductive ribbons (7) having a body portion with a first width as well as first and second end portions bonded to the semiconductor die (1) and to electrically conductive leads (3a) in the array of electrically conductive leads (3a/3b), respectively (see Torii, Fig.1 as shown above). Torii is silent upon explicitly disclosing wherein at least one of the first and second end portions of the electrically conductive ribbons comprises a tapered portion having a second width smaller than the first width of the body portion. For support see Shingyoii, which teaches wherein at least one of the first and second end portions of the electrically conductive ribbons (11e) comprises a tapered portion having a second width smaller than the first width of the body portion (see Shingyoii, Fig.4C and 5B as shown above, col.2, lines 63-67, and col.3, lines 1-13). Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Torii and Shingyoii to enable the Torii’s at least one of the first and second end portions of the electrically conductive ribbons to comprise a tapered portion having a second width smaller than the first width of the body portion as taught by Shingyoii in order to reduced production costs . Regarding Claim 10: Torii as modified teaches a device as set forth in claim 9 as above. The combination of Torii and Shingyoii further teaches wherein the electrically conductive ribbons (7) have a substantially constant thickness at the first and second end portions and at the body portion (see Torii, Fig.1 as shown above). Regarding Claim 11: Torii as modified teaches a device as set forth in claim 9 as above. The combination of Torii and Shingyoii further teaches wherein the electrically conductive ribbons (7) are wedge-bonded at the first and second end portions to the semiconductor die (1) and to electrically conductive leads (3a) in the array of electrically conductive leads (3a/3b) (see Torii, Fig.1 as shown above). Regarding Claim 12: Torii as modified teaches a device as set forth in claim 9 as above. The combination of Torii and Shingyoii further teaches wherein electrically conductive material (11e) dispensed at the tapered portion having a second width smaller than the first width of the body portion to provide a current conduction path of substantially constant cross- sectional area extending between the first and second end portions (see Shingyoii, Fig.4C and 5B as shown above). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to BITEW A DINKE whose telephone number is (571)272-0534. The examiner can normally be reached M-F 7 a.m. - 5 p.m.. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at (571)272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /BITEW A DINKE/Primary Examiner, Art Unit 2812
Read full office action

Prosecution Timeline

Jan 18, 2024
Application Filed
Jun 26, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12677410
SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME
3y 5m to grant Granted Jul 07, 2026
Patent 12677485
DIELECTRIC LAYER RESPONSE-BASED FIELD EFFECT TRANSISTOR PHOTODETECTOR
3y 0m to grant Granted Jul 07, 2026
Patent 12666686
SEMICONDUCTOR STRUCTURE WITH FLUSH SHALLOW TRENCH ISOLATION AND GATE OXIDE AND METHOD OF MANUFACTURING THE SAME
3y 0m to grant Granted Jun 23, 2026
Patent 12666843
DISPLAY APPARATUS, DISPLAY MODULE, ELECTRONIC DEVICE, AND METHOD FOR MANUFACTURING DISPLAY APPARATUS
2y 11m to grant Granted Jun 23, 2026
Patent 12652880
OPTICAL DEVICE
3y 2m to grant Granted Jun 09, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
73%
Grant Probability
85%
With Interview (+11.9%)
2y 3m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 771 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month