Prosecution Insights
Last updated: July 17, 2026
Application No. 18/416,530

DISPLAY DEVICE

Non-Final OA §103
Filed
Jan 18, 2024
Priority
Jan 30, 2023 — RE 10-2023-0011840
Examiner
PRASAD, NEIL R
Art Unit
2897
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
LG Display Co., Ltd.
OA Round
1 (Non-Final)
85%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
95%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allowance Rate
607 granted / 711 resolved
+17.4% vs TC avg
Moderate +10% lift
Without
With
+9.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 2m
Avg Prosecution
20 currently pending
Career history
731
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
82.5%
+42.5% vs TC avg
§102
10.3%
-29.7% vs TC avg
§112
0.4%
-39.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 711 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement The information disclosure statement (IDS) submitted on 1/18/2024 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-17 are rejected under 35 U.S.C. 103 as being unpatentable over Guo et al. (US Publication No. 2019/0172761) in view of You et al. (US Publication No. 2023/0354658). Regarding claim 1, A display device, comprising: a plurality of sub-pixels including at least one emission sub-pixel (110X’) and a repair sub-pixel (120’) disposed on a substrate a light emitting element disposed in the at least one emission sub-pixel (190) a transistor (DR) disposed in the emission sub-pixel (190) a first reflective layer (DE right) disposed between the light emitting element and the transistor in the at least one emission sub-pixel, and electrically connected to the transistor a second reflective layer (DE left) disposed in the repair sub-pixel (120’) Guo does not clearly disclose a connection layer disposed below the first reflective layer and the second reflective layer to overlap the first reflective layer and the second reflective layer. However, You discloses a connection layer (CE/RL) below a first reflective layer (E1a) and a second reflective layer (E1b) (Figures 8-9). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have a connection layer between two reflective layers, as taught by You, to maintain the same brightness per unit area (paragraph 97). Regarding claim 2, You discloses the light emitting element (LDa) is electrically connected (Ha) to the transistor (GE) through the first reflective layer (E1a). Regarding claim 3, You discloses at least one emission sub-pixel includes a first sub-pixel, a second sub-pixel, and a third sub-pixel configured to emit light of different colors (paragraph 79). Regarding claim 4, You discloses the repair sub-pixel (LDb) includes a fourth sub-pixel configured as a non-emission sub-pixel (each pixel has a 4th, 5th, and 6th repair pixel configured as non-emissive until needed to replace a defective pixel, Figure 8). Regarding claim 5, You discloses the connection layer (CE) extends between the first to fourth sub-pixels, and overlaps the first reflective layer (E1a) disposed in each of the first to third sub-pixels and overlaps the second reflective layer (E1b) disposed in the fourth sub-pixel. Regarding claim 6, You discloses the transistor (GE) is not disposed in the repair sub-pixel (LDb) (Figure 9). Regarding claim 7, You discloses the connection layer (CE) is electrically connected to the second reflective layer (E1b). Regarding claim 8, You discloses the at least one emission sub-pixel is detected to emit light properly, and the connection layer (CE) is insulated (VIA) from the first reflective layer (E1a) (paragraphs 102-104). Regarding claim 9, You discloses a bank (PDL) disposed on the plurality of sub-pixels, and having an open area (top) overlapping with the light emitting element (LD), wherein the bank covers an entirety (from the side) of the repair sub-pixel (LDb). Regarding claim 10, You discloses the connection layer and the second reflective layer are electrically floating (paragraph 102). Regarding claim 11, You discloses when one of the at least one emission sub- pixel is detected as a defective sub-pixel that does not emit light properly, a repair light emitting element, that emits light of a same color as the light emitting element disposed in the defective sub-pixel, is disposed in the repair sub-pixel (paragraphs 102-104). Regarding claim 12, You discloses the connection layer (CE) is electrically connected to the first reflective layer (E1a) disposed in the defective sub-pixel (LDa) (paragraph 94). Regarding claim 13, You discloses the repair light emitting element (LDb) is electrically connected to the transistor (GE) disposed in the defective sub-pixel (LDa) through the second reflective layer (E1b), the connection layer (CE) and the first reflective layer (E1a) (Figure 10). Regarding claim 14, You discloses a common electrode (E2) connected to the light emitting element disposed in the defective sub-pixel (LDa) and the repair light emitting element disposed in the repair sub-pixel (LDb). Regarding claim 15, You discloses an intermediate line (OPa/b) disposed below the common electrode (E2) and connected to the common electrode (CE); and a low potential power supply line (data line) disposed below the intermediate line and connected to the intermediate line (Figure 6). Regarding claim 16, You discloses a bank (PDL) disposed on the plurality of sub-pixels and having open areas overlapping with the light emitting element (LDa) and the repair light emitting element (LDb). Regarding claim 17, You discloses the connection layer (CE) is disposed on a same layer as an electrode (SE) included in the transistor (GE). Claims 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Guo et al. (US Publication No. 2019/0172761) in view of You et al. (US Publication No. 2023/0354658), and further in view of Cha et al. (US Publication No. 2017/0162746). Regarding claim 18, Guo/You discloses the limitations as discussed in the rejection of claim 1 above. Guo/You does not disclose a bonding layer disposed between the first reflective layer and the light emitting element. However, Cha discloses a bonding layer (UBM) between the reflective layer (242) and light emitting element (100_R) (paragraphs 64 and 102). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the connection between the reflective layer and light emitting element of Guo/You to include the bonding layer, as taught by Cha, since it can improve adhesion and therefore light extraction efficiency (paragraph 61). Regarding claim 19, Cha discloses the bonding layer comprises a eutectic metal (paragraph 102). Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Choi et al. (US Publication No. 2022/0320055) discloses the use of repair pixels (Figure 4; paragraphs 151-152). Wu et al. (US Publication No. 2021/0183309) discloses repairing light emitting die regions (paragraphs 22-23). Any inquiry concerning this communication or earlier communications from the examiner should be directed to NEIL R PRASAD whose telephone number is (571) 270-3129. The examiner can normally be reached M-F 9am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at (469) 295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /N.R.P/ 5/25/2026 Examiner, Art Unit 2897 /JACOB Y CHOI/ Supervisory Patent Examiner, Art Unit 2897
Read full office action

Prosecution Timeline

Jan 18, 2024
Application Filed
Jun 04, 2026
Non-Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
85%
Grant Probability
95%
With Interview (+9.5%)
2y 2m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 711 resolved cases by this examiner. Grant probability derived from career allowance rate.

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