CTNF 18/416,608 CTNF 87887 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Response to Amendment Applicant's amendment to the claims, filed on April 6 th , 2026, is acknowledged. Entry of amendment is accepted and made of record. Election/Restrictions 08-25-01 AIA Applicant's election without traverse of Species I directed to Figs. 2A-2B (Claims 1-20) in the reply filed on April 6 th , 2026 is acknowledged. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15 AIA Claim s 1-2 and 4-6 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Kim et al. (Pub. No.: US 2019/0157245 A1), hereinafter as Kim245 . Regarding claim 1 , Kim245 discloses a semiconductor package in Figs. 1-3 and 4A-4B comprising: a first semiconductor chip (chip CH1) comprising: a first semiconductor layer (substrate 100) comprising a surface (surface 100a) which extends in a first direction (lateral direction in Fig. 2) (see Fig. 2 and [0046]); and a first connection pad (pad 150) provided on the surface of the first semiconductor layer (see Fig. 2 and [0048]); and a second semiconductor chip (chip CH2) comprising: a second semiconductor layer (substrate 200); and a second connection pad (pad 250) provided on a surface of the second semiconductor layer (surface 200a), wherein the first connection pad is directly connected to the second connection pad (see Fig. 2), wherein the first connection pad is provided on the second connection pad in a second direction (vertical direction in up-side down view of Fig. 2) perpendicular to the first direction, and wherein a ratio of a width of the first connection pad (W1 of pad 150) in the first direction to a width of the second connection pad (length L2 of pad 250) in the first direction is less than or equal to 1.1 and greater than or equal to 0.5 (W1 = W2, so W1/L2 = W2/L2 which is ½ or 0.5 because L2/W2 = 2) (see Figs. 3, 4A-4B and [0061]). Regarding claim 2 , Kim245 discloses the semiconductor package of claim 1, wherein the first semiconductor chip comprises a first insulating layer (insulating layers 110a-110d, insulating layer 140 and insulating layer 160) provided on the surface of the first semiconductor layer and surrounding a side surface of the first connection pad (see Fig. 2 and [0046], [0048-0049]), wherein the second semiconductor chip comprises a second insulating layer (insulating layers 210a-210d, insulating layer 240 and insulating layer 260) provided on the surface of the second semiconductor layer and surrounding a side surface of the second connection pad (see Fig. [0054-0055]), and wherein the first insulating layer comprises a first insulating material (silicon oxide of insulating layers 110a-110d and 140) and the second insulating layer comprises a second insulating material (SiCOH of insulating layer 240 or SiCN of insulating layer 260) that is different than the first insulating material (see [0054-0055]). Regarding claim 4 , Kim245 discloses the semiconductor package of claim 2, wherein the first insulating layer is directly connected to the second insulating layer, and wherein the first insulating layer is provided on the second insulating layer in the second direction (up-side down view of Fig. 2). Regarding claim 5 , Kim245 discloses the semiconductor package of claim 2, wherein the first semiconductor chip comprises a wiring structure (plurality of metal lines 120 and vias V1) provided between the surface of the first semiconductor layer and the first insulating layer (see Fig. 2 and [0048]), wherein the wiring structure is provided between the surface of the first semiconductor layer and the first connection pad (see Fig. 2), wherein the wiring structure comprises a wiring pad (uppermost metal line 120) electrically connected to the first connection pad, and wherein the first insulating layer comprises a surface (bottom surface of insulating layer 110a) in direct contact with the surface of the first semiconductor layer (see Fig. 2). Regarding claim 6 , Kim245 discloses the semiconductor package of claim 1, wherein the first connection pad and the second connection pad comprise a same metal material (see [0048] and [0062], [0065]) . 07-15-03-aia AIA Claim s 1, 7-10 and 12-15 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kim (Pub. No.: US 2022/0037289 A1), hereinafter as Kim289 . Regarding claim 1 , Kim289 discloses a semiconductor package in Figs. 1-2 comprising: a first semiconductor chip (chip 200) comprising: a first semiconductor layer (substrate 210) comprising a surface (surface 210L) which extends in a first direction (direction D1) (see Fig. 1 and [0033]); and a first connection pad (second connection portion CP2) provided on the surface of the first semiconductor layer (see Figs. 1-2 and [0037]); and a second semiconductor chip (chip 100) comprising: a second semiconductor layer (substrate 110) (see Fig. 1 and [0026]); and a second connection pad (first connection portion CP1) provided on a surface of the second semiconductor layer (surface 100a), wherein the first connection pad is directly connected to the second connection pad, wherein the first connection pad is provided on the second connection pad in a second direction (direction D2) perpendicular to the first direction (see Figs. 1-2 and [0037-0038]), and wherein a ratio of a width of the first connection pad (width W2) in the first direction to a thickness of the second connection pad (width W1) in the second direction is greater than or equal to 1.1 and less than or equal to 0.5 (ratio W2/W1 = 3um/3um = 1) (see Fig. 2 and [0037]). Regarding claim 7 , Kim289 discloses the semiconductor package of claim 1, wherein a thickness of the first connection pad (thickness T2) in the second direction is greater than a thickness of the second connection pad (thickness T1) in the second direction (see Fig. 2 and [0039]). Regarding claim 8 , Kim289 discloses the semiconductor package of claim 1, wherein a ratio of a thickness of the first connection pad (thickness T2) in the second direction to a thickness of the second connection pad (thickness T1) in the second direction is greater than or equal to 1.6 and less than or equal to 2.1 (ratio T2/T1 = 3um/1.5um = 2) (see Fig. 2 and [0039]). Regarding claim 9 , Kim289 discloses a semiconductor package in Figs. 1-2 comprising: a first semiconductor chip (chip 200) comprising: a first semiconductor layer (substrate 210) comprising a surface (surface 210L) which extends in a first direction (direction D1) (see Fig. 1 and [0033]); and a first connection pad (second connection portion CP2) provided on the surface of the first semiconductor layer (see Figs. 1-2 and [0037]); and a second semiconductor chip (chip 100) comprising: a second semiconductor layer (substrate 110) (see Fig. 1 and [0026]); and a second connection pad (first connection portion CP1) provided on a surface of the second semiconductor layer (surface 100a), wherein the first connection pad is directly connected to the second connection pad, wherein the first connection pad is provided on the second connection pad in a second direction (direction D2) perpendicular to the first direction (see Figs. 1-2 and [0037-0038]), and wherein a ratio of a thickness of the first connection pad (thickness T2) in the second direction to a thickness of the second connection pad (thickness T1) in the second direction is greater than or equal to 1.6 and less than or equal to 2.1 (ratio T2/T1 = 3um/1.5um = 2) (see Fig. 2 and [0039]). Regarding claim 10 , Kim289 discloses the semiconductor package of claim 9, wherein the first semiconductor chip comprises a first insulating layer (combination of layer 226 and IL2) provided on the surface of the first semiconductor layer and surrounding a side surface of the first connection pad (see Fig. 1 and [0025], [0034]), wherein the second semiconductor chip comprises a second insulating layer (layer IL1) provided on the surface of the second semiconductor layer and surrounding a side surface of the second connection pad (see Fig. 1 and [0025]), and wherein the first insulating layer comprises a first insulating material (silicon oxide of layer 226) and the second insulating layer comprises a second insulating material (SiCN of layer IL1) that is different than the first insulating material (see [0034] and [0042]). Regarding claim 12 , Kim289 discloses the semiconductor package of claim 10, wherein the first insulating layer is directly connected to the second insulating layer, and wherein the first insulating layer is provided on the second insulating layer in the second direction (see Fig. 1). Regarding claim 13 , Kim289 discloses the semiconductor package of claim 10, wherein the first semiconductor chip comprises a wiring structure (combination of layers 222 and 224) provided between the surface of the first semiconductor layer and the first insulating layer (see Fig. 1 and [0034]), wherein the wiring structure is provided between the surface of the first semiconductor layer and the first connection pad (see Fig. 2), wherein the wiring structure comprises a wiring pad (lower layer 224) electrically connected to the first connection pad, and wherein the first insulating layer comprises a surface (top surface of layer 226) in direct contact with the surface of the first semiconductor layer (see Fig. 1). Regarding claim 14 , Kim289 discloses the semiconductor package of claim 9, wherein the first connection pad and the second connection pad comprise a same metal material (see Fig. 2 and [0037]). Regarding claim 15 , Kim289 discloses the semiconductor package of claim 9, wherein a width of the first connection pad (width W2) in the first direction is greater than a width of the second connection pad (width W1) in the first direction (see Fig. 2) . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries set forth in Graham v. John Deere Co. , 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: a. Determining the scope and contents of the prior art. b. Ascertaining the differences between the prior art and the claims at issue. c. Resolving the level of ordinary skill in the pertinent art. d. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-21-aia AIA Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (Pub. No.: US 2019/0157245 A1), hereinafter as Kim245, as applied to claim 2 above, and in view of Hong et al. (Pub. No.: US 2021/0104482), hereinafter as Hong . Regarding claim 3 , Kim245 discloses the semiconductor package of claim 2, wherein the first insulating layer comprises silicon oxide (silicon oxide of insulating layer 140) (see [0048]), but fails to disclose wherein the second insulating layer comprises tetraethyl orthosilicate (TEOS) Hong discloses a semiconductor package comprising a first insulating layer (layer 120-2) and a second insulating layer (layer 120-1) comprising tetraethyl orthosilicate (TEOS) (see Fig.1 and [0025], [0029]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the second insulating layer of Kim245 to be made from TEOS same material as the second insulating layer of Hong because the disclosure of Hong teaching that TEOS and SiCN are equivalent materials to form excellent insulating layer for semiconductor package and choosing TEOS is just merely manufacturing choice . 07-21-aia AIA Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Kim (Pub. No.: US 2022/0037289 A1), hereinafter as Kim289, as applied to claim 10 above, and in view of Hong et al. (Pub. No.: US 2021/0104482), hereinafter as Hong . Regarding claim 11 , Kim289 discloses the semiconductor package of claim 10, wherein the first insulating layer comprises silicon oxide (silicon oxide of layer 226), but fails to disclose wherein the second insulating layer comprises tetraethyl orthosilicate (TEOS) Hong discloses a semiconductor package comprising a first insulating layer (layer 120-2) and a second insulating layer (layer 120-1) comprising tetraethyl orthosilicate (TEOS) (see Fig.1 and [0025], [0029]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the second insulating layer of Kim289 to be made from TEOS same material as the second insulating layer of Hong because the disclosure of Hong teaching that TEOS and SiCN are equivalent materials to form excellent insulating layer for semiconductor package and choosing TEOS is just merely manufacturing choice. Allowable Subject Matter Claims 16-20 are allowed over prior art of record. The following is an examiner' s statement of reason for allowance: the prior art made of record does not teach or fairly suggest the following: an interposer, a logic die provided on the interposer, and a high bandwidth memory provided on the interposer, wherein the high bandwidth memory comprises: a buffer die and the first semiconductor chip provided on the buffer die and the second semiconductor chip as recited in claim 16. Claims 17-20 depend on claim 16, and therefore also include said claimed limitation. 13-03 Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to CUONG B NGUYEN whose telephone number is (571)270-1509 (Email: CuongB.Nguyen@uspto.gov) . The examiner can normally be reached Monday-Friday, 8:30 AM-5:00 PM Eastern Standard Time. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven H. Loke can be reached on (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CUONG B NGUYEN/Primary Examiner, Art Unit 2818 Application/Control Number: 18/416,608 Page 2 Art Unit: 2818 Application/Control Number: 18/416,608 Page 3 Art Unit: 2818 Application/Control Number: 18/416,608 Page 4 Art Unit: 2818 Application/Control Number: 18/416,608 Page 5 Art Unit: 2818 Application/Control Number: 18/416,608 Page 6 Art Unit: 2818 Application/Control Number: 18/416,608 Page 7 Art Unit: 2818 Application/Control Number: 18/416,608 Page 8 Art Unit: 2818 Application/Control Number: 18/416,608 Page 9 Art Unit: 2818 Application/Control Number: 18/416,608 Page 10 Art Unit: 2818 Application/Control Number: 18/416,608 Page 11 Art Unit: 2818
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