Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to the Application filed December 11, 2025.
Status of claims to be treated in this office action:
a. Independent: 1, 10, and 16
b. Pending: 1 and 3-20
Claims 1 and 10 have been amended, claim 2 has been canceled, and claims 19 and 20 are new.
The position taken in the office action mailed on September 15, 2025 is hereby maintained for the revised rationale set forth below. Previously presented 102 and 103 rejections are further reinforced in view of the newly cited references Micheloni et al. (US Pub. 20040170061 A1; “Micheloni”), Ju (US Pub. 20070242552 A1), Lee (US Pub. 20190019558 A1), Yun et al. (US Pub. 20150287710 A1; “Yun”), and Esseni et al. (US Pub. 20020033499 A1; “Esseni”). Rejections based on the newly cited references follow.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Memory device with block-level source lines and pass-transistor control.
Claim Objections
Claims 10, 19, and 20 are objected to because of the following informalities:
Regarding claim 10, the first and second limitation contain “a -connection”. The hyphen should be removed.
Regarding claims 19 and 20, make the following change:
“and each of the memory strings includes”
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 1 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding the last three limitations of claim 1 on page 3, submitted December 11, 2025, the meanings of “source voltage supplied through the…local source line” and “supplying the first and second source voltages to the global source line” are unclear. Para. [0007] mentions a source voltage supplied “to the global source line”, and both paras. [0037] mention a source voltage “supplied to the local source line”. Thus, it is unclear where the source voltages are supplied to, and what “supplied to” means. Using the broadest reasonable interpretation in combination with Fig. 2, the Examiner will interpret the claim limitation as meaning the voltage generation circuit generates source voltages that are applied to the global source line, which is connected to two local source lines via pass gate transistors.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 10 and 14-15 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Micheloni (US Pub. 20040170061 A1).
Regarding independent claim 10, Micheloni discloses a semiconductor device (Fig. 1: electrically programmable, non-volatile semiconductor memory; [0037]) comprising:
a first source pass transistor (source line selector 105a1; [0041]) controlling a -connection between a first global source line (common source line SL1; [0041]) and a first local source line (independent source line Sla; [0041]);
a second source pass transistor (105q2. Examiner notes that Fig. 1 contains two transistors labeled 105q2; this mapping refers to the transistor below RSLq2) controlling a -connection between a second global source line (SL2) and a second local source line (SLq); and
a memory block ([0038]: plurality of memory sectors) including a first sub-memory block (memory sector 103a) using a first source voltage supplied through the first local source line (Sla) and a second sub-memory block (103q) using a second source voltage supplied through the second local source line (Slq; source voltages are described per [0041]: The source line selectors 105a1, 105a2, . . . , 105q1, 105q2…allow selectively connecting the source lines SLa, . . . , SLq of the memory sectors to a first common source line SL1, connected to a reference voltage GND (ground), or to a second common source line SL2, connected to an output of a charge pump generating an erase source voltage Ves, for example a relatively high positive voltage).
Regarding claim 14, Micheloni discloses the limitations of claim 10, and further through Micheloni:
wherein during an erase operation, the first sub-memory block (103a) of the memory block is selected, and an erase voltage (erase source voltage Ves; [0041]) is applied to the first local source line (Sla) as the first source voltage ([0041]: when a given memory sector is accessed in erase, the respective sector source line is connected to the common source line SL2, and thus to the erase source voltage).
Regarding claim 15, Micheloni discloses the limitations of claim 14, and further through Micheloni:
wherein a ground voltage (reference voltage GND (ground); [0041]) is applied to the second local source line (Slq) as the second source voltage ([0041]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-5, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Ju (US Pub. 20070242552 A1) in view of Lee (US Pub. 20190019558 A1).
Regarding independent claim 1, Ju discloses a semiconductor device (Fig. 2: flash memory device 100; [0021]) comprising:
a first source pass transistor (Fig. 3: NMOIS transistor GS1; [0036]) controlling a connection between a global source line (global source select line GSSL; [0028]) and a first local source line (source select line SSL; [0034]);
a second source pass transistor controlling a connection between the global source line and a second local source line (Fig. 3 illustrates memory blocks MF1 to MFK, and memory block MFK. Per [0033]: the memory blocks MF1 to MFK have substantially the same construction and operation. Thus, MFK includes a second NMOIS transistor that controls the connection between GSSL and a second source select line);
a first memory block (MF1)
a second memory block (MFK)
a voltage generation circuit (Fig. 2: high-voltage generator 107; [0021])
Ju does not explicitly disclose:
a first memory block using a first source voltage supplied through the first local source line; and
a second memory block using a second source voltage supplied through the second local source line; and
a voltage generation circuit generating the first and second source voltages and supplying the first and second source voltages to the global source line.
However, Lee teaches:
a first memory block (Fig. 12: memory block BLK1; [0051]) using a first source voltage (source line SL1; [0057]; [0068]: first and second source lines SL1 and SL2 may be coupled to different voltage sources; [0083]: voltages generated from different voltage sources may be applied to the respective first to eighth source. Examiner concludes that the different source lines may carry a different source voltage) supplied through the first local source line (local line LL1); and
a second memory block (BLK2; [0053]) using a second source voltage (SL3; [0063]; [0086]) supplied through the second local source line (LL1; see Fig. 12: there are multiple local lines LL1, and one transmits SL1 and another transmits SL3); and
a voltage generation circuit (Fig. 2: voltage generation circuit 210; [0040]) generating the first and second source voltages and supplying the first and second source voltages to the global source line ([0040]: the voltage generation circuit 210…may…transmit the generated voltages to the row decoder 220 through global lines GL. Also, the voltage generation circuit 210 may generate source line voltages Vsl having various levels, which are to be applied to source lines SL, and transmit the generated source line voltages Vsl to the source decoder 230. Examiner asserts that Lee teaches both that the voltage generation circuit generates and supplies voltages from the global line GL to the local source lines and the block, and also supplies voltages from the local source lines SL1 and SL3 to the global line GL).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Lee to Ju wherein a semiconductor device comprises: a first memory block using a first source voltage supplied through the first local source line; and a second memory block using a second source voltage supplied through the second local source line; and a voltage generation circuit generating the first and second source voltages and supplying the first and second source voltages to the global source line in order to decrease the resistance of the vertical channel layers and decrease the size of the memory device (Lee, [0073] & [0079]).
Regarding claim 3, Ju and Lee together disclose the limitations of claim 1, and further through Ju:
wherein the first memory block (Fig. 3: MF1) includes a drain select line (drain select line DSL; [0034]), and
the semiconductor device (Fig. 2: 100) further comprises:
a global drain select line (Fig. 3: global drain select line GDSL; [0028]); and
a drain select pass transistor (NMOIS transistor GD1; [0036]) controlling a connection between the global drain select line and the drain select line (see Fig. 3).
Regarding claim 4, Ju and Lee together disclose the limitations of claim 1, and further through Ju:
wherein the first memory block (Fig. 3: MF1) includes word lines (local word lines WL1 to WLJ; [0034]), and
the semiconductor device (Fig. 2: 100) further comprises:
global word lines (Fig. 3: global word lines GWL1 to GWLJ; [0028]); and
word line pass transistors (NMOIS transistors G1 to GJ) controlling a connection between the global word lines and the word lines (see Fig. 3).
Regarding claim 5, Ju and Lee together disclose the limitations of claim 1. Ju discloses a first memory block and a semiconductor device, but does not disclose a source select line or global source select line different from a global source line and a local source line.
However, Lee teaches:
wherein the first memory block (Fig. 12: BLK1) includes a source select line (Fig. 6: source select line SSL; [0057]), and
a global source select line (global lines GL may include ); and
a source select pass transistor controlling a connection between the global source select line and the source select line ([0079]: the first global switch circuit GSW1 may include pass switches respectively corresponding to source select lines, word lines, and drain select lines, which are included in each memory block; [0080]: The first local switch circuit LSW1 may transmit voltages applied through the sub-global lines SGL to local lines LL1 to LLj coupled to the first memory block BLK1…The first local switch circuit LSW1 may include pass switches respectively corresponding to source select lines… which are included in each memory block).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Lee to modified Ju wherein the first memory block includes a source select line, a global source select line; and a source select pass transistor controlling a connection between the global source select line and the source select line in order to decrease the resistance of the vertical channel layers and decrease the size of the memory device (Lee, [0073] & [0079]).
Regarding claim 19, Ju and Lee together disclose the limitations of claim 1. Ju does not disclose:
wherein the first memory block includes memory strings, and each of the memory string includes at least one drain select transistor, a plurality of memory cells and at least one source select transistor.
However, Lee teaches:
wherein the first memory block (Fig. 6 shows a portion of a memory block) includes memory strings (Fig. 6: strings ST; [0057]), and each of the memory string includes at least one drain select transistor (Fig. 7: drain select transistor DST; [0059]: The strings ST may include source select transistors SST, memory cells C1 to Cn (n is a positive integer), and drain select transistors DST), a plurality of memory cells ([0057]: Memory cells may be formed between the word lines WL and the vertical channel layers CH) and at least one source select transistor (Fig. 7: source select transistor SST; [0059]).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Lee to modified Ju wherein the first memory block includes a source select line, a global source select line; and a source select pass transistor controlling a connection between the global source select line and the source select line in order to decrease the resistance of the vertical channel layers and decrease the size of the memory device (Lee, [0073] & [0079]).
Claims 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Ju (US Pub. 20070242552 A1) and Lee (US Pub. 20190019558 A1) as applied to claim 1 above, and further in view of Watanabe (US Pub. 20030072176 A1).
Regarding claim 8, Ju and Lee together disclose the limitations of claim 1. Neither Ju nor Lee disclose:
wherein during a program operation, the first memory block is selected, and a first operation voltage is applied to the first local source line as the first source voltage.
However, Watanabe teaches:
wherein during a program operation, the first memory block is selected, and a first operation voltage is applied to the first local source line as the first source voltage ([0027]: In the example in FIG. 3, the sector selection switch SW33 connects the local source line LSL of the sector SCT3 in the bank BNK3 to the global source line GSL…during the programming, the source line voltage generator 12 applies, to the local source line LSL of the sector SCT3, the source line voltage which is optimized in accordance with the location of the sector SCT3. See Fig. 3: sector SCT3 is selected and is analogous to a first memory block).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Watanabe to modified Ju wherein during a program operation, the first memory block is selected, and a first operation voltage is applied to the first local source line as the first source voltage in order to optimize programming by optimizing the drain-source voltage of selected cells (Watanabe, [0015]).
Regarding claim 9, Ju, Lee, and Watanabe together disclose the limitations of claim 8, and further through Watanabe:
wherein a second operation voltage of a level different from that of the first operation voltage is applied to the second local source line as the second source voltage ([0027]: during the programming, the source line voltage generator 12 applies, to the local source line LSL of the sector SCT3, the source line voltage which is optimized in accordance with the location of the sector SCT3; [0032]: When the cell array is constituted by a plurality of blocks each formed of a plurality of sectors, the source line voltage may be controlled in the above manner in accordance with the location of each block. In this case, the source line voltage is variably controlled in accordance with the block address of a block to be programmed. Examiner concludes that a second operation voltage which is applied to the second local source line may be optimized based on the second block’s location, and therefore may be different from the first operation voltage).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Watanabe to modified Ju wherein a second operation voltage of a level different from that of the first operation voltage is applied to the second local source line as the second source voltage in order to optimize programming by optimizing the drain-source voltage of selected cells (Watanabe, [0015]).
Claims 11 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Micheloni (US Pub. 20040170061 A1) as applied to claim 10 above, and further in view of Lee (US Pub. 20190019558 A1).
Regarding claim 11, Micheloni discloses the limitations of claim 10, and further through Micheloni:
a voltage generation circuit (Fig. 1: variable voltage generator Vg; [0047])
the first global source line (SL1) and the second global source line (SL2).
Micheloni does not explicitly disclose:
a voltage generation circuit generating the first source voltage and the second source voltage and supplying the first source voltage and the second source voltage to the first global source line and the second global source line.
However, Lee teaches:
a voltage generation circuit (Fig. 2: 210) generating the first source voltage and the second source voltage and supplying the first source voltage and the second source voltage to the first global source line and the second global source line ([0040]. Examiner asserts that Lee’s use of the term “global lines GL” indicates that the component GL consists of multiple global source lines).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Lee to Micheloni wherein the semiconductor device further comprises a voltage generation circuit generating the first source voltage and the second source voltage and supplying the first source voltage and the second source voltage to the first global source line and the second global source line in order to decrease the resistance of the vertical channel layers and decrease the size of the memory device (Lee, [0073] & [0079]).
Regarding claim 20, Micheloni discloses the limitations of claim 10. The limitations of claim 20 are the same as the limitations from claim 19, and are thus rejected for the same reasons.
Claims 12 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Micheloni (US Pub. 20040170061 A1) as applied to claim 10 above, and further in view of Watanabe (US Pub. 20030072176 A1).
Regarding claim 12, Micheloni discloses the limitations of claim 10. The limitations of claim 12 are mostly the same as the limitations from claim 8, and are thus rejected for the same reasons.
Regarding claim 13, Micheloni and Watanabe together disclose the limitations of claim 12. The limitations of claim 13 are the same as the limitations from claim 9, and are thus rejected for the same reasons.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Yun (US Pub. 20150287710 A1) in view of Esseni (US Pub. 20020033499 A1).
Regarding independent claim 16, Yun discloses a semiconductor device comprising:
a peripheral circuit ([0032]: Referring to FIG. 1, the semiconductor device may include a memory cell array 10 in which memory cells are arranged, and a peripheral circuit (not shown) that has functional circuits which operate the memory cells);
a gate structure including stacked gate lines (Fig. 3: gate electrodes 110; [0037]: In the cell region 20, the gate electrodes 110 and the interlayer insulating layers 102 may be alternately stacked in the vertical direction);
a bonding structure positioned between the peripheral circuit and the gate structure and electrically connecting the peripheral circuit and the gate structure ([0007]: Still other embodiments of the inventive concepts provide a connection structure for a semiconductor device that electrically connects vertically stacked electrodes to peripheral circuits and to related methods of fabricating such a connection structure);
Yun does not disclose:
local source lines positioned on the gate structure; and
source pass transistors controlling a connection between the local source lines and at least one global source line.
However, Esseni teaches:
local source lines (Fig. 3: local source lines 52; [0039]) positioned on the gate structure ([0035]: The architecture illustrated in FIG. 3 may be implemented using a standard process for stacked gate flash memories that uses two polysilicon levels and three metal levels); and
source pass transistors (pass gates 65) controlling a connection between the local source lines (local source lines 52) and at least one global source line ([0039]: The local source lines 52 are connected to the main source line 59 by pass gates 65 formed by NMOS selection transistors, the control terminals whereof are connected to the source selection line 60).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Esseni to Yun wherein a semiconductor device comprises local source lines positioned on the gate structure; and source pass transistors controlling a connection between the local source lines and at least one global source line in order implement a memory cell with higher efficiency by using low doping in the base region (Esseni, [0043]).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Yun (US Pub. 20150287710 A1) and Esseni (US Pub. 20020033499 A1) as applied to claim 16 above, and further in view of Micheloni (US Pub. 20040170061 A1).
Regarding claim 17, Yun and Esseni together disclose the limitations of claim 16. The limitations of claim 17 are substantially the same as the limitations from claim 10, and are thus rejected for the same reasons.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Yun (US Pub. 20150287710 A1) and Esseni (US Pub. 20020033499 A1) as applied to claim 16 above, and further in view of Ju (US Pub. 20070242552 A1).
Regarding claim 18, Yun and Esseni together disclose the limitations of claim 16. The limitations of claim 18 are substantially the same as the first two limitations from claim 1, and are thus rejected for the same reasons.
Allowable Subject Matter
Claims 6 and 7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Kim (US Pub. 20220052066 A1): para. [0073] and Fig. 8 are relevant to claim 16.
Lee et al. (US Pub. 20160260489 A1): paras. [0126] and [0128] and Fig. 15 are relevant to claims 1, 10, and 16.
Lee (US Pub. 20190252023 A1): paras. [0019] and [0032]-[0033] and Figs. 2 and 4 are relevant to claims 1, 10, and 16.
Nam et al. (US Pub. 20150287479 A1): paras. [0050]-[0051], [0092], and [0105], and Figs. 4-5B are relevant to claims 1, 10, and 16.
Pyeon et al. (US Pub. 20120236647 A1): paras. [0039], [0050], and Figs. 2-3 are relevant to claims 1, 10, and 16.
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/E.R.A./Examiner, Art Unit 2824
/HAN YANG/Primary Examiner, Art Unit 2824
3/12/2026