Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to the Application filed June 22, 2026.
Status of claims to be treated in this office action:
a. Independent: 1, 6, 10, and 16
b. Pending: 1, 3, and 5-20
Claims 1, 6, 10, and 16-20 have been amended, claim 4 has been canceled, and claim 2 was previously canceled.
Specification
The new title has been reviewed and accepted by the Examiner.
Claim Objections
The claim objections are withdrawn pursuant to claim amendments.
Claim Rejections - 35 USC § 112
The rejection of claim 1 under 35 U.S.C. 112(b) has been withdrawn pursuant to claim amendments.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 3, 5, 6-7, 8-9, 11, and 19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "first pass transistor" in line 7 of claim 1 on page 3. There is insufficient antecedent basis for this limitation in the claim. The phrase “first source pass transistor” should be used instead. Claim 1 also recites the limitation "second pass transistor" in line 10 of claim 1 on page 3. There is insufficient antecedent basis for this limitation in the claim. The phrase “second source pass transistor” should be used instead. Claim 1 and claims 3, 5, 8-9, and 19, which depend on independent claim 1, are thus rejected under 35 U.S.C. 112(b).
Claim 6 also recites the limitations "first pass transistor" and "second pass transistor" on lines 6 and 9 of p.5, respectively, and thus claim 6 and claim 7, which depends on independent claim 6, are also rejected under 35 U.S.C. 112(b).
Claim 11 recites “supplying the first source voltage and the second source voltage to the first global source line and the second global source line.” in the third and fourth lines of claim 11 on p.6. This phrase is indefinite because it is unclear which source voltage is supplied to which global source line. Examiner believes that either source voltage can be supplied to either global source line, but the claim is written broadly.
Response to Arguments
Applicant’s arguments with respect to claims 1, 3-5, and 8-20 have been considered but are moot because the new ground of rejection relies on newly found references along with previously used references applied in the prior rejection of record. New grounds of rejection are made in view of Lee (US Pub. 20120195123 A1; “Lee-123”) and Ha et al. (US Pub. 20060274579 A1; “Ha”). Lee-123 paras. [0018] and [0064] and Fig. 3 are relevant to claims 1, 6, 10, and 16; and Ha paras. [0008] and [0011] and Figs. 1 and 3 are relevant to claims 1, 6, 10, and 16.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 10-15 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Lee-123 (US Pub. 20120195123 A1).
Regarding independent claim 10, Lee-123 discloses a semiconductor device (Fig. 3: NOR flash nonvolatile memory device, 200; [0064]) comprising:
a first source pass transistor (source line select transistor 265a; [0065]) controlling a connection between a first global source line (GSL0) and a first local source line (local source line LSL0; [0064]);
a second source pass transistor (265n) controlling a connection between a second global source line (GSLn) and a second local source line (LSLn); and
a memory block (array 205; [0064]) including a first sub-memory block (cells 210 connected to LSL0) using a first source voltage supplied through the first local source line ([0065]: The global bit lines GBL0, . . . , GBLn and the global source lines GSL0, . . . , GSLn are connected to the column voltage control circuit 255. The column voltage control circuit 255 generates the appropriate voltage levels for selectively reading, programming, and erasing the dual floating gate transistor NOR flash cells 210) and a second sub-memory block (cells 210 connected to LSLn) using a second source voltage supplied through the second local source line ([0065]).
Regarding claim 11, Lee-123 discloses the limitations of claim 10, and further through Lee-123:
a voltage generation circuit generating the first source voltage and the second source voltage and supplying the first source voltage and the second source voltage to the first global source line and the second global source line ([0076]: The erase voltage generator 340 is also connected to the bit line select control sub-circuit 251 and source line select control sub-circuit 253 for providing the very large positive erase select voltage to connect global bit lines GBL0, . . . , GBLn to the local bit line LBL0, LBL1, . . . , LBLn-1, and LBLn and the global source lines GSL0, . . . , GSLn and the local source lines LSL0, LSL1, . . . , LSLn-1, and LSLn; [0065]: The global bit lines GBL0, . . . , GBLn and the global source lines GSL0, . . . , GSLn are connected to the column voltage control circuit 255. The column voltage control circuit 255 generates the appropriate voltage levels for selectively reading, programming, and erasing the dual floating gate transistor NOR flash cells 210).
Regarding claim 12, Lee-123 discloses the limitations of claim 10, and further through Lee-123:
wherein during a program operation, the first sub-memory block of the memory block is selected, and a first operation voltage is applied to the first local source line as the first source voltage (Fig. 9 shows a voltage difference between “SLG SEL” and “SLG UNSEL” for the program operation, and the SLG signals/lines control which local source line is connected to the global source line, and therefore controls which local source line receives a high or low voltage; [0073]: The source line select control sub-circuit 253 receives the decoded program, erase, and read timing and control signals from the control decoder 305 and the decoded addresses from the address decoder 325. The source line select control sub-circuit 253 selects which of the source line select signals SLG0 and SLG1 that activates the source line select transistors 265a, . . . , 265n that connects the local source lines LSL0, LSL1, . . . , LSLn-1, and LSLn to which the selected NOR flash nonvolatile memory device 200 is connected to the associated global source lines GSL0, . . . , GSLn; [0068]; also see [0018]-[0019] for descriptions of programming and erasing half-blocks of memory).
Regarding claim 13, Lee-123 discloses the limitations of claim 10, and further through Lee-123:
wherein a second operation voltage of a level different from that of the first operation voltage is applied to the second local source line as the second source voltage (Fig. 9; [0073]; [0018]-[0019]; [0107]).
Regarding claim 14, Lee-123 discloses the limitations of claim 10, and further through Lee-123:
wherein during an erase operation, the first sub-memory block (cells 210 connected to LSL0) of the memory block (205) is selected, and an erase voltage is applied to the first local source line as the first source voltage ([0076]: The erase voltage generator 340 is also connected to the bit line select control sub-circuit 251 and source line select control sub-circuit 253 for providing the very large positive erase select voltage to connect global bit lines GBL0, . . . , GBLn to the local bit line LBL0, LBL1, . . . , LBLn-1, and LBLn and the global source lines GSL0, . . . , GSLn and the local source lines LSL0, LSL1, . . . , LSLn-1, and LSLn).
Regarding claim 15, Lee-123 discloses the limitations of claim 14, and further through Lee-123:
wherein a ground voltage is applied to the second local source line as the second source voltage ([0109]: the source line voltage control sub-circuit 253 activates the source line select signals SLG0 and SLG1 to a voltage level of very large program gating voltage of approximately +10V or the ground reference voltage level (0.0V) to selectively activate or deactivate the source line select transistors 265a, . . . , 265n to connect the selected local source lines LSL0, LSL1, . . . , LSLn-1, and LSLn to the global source lines GSL0, . . . , GSLn for selectively applying the programming voltage level that is approximately the ground reference voltage level or the large inhibit voltage level (+10.0V-Vt) to the drains of the selected floating gate transistors M0).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-5, 8-9, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lee-123 (US Pub. 20120195123 A1) in view of Ha (US Pub. 20060274579 A1).
Regarding independent claim 1, Lee-123 discloses a semiconductor device (Fig. 3: 200) comprising:
a global source line (GSL0);
a voltage generation circuit generating a first source voltage and a second source voltage and applying the first source voltage and the second source voltage to the global source line ([0076]);
a first source pass transistor (265a) controlling a connection between the global source line (GSL0) and a first local source line (LSL0), wherein the first source voltage is applied to the first local source line through the first pass transistor ([0068]: Each of the gates of the source line select transistors 265a, . . . , 265n is connected to the source line select control sub-circuit 253 within the row voltage control circuit 250 to provide the source line select signals SLG0 and SLG1 for activation of the source line select transistors 265a, . . . , 265n to connect a selected local source lines LSL0, LSL1, . . . , LSLn-1, and LSLn to its associated global source line GSL0, . . . , GSLn);
a second source pass transistor (265b) controlling a connection between the global source line (GSL0) and a second local source line (LSL1), wherein the second source voltage is applied to the second local source line through the second pass transistor ([0107]: The source line select control circuit 253 activates the source line select signals SLG0 and SLG1 to a voltage level of the ground reference voltage level to turnoff the source line select transistors 265a, . . . , 265n to disconnect the unselected local source lines LSL0, LSL1, . . . , LSLn-1, and LSLn to the global source lines GSL0, . . . , GSLn; [0068]; also see description of selected vs unselected half block in [0018]-[0019] and [0035]);
a first memory block (cells 210 connected to LSL0) including word lines (WL0-WLm) and using a first source voltage applied through the first local source line ([0068]);
a second memory block (cells 210 connected to LSL1) using a second source voltage applied through the second local source line ([0107]);
Lee-123 does not explicitly disclose:
global word lines; and
word line pass transistors controlling a connection between the global word lines and the word lines,
wherein the first source pass transistor and the word line pass transistors are controlled by the same block select signal.
However, Ha teaches:
global word lines (Fig. 3: wordline driving signals S0 through S15; [0009]); and
word line pass transistors (high-voltage pass transistors WN0 through WN15; [0011]) controlling a connection between the global word lines (S0 through S15) and the word lines (wordlines WL0 through WL15; [0008]),
wherein the first source pass transistor (high-voltage pass transistor CN; [0011]) and the word line pass transistors (WN0 through WN15) are controlled by the same block select signal (block wordline BLKWL; [0011]).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Ha to Lee-123 wherein there are global word lines; and word line pass transistors controlling a connection between the global word lines and the word lines, wherein the first source pass transistor and the word line pass transistors are controlled by the same block select signal in order to provide a multi-voltage generator that generates program, read, and high voltages in response to the operating mode of the memory device (Ha, [0003]).
Regarding claim 3, Lee-123 and Ha together disclose the limitations of claim 1, and further through Ha:
wherein the first memory block (Fig. 3: block memory cell array 110 & wordline driver 124; [0029] & [0009]) includes a drain select line (string select line SSL; [0008]), and
the semiconductor device (flash memory device 300; [0029]) further comprises:
a global drain select line (the line connected to string select voltage VSSL; [0009]); and
a drain select pass transistor (high-voltage pass transistor SN; [0011]) controlling a connection between the global drain select line and the drain select line ([0011]).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Ha to modified Lee-123 wherein the first memory block includes a drain select line, and the semiconductor device further comprises: a global drain select line; and a drain select pass transistor controlling a connection between the global drain select line and the drain select line in order to provide a multi-voltage generator that generates program, read, and high voltages in response to the operating mode of the memory device (Ha, [0003]).
Regarding claim 5, Lee-123 and Ha together disclose the limitations of claim 1, and further through Ha:
wherein the first memory block (Fig. 3: 110 & 124) includes a source select line (ground select line GSL; [0008]), and
the semiconductor device (300) further comprises:
a global source select line (the line connected to ground select voltage VGSL; [0009]); and
a source select pass transistor (high-voltage pass transistor GN; [0011]) controlling a connection between the global source select line and the source select line ([0011]).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Ha to modified Lee-123 wherein the first memory block includes a source select line, and the semiconductor device further comprises: a global source select line; and a source select pass transistor controlling a connection between the global source select line and the source select line in order to provide a multi-voltage generator that generates program, read, and high voltages in response to the operating mode of the memory device (Ha, [0003]).
Regarding claim 8, Lee-123 and Ha together disclose the limitations of claim 1. The limitations of claim 8 are substantially the same as the limitations from claim 12, and are thus rejected for the same reasons.
Regarding claim 9, Lee-123 and Ha together disclose the limitations of claim 8. The limitations of claim 9 are exactly the same as the limitations from claim 13, and are thus rejected for the same reasons.
Regarding claim 19, Lee-123 and Ha together disclose the limitations of claim 1, and further through Ha:
wherein the first memory block (Fig. 3: 110 & 124) includes memory strings (memory strings CS; [0008]), and each of the memory strings includes at least one drain select transistor (string select transistors SST; [0008]), a plurality of memory cells (memory cells M0 through M15; [0008]) and at least one source select transistor (ground select transistors GST; [0008]).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Ha to modified Lee-123 wherein the first memory block includes memory strings, and each of the memory strings includes at least one drain select transistor, a plurality of memory cells and at least one source select transistor in order to provide a multi-voltage generator that generates program, read, and high voltages in response to the operating mode of the memory device (Ha, [0003]).
Regarding claim 20, Lee-123 discloses the limitations of claim 10. The limitations of claim 20 are the same as the limitations from claim 19, and are thus rejected for the same reasons.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Yun (US Pub. 20150287710 A1) in view of Esseni (US Pub. 20020033499 A1), and Ha (US Pub. 20060274579 A1).
Regarding independent claim 16, Yun discloses a semiconductor device comprising:
a peripheral circuit ([0032]: Referring to FIG. 1, the semiconductor device may include a memory cell array 10 in which memory cells are arranged, and a peripheral circuit (not shown) that has functional circuits which operate the memory cells);
a gate structure (Fig. 3: gate electrodes 110; [0037]: In the cell region 20, the gate electrodes 110 and the interlayer insulating layers 102 may be alternately stacked in the vertical direction) including stacked word lines ([0036]: the cell gate electrodes 112 may correspond to wordlines. Per Fig. 3, cell gate electrodes 112 are stacked);
a bonding structure positioned between the peripheral circuit and the gate structure and electrically connecting the peripheral circuit and the gate structure ([0007]: Still other embodiments of the inventive concepts provide a connection structure for a semiconductor device that electrically connects vertically stacked electrodes to peripheral circuits and to related methods of fabricating such a connection structure);
Yun does not disclose:
a first local source line positioned on the gate structure;
a second local source line positioned on the gate structure;
a first source pass transistor controlling a connection between the first local source line and at least one global source line;
a second source pass transistor controlling a connection between the second local source line and the at least one global source line; and
word line pass transistors controlling a connection between the word lines and global word lines,
wherein the first source pass transistor and the word line pass transistors are controlled by the same block select signal.
However, Esseni teaches:
a first local source line (Fig. 3: leftmost local source line 52; [0039]) positioned on the gate structure ([0035]: The architecture illustrated in FIG. 3 may be implemented using a standard process for stacked gate flash memories that uses two polysilicon levels and three metal levels); and
a second local source line (middle local source line 52) positioned on the gate structure ([0035]);
a first source pass transistor (leftmost pass gate 65) controlling a connection between the first local source line (leftmost local source line 52) and at least one global source line ([0039]: The local source lines 52 are connected to the main source line 59 by pass gates 65 formed by NMOS selection transistors, the control terminals whereof are connected to the source selection line 60).
a second source pass transistor (middle pass gate 65) controlling a connection between the second local source line (middle local source line 52) and the at least one global source line ([0039]); and
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Esseni to Yun wherein a first local source line positioned on the gate structure; a second local source line positioned on the gate structure; a first source pass transistor controlling a connection between the first local source line and at least one global source line; a second source pass transistor controlling a connection between the second local source line and the at least one global source line; and in order implement a memory cell with higher efficiency by using low doping in the base region (Esseni, [0043]).
Also, through Ha:
word line pass transistors (Fig. 3: WN0-WN15) controlling a connection between the word lines (WL0-WL15) and global word lines (S0-S15),
wherein the first source pass transistor (CN) and the word line pass transistors (WN0-WN15) are controlled by the same block select signal (BLKWL).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Ha to modified Yun wherein there are word line pass transistors that control a connection between the word lines and global word lines, and wherein the first source pass transistor and the word line pass transistors are controlled by the same block select signal in order to provide a multi-voltage generator that generates program, read, and high voltages in response to the operating mode of the memory device (Ha, [0003]).
Claims 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Yun (US Pub. 20150287710 A1), Esseni (US Pub. 20020033499 A1), and Ha (US Pub. 20060274579 A1) as applied to claim 16 above, and further in view of Lee-123 (US Pub. 20120195123 A1).
Regarding claim 17, Yun, Esseni, and Ha together disclose the limitations of claim 16. The limitations of claim 17 are substantially the same as the limitations from claim 10, and are thus rejected for the same reasons.
Regarding claim 18, Yun, Esseni, and Ha together disclose the limitations of claim 16. The limitations of claim 18 are substantially the same as limitations from claim 1, and are thus rejected for the same reasons.
Allowable Subject Matter
Claims 6 and 7 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Independent claim 6 includes allowable subject matter since the prior art made of record and considered pertinent to the applicant’s disclosure, taken individually or in combination, does not teach or suggest the claimed invention having:
“during a read operation, the first memory block is selected, and a negative voltage is applied to the first local source line as the first source voltage”
The Examiner was not able to find additional references to logically combine with Lee-123, Ha, Yun, and Esseni in order to reject the other above features of claim 6. Claim 7 is also allowed due to its dependency on claim 6. Refer to conclusion section for relevant references.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Hirano (US Pat. 6072722 A): col. 18, lines 8-31 and Figs. 8, 9, and 12 are relevant to claims 1, 6, 10, and 16.
Liu et al. (US Pub. 20220366951 A1): para. [0175] and Figs. 2 and 8 are relevant to claims 1, 6, 10, and 16.
Lee (US Pub. 20050226048 A1): para. [0061] and Fig. 2 are relevant to claims 1, 6, 10, and 16.
Lee et al. (US Pub. 20230134907 A1): paras. [0132]-[0133] and Fig. 11 are relevant to claims 1, 6, 10, and 16.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/E.R.A./Examiner, Art Unit 2824
/HAN YANG/Primary Examiner, Art Unit 2824
8/21/2026
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