DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of claims
Claims 1-20 are pending in this application.
It appears that not all amendments to claim 1 were properly indicated. For example, amended claim 1 (filed 7/14/2026) does not recite the limitation wherein “a second portion extending from the first portion along a surface of the support layer,” as was recited in the original claim 1, filed 1/19/2024. This deletion was not indicated in the amended claim 1, filed 7/14/2026. For purposes of this office action, the deletion of the claimed subject matter is acknowledged. Applicant is kindly reminded that “All claims being currently amended in an amendment paper shall be presented in the claim listing, indicate a status of "currently amended," and be submitted with markings to indicate the changes that have been made relative to the immediate prior version of the claims. The text of any added subject matter must be shown by underlining the added text. The text of any deleted matter must be shown by strike-through except that double brackets placed before and after the deleted characters may be used to show deletion of five or fewer consecutive characters. The text of any deleted subject matter must be shown by being placed within double brackets if strike-through cannot be easily perceived--. See MPEP 714 and 37 CFR 1.121.
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Claim Objections
Claim 17 is objected to because of the following informalities: In line 17, the claim recites, “…and a second portion a surface of the support layer…”. Examiner believes that it should recite, “…and a second portion -- on -- a surface of the support layer…”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-8 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation “the second portion” in line 10. There is insufficient antecedent basis for this limitation in the claim. Hence the claim is rejected. For examination purposes, the limitation will be treated as “a second portion”. Claims 2-8 depend from claim 1 and are rejected at least for the reasons above.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1, 3-5, 8, 17 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over An et al. (US 2021/0125996 A1, newly cited).
Re Claim 1, An teaches a capacitor structure (Fig. 15), comprising:
a lower electrode (200, Fig. 15, para [0028]) on a substrate (100, Fig. 15, para [0029]);
a support layer (140+150, Fig. 15, para [0028]) on a sidewall of the lower electrode (200, see Fig. 15), the support layer including an insulating material (para [0044]);
an interface structure (245+250a+255, Fig. 15 in view of embodiment in Fig. 11, where layer 250 in Fig. 15 is made up of layers 250a+250b with layer 255 in between them, as shown in Fig. 11, see Examiner comments below, paras [0115] - [0117] and [0126]) on the lower electrode (200), the interface structure (245+250a+255) including:
a first interface pattern (245, Fig. 15, para [0126]) on the sidewall of the lower electrode (200), the first interface pattern including a first metal (245 can include first metal titanium, para [0128]), and
a second interface pattern (250a+255, Fig. 15 in view of Fig. 11, paras [0115] - [0117]) on the first interface pattern (245) and including an oxide of a second metal (250a can be an oxide of second metal like hafnium oxide, para [0048]), the second interface pattern (250a+255) including a first portion (marked “1st portion of 250a+255” in annotated Fig. 15 below) on an outer sidewall of the first interface pattern (outer sidewall of 245) and a second portion (marked “2nd portion of 250a+255” in annotated Fig. 15 below) including the first metal (“2nd portion of 250a+255” includes layer 255 which can also have the first metal titanium, para [0117]);
a dielectric pattern (250b, Fig. 15 in view of Fig. 11, see Examiner comments below, paras [0115] - [0117]) on the interface structure (245+250a+255); and
an upper electrode (260+270, Fig. 15, para [0029]) on the dielectric pattern (250b).
wherein the support layer (140+150, Fig. 15) is provided in a plurality of support layers spaced apart from each other in a vertical direction (140 and 150 are spaced apart in vertical direction, Fig. 15), and the dielectric pattern (250b, Fig. 15 in view of Fig. 11) is interposed between two adjacent support layers (140 and 150), and
wherein the second portion of the second interface pattern (“2nd portion of 250a+255”) contacts upper and lower surfaces of the two adjacent support layers facing each other (upper surface of 140 and lower surface of 150, see Fig. 15).
Examiner notes that layer 250 is shown as a single layer in the embodiment of Fig. 15. However, in another embodiment in Fig. 11, An discloses that the dielectric layer 250 can be made of a first portion 250a and a second portion 250b with an insertion film 255 in between (paras [0115] - [0117]). It would have been prima facie obvious to one of ordinary skill in the art, absent unexpected results, to modify the layer 250 in Fig. 15, such that the layer 250 is made of a first portion 250a and a second portion 250b with an insertion film 255 as shown in Fig. 11, because the insertion film 255 promotes crystallization of the capacitor dielectric film 250 (para [0116]). The modified capacitor structure of An is shown below.
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Re Claim 3, An teaches the capacitor structure of claim 1, wherein the first interface pattern (245, Fig. 15, para [0126]) includes the first metal, an oxide of the first metal or a nitride of the first metal (245 can be titanium oxide, para [0128]).
Re Claim 4, An teaches the capacitor structure of claim 1, wherein the first metal includes scandium (Sc), yttrium (Y), titanium (Ti), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), molybdenum (Mo), tungsten (W), iron (Fe), ruthenium (Ru), osmium (Os), cobalt (Co), rhodium (Rh), iridium (Ir), boron (B) or tin (Sn) (245 can include first metal titanium, para [0128], see claim 1 above).
Re Claim 5, An teaches the capacitor structure of claim 1, wherein the second metal includes a metal with four valance electrons or a metal with three valance electrons (second metal is hafnium which has four valance electrons, see claim 1 above).
Re Claim 8, An teaches the capacitor structure of claim 1, wherein a portion of the lower electrode (200, Fig. 15) contacting the first interface pattern (245) further includes the first metal (first metal is titanium, see claim 1 above, and lower electrode 200 can include titanium, para [0039]).
Re Claim 17, An teaches a semiconductor device, comprising:
an active pattern (“ACT”, Figs. 19-20, para [0141]) on a substrate (100, Figs. 15 and 20, para [0029]);
a gate structure (320, corresponding to word lines, “WL”, Figs. 19-20, para [0152]) in an upper portion of the active pattern (“ACT”, see Fig. 19), the gate structure extending in a first direction (DR3 direction, Fig. 19) substantially parallel to an upper surface of the substrate (100);
a bit line structure (bit lines, “BL”, Fig. 19, para [0143]) on a middle portion of the active pattern (“ACT”, see Fig. 19), the bit line structure extending in a second direction (DR4 direction, Fig. 19) substantially parallel to the upper surface of the substrate (100) and crossing the first direction (DR3 direction, Fig. 19);
a contact plug structure (360, corresponding to landing pad, “LP”, Figs. 19-20, para [0156]) on each of opposite ends of the active pattern (“ACT”, see Fig. 19);
a capacitor structure (capacitor structure in Fig. 15, similar to the one in Fig. 20) on the contact plug structure (360), the capacitor structure including:
a lower electrode (200, Fig. 15, para [0028]) on the substrate (100, Fig. 15, para [0029]);
a support layer (140+150, Fig. 15, para [0028]) on a sidewall of the lower electrode (200, see Fig. 15), the support layer including an insulating material (para [0044]);
an interface structure (245+250a+255, Fig. 15 in view of embodiment in Fig. 11, where layer 250 in Fig. 15 is made up of layers 250a+250b with layer 255 in between them, as shown in Fig. 11, see Examiner comments below, paras [0115] - [0117] and [0126]) including:
a first interface pattern (245, Fig. 15, para [0126]) on the sidewall of the lower electrode (200), the first interface pattern including a first metal (245 can include first metal titanium, para [0128]), and
a second interface pattern (250a+255, Fig. 15 in view of Fig. 11, paras [0115] - [0117]) including a first portion (marked “1st portion of 250a+255” in annotated Fig. 15 above) on an outer sidewall of the first interface pattern (outer sidewall of 245) and a second portion (marked “2nd portion of 250a+255” in annotated Fig. 15 above) on a surface of the support layer (140/150, see Fig. 15), the second interface pattern (250a+255) including an oxide of a second metal (250a can be an oxide of second metal like hafnium oxide, para [0048]), and the second portion of the second interface pattern further including the first metal (“2nd portion of 250a+255” includes layer 255 which can also have the first metal titanium, para [0117]);
a dielectric pattern (250b, Fig. 15 in view of Fig. 11, see Examiner comments below, paras [0115] - [0117]) on the interface structure (245+250a+255); and
an upper electrode (260+270, Fig. 15, para [0029]) on the dielectric pattern (250b).
wherein the support layer (140+150, Fig. 15) is provided in a plurality of support layers spaced apart from each other in a vertical direction (140 and 150 are spaced apart in vertical direction, Fig. 15), and the dielectric pattern (250b, Fig. 15 in view of Fig. 11) is interposed between two adjacent support layers (140 and 150), and
wherein the second portion of the second interface pattern (“2nd portion of 250a+255”) contacts upper and lower surfaces of the two adjacent support layers facing each other (upper surface of 140 and lower surface of 150, see Fig. 15).
Examiner notes that layer 250 is shown as a single layer in the embodiment of Fig. 15. However, in another embodiment in Fig. 11, An discloses that the dielectric layer 250 can be made of a first portion 250a and a second portion 250b with an insertion film 255 in between (paras [0115] - [0117]). It would have been prima facie obvious to one of ordinary skill in the art, absent unexpected results, to modify the layer 250 in Fig. 15, such that the layer 250 is made of a first portion 250a and a second portion 250b with an insertion film 255 as shown in Fig. 11, because the insertion film 255 promotes crystallization of the capacitor dielectric film 250 (para [0116]). The modified capacitor structure of An is shown above (see claim 1 rejection above).
Re Claim 19, An teaches the semiconductor device of claim 17, wherein the first metal includes scandium (Sc), yttrium (Y), titanium (Ti), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), molybdenum (Mo), tungsten (W), iron (Fe), ruthenium (Ru), osmium (Os), cobalt (Co), rhodium (Rh), iridium (Ir), boron (B) or tin (Sn) (245 can include first metal titanium, para [0128], see claim 17 above).
Re Claim 20, An teaches the semiconductor device of claim 17, wherein the second metal includes a metal with four valance electrons or a metal with three valance electrons (second metal is hafnium which has four valance electrons, see claim 17 above).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over An et al. (US 2021/0125996 A1, newly cited) and further in view of Moon et al. (US 2020/0091279 A1, of record).
Re Claim 6, An teaches the capacitor structure of claim 1, but does not explicitly disclose that the thickness of the second portion of the second interface pattern (250a+255, Fig. 15 in view of Fig. 11) is in a range of about 0.5 angstroms to about 2 angstroms.
Related art Moon teaches that the thickness of the crystallization induction film 150 can range from about 3 Å to about 7 Å (para [0032]) and the thickness of the dielectric layer 160 can range from about 30 Å to about 50 Å (para [0032]), which are equivalent to the film 255 and dielectric layer 250a of An respectively. It would have been obvious to one of ordinary skill in the art, at the time of invention, to optimize the thickness of the second portion of the second interface pattern, depending on the design needs and the capacitance of the DRAM capacitor and arrive at the claimed range. With respect to the limitations of the claim, where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. See In re Aller, 220 F.2d 454, 456, 105 USPQ 233 (CCPA 1955). The optimization of the claimed thickness range would have been obvious to one of ordinary skill in the art.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over An et al. (US 2021/0125996 A1, newly cited) and further in view of Moon et al. (US 2020/0091279 A1, of record) and Jung et al. (US 2021/0384197 A1, hereinafter Jung’197, of record).
Re Claim 7, An teaches the capacitor structure of claim 1, but does not explicitly state that the support layer (140+150, Fig. 15) further includes the first metal and the second metal.
Related art, Moon discloses that the dielectric structure of the capacitor can be annealed at an elevated temperature to improve the performance of the capacitor structure (para [0120]). Furthermore, Jung’197 teaches that during the annealing step, metals from the metal-oxides layers of the dielectric structure may diffuse or migrate into nearby layers (paras [0010] – [0011]). Therefore, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, that during the annealing step of An modified by Moon and Jung’197, the first and second metals (from layers 250a+255, Fig. 15, see claim 1 above) can diffuse or migrate into the nearby support layer (140+150, Fig. 15), thus satisfying the claim limitation.
Rejection 2
Claim Rejections - 35 USC § 102
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-6, 8-13, 15 and 17-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (US 2022/0416010 A1, newly cited).
Re Claim 1, Lee teaches a capacitor structure (Figs. 7B and 10), comprising:
a lower electrode (LE2, Fig. 7B, para [0076]) on a substrate (210, Fig. 7B, para [0072]);
a support layer (226P+242P+244P, Fig. 7B, paras [0075] and [0078]) on a sidewall of the lower electrode (LE2, see Fig. 7B), the support layer including an insulating material (paras [0075] and [0078]);
an interface structure (250C1+250C2+250C3, Fig. 10, paras [0097] – [0099]) on the lower electrode (LE2), the interface structure including:
a first interface pattern (250C1, Fig. 10, paras [0097] – [0099]) on the sidewall of the lower electrode (LE2), the first interface pattern including a first metal (250C1 can have a first metal element, para [0098]), and
a second interface pattern (250C2+250C3, Fig. 10, paras [0097] – [0099]) on the first interface pattern (250C1) and including an oxide of a second metal (250C2 can be an oxide made of a second metal element para [0098]), the second interface pattern (250C2+250C3) including a first portion (250C2) on an outer sidewall of the first interface pattern (outer sidewall of 250C1) and a second portion (250C3) including the first metal (250C3 can also include first metal as 250C1, para [0098]);
a dielectric pattern (260, Fig. 10, paras [0076]) on the interface structure (250C1+250C2+250C3, Fig. 10); and
an upper electrode (UE2, Figs. 7B and 10, para [0076]) on the dielectric pattern (260);
wherein the support layer (226P+242P+244P, Fig. 7B) is provided in a plurality of support layers spaced apart from each other in a vertical direction (226P, 242P and 244P are spaced apart in vertical direction, Fig. 7B), and the dielectric pattern (260, Figs. 7B and 10) is interposed between two adjacent support layers (see Fig. 7B), and
wherein the second portion (250C3) of the second interface pattern (250C2+250C3) contacts upper and lower surfaces of the two adjacent support layers facing each other (upper surface of 226P and lower surface of 242P, see Figs. 7B and 10).
Re Claim 2, Lee teaches the capacitor structure of claim 1, wherein a thickness in the vertical direction of the second portion (vertical height of 250C3, Fig. 10) of the second interface pattern (250C2+250C3, Fig. 10) is greater than a thickness in a horizontal direction of the first portion (horizontal width of 250C2, Fig. 10) of the second interface pattern (250C2+250C3, Fig. 10), the vertical direction being substantially perpendicular to an upper surface of the substrate (compare Figs. 7B and 10), and the horizontal direction being substantially parallel to the upper surface of the substrate (compare Figs. 7B and 10).
Re Claim 3, Lee teaches the capacitor structure of claim 1, wherein the first interface pattern (250C1, Fig. 10) includes the first metal, an oxide of the first metal or a nitride of the first metal (250C1 can have a first metal element, para [0098]).
Re Claim 4, Lee teaches the capacitor structure of claim 1, wherein the first metal includes scandium (Sc), yttrium (Y), titanium (Ti), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), molybdenum (Mo), tungsten (W), iron (Fe), ruthenium (Ru), osmium (Os), cobalt (Co), rhodium (Rh), iridium (Ir), boron (B) or tin (Sn) (250C1 can be an oxide of a first metal element, like titanium, paras [0040] and [0098]).
Re Claim 5, Lee teaches the capacitor structure of claim 1, wherein the second metal includes a metal with four valance electrons or a metal with three valance electrons (250C2 can be an oxide made of a second metal element para [0098], for example tin, para [0040], where tin has four valence electrons).
Re Claim 6, Lee teaches the capacitor structure of claim 1, wherein a thickness of the second portion (250C3) of the second interface pattern (250C2+250C3) is in a range of about 0.5 angstroms to about 2 angstroms (total thickness of the interface layer 250 can be 3 angstrom, para [0042], hence thickness of 250C3 layer can be 3/3 = 1 angstrom).
Re Claim 8, Lee teaches the capacitor structure of claim 1, wherein a portion of the lower electrode (LE2, Fig. 10) contacting the first interface pattern (250C1) further includes the first metal (LE2 and 250C1, both can comprise of a first metal titanium, paras [0037] and [0040]).
Re Claim 9, Lee teaches a capacitor structure, comprising:
a lower electrode (LE2, Fig. 7B, para [0076]) on a substrate (210, Fig. 7B, para [0072]);
a support layer (226P+242P+244P, Fig. 7B, paras [0075] and [0078]) on a sidewall of the lower electrode (LE2, see Fig. 7B), the support layer including an insulating material (paras [0075] and [0078]);
an interface structure (250C1+250C2+250C3, Fig. 10, paras [0097] – [0099]) on the lower electrode (LE2), the interface structure including:
a first interface pattern (250C1, Fig. 10, paras [0097] – [0099]) on the sidewall of the lower electrode (LE2), the first interface pattern including an oxide of a first metal (250C1 can be an oxide of a first metal element para [0098]), and
a second interface pattern (250C2+250C3, Fig. 10, paras [0097] – [0099]) on the first interface pattern (250C1) and including an oxide of a second metal (250C2 can be an oxide of a second metal element para [0098]), the second interface pattern (250C2+250C3) including a first portion (250C2) on an outer sidewall of the first interface pattern (outer sidewall of 250C1) and a second portion (250C3) extending from the first portion (250C2) along a surface of the support layer (226P, Fig. 7B);
a dielectric pattern (260, Fig. 10, paras [0076]) on the interface structure (250C1+250C2+250C3, Fig. 10); and
an upper electrode (UE2, Figs. 7B and 10, para [0076]) on the dielectric pattern (260),
wherein a thickness in a vertical direction of the second portion (vertical height of 250C3, Fig. 10) of the second interface pattern (250C2+250C3, Fig. 10) is greater than a thickness in a horizontal direction of the first portion (horizontal width of 250C2, Fig. 10) of the second interface pattern (250C2+250C3, Fig. 10), the vertical direction being substantially perpendicular to an upper surface of the substrate (compare Figs. 7B and 10), and the horizontal direction being substantially parallel to the upper surface of the substrate (compare 7B and 10);
wherein the support layer (226P+242P+244P, Fig. 7B) is provided in a plurality of support layers spaced apart from each other in the vertical direction (226P, 242P and 244P are spaced apart in vertical direction, Fig. 7B), and the dielectric pattern (260, Figs. 7B and 10) is interposed between two adjacent support layers (see Fig. 7B), and
wherein the second portion (250C3) of the second interface pattern (250C2+250C3) contacts upper and lower surfaces of the two adjacent support layers facing each other (upper surface of 226P and lower surface of 242P, see Figs. 7B and 10).
Re Claim 10, Lee teaches the capacitor structure of claim 9, wherein the second portion (250C3) of the second interface pattern (250C2+250C3) further includes the first metal (250C3 can also include first metal as 250C1, para [0098]).
Re Claim 11, Lee teaches the capacitor structure of claim 9, wherein the first metal includes scandium (Sc), yttrium (Y), titanium (Ti), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), molybdenum (Mo), tungsten (W), iron (Fe), ruthenium (Ru), osmium (Os), cobalt (Co), rhodium (Rh), iridium (Ir), boron (B) or tin (Sn) (250C1 can be an oxide made of a first metal element, like titanium, paras [0040] and [0098]).
Re Claim 12, Lee teaches the capacitor structure of claim 9, wherein the second metal includes a metal with four valance electrons or a metal with three valance electrons (250C2 can be an oxide made of a second metal element para [0098], for example tin, para [0040], where tin has four valence electrons).
Re Claim 13, Lee teaches the capacitor structure of claim 9, wherein a thickness of the second portion (250C3) of the second interface pattern (250C2+250C3) is in a range of about 0.5 angstroms to about 2 angstroms (total thickness of the interface layer 250 can be 3 angstrom, para [0042], hence thickness of 250C3 layer can be 3/3 = 1 angstrom).
Re Claim 15, Lee teaches the capacitor structure of claim 9, wherein a portion of the lower electrode (LE2, Fig. 10) contacting the first interface pattern (250C1) further includes the first metal (LE2 and 250C1, both can comprise of a first metal titanium, paras [0037] and [0040]).
Re Claim 17, Lee teaches a semiconductor device, comprising:
an active pattern (“AC”, Figs. 6 and 7B, para [0069]) on a substrate (210, Fig. 7B, para [0072]);
a gate structure (word lines, “WL”, Figs. 6 and 7B, para [0069]) in an upper portion of the active pattern (“AC”, see Fig. 6), the gate structure extending in a first direction (x-axis, Fig. 6) substantially parallel to an upper surface of the substrate (Figs. 6 and 7B, para [0069]);
a bit line structure (bit lines, “BL”, Fig. 6, para [0070]) on a middle portion of the active pattern (“AC”, see Fig. 6), the bit line structure extending in a second direction (y-axis, Fig. 6) substantially parallel to the upper surface of the substrate (Figs. 6 and 7B, para [0070]) and crossing the first direction (x-axis, Fig. 6);
a contact plug structure (224, corresponding to landing pad, “LP”, Figs. 6 and 7B, para [0074]) on each of opposite ends of the active pattern (“AC”, Figs. 6 and 7B);
a capacitor structure (capacitor structure in Figs. 7B and 10) on the contact plug structure (224), the capacitor structure including:
a lower electrode (LE2, Fig. 7B, para [0076]) on the substrate (210, Fig. 7B, para [0072]);
a support layer (226P+242P+244P, Fig. 7B, paras [0075] and [0078]) on a sidewall of the lower electrode (LE2, see Fig. 7B), the support layer including an insulating material (paras [0075] and [0078]);
an interface structure (250C1+250C2+250C3, Fig. 10, paras [0097] – [0099]) including:
a first interface pattern (250C1, Fig. 10, paras [0097] – [0099]) on the sidewall of the lower electrode (LE2), the first interface pattern including a first metal (250C1 can have a first metal element, para [0098]), and
a second interface pattern (250C2+250C3, Fig. 10, paras [0097] – [0099]) including a first portion (250C2) on an outer sidewall of the first interface pattern (outer sidewall of 250C1) and a second portion (250C3) on a surface of the support layer (226P, Fig. 10), the second interface pattern (250C2+250C3) including an oxide of a second metal (250C2 can be an oxide made of a second metal element para [0098]), and the second portion (250C3) of the second interface pattern further including the first metal (250C3 can also include first metal as 250C1, para [0098]);
a dielectric pattern (260, Fig. 10, paras [0076]) on the interface structure (250C1+250C2+250C3, Fig. 10); and
an upper electrode (UE2, Figs. 7B and 10, para [0076]) on the dielectric pattern (260);
wherein the support layer (226P+242P+244P, Fig. 7B) is provided in a plurality of support layers spaced apart from each other in a vertical direction (226P, 242P and 244P are spaced apart in vertical direction, Fig. 7B), and the dielectric pattern (260, Figs. 7B and 10) is interposed between two adjacent support layers (see Fig. 7B), and
wherein the second portion (250C3) of the second interface pattern (250C2+250C3) contacts upper and lower surfaces of the two adjacent support layers facing each other (upper surface of 226P and lower surface of 242P, see Figs. 7B and 10).
Re Claim 18, Lee teaches the semiconductor device of claim 17, wherein a thickness in the vertical direction of the second portion (vertical height of 250C3, Fig. 10) of the second interface pattern (250C2+250C3, Fig. 10) is greater than a thickness in a horizontal direction of the first portion (horizontal width of 250C2, Fig. 10) of the second interface pattern (250C2+250C3, Fig. 10), the vertical direction being substantially perpendicular to an upper surface of the substrate (compare Figs. 7B and 10), and the horizontal direction being substantially parallel to the upper surface of the substrate (compare Figs. 7B and 10).
Re Claim 19, Lee teaches the semiconductor device of claim 17, wherein the first metal includes scandium (Sc), yttrium (Y), titanium (Ti), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), molybdenum (Mo), tungsten (W), iron (Fe), ruthenium (Ru), osmium (Os), cobalt (Co), rhodium (Rh), iridium (Ir), boron (B) or tin (Sn) (250C1 can be an oxide made of a first metal element, like titanium, paras [0040] and [0098]).
Re Claim 20, Lee teaches the semiconductor device of claim 17, wherein the second metal includes a metal with four valance electrons or a metal with three valance electrons (250C2 can be an oxide made of a second metal element para [0098], for example tin, para [0040], where tin has four valence electrons).
Claim Rejections - 35 USC § 103
Claims 7 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2022/0416010 A1, newly cited) and further in view of Moon et al. (US 2020/0091279 A1, of record) and Jung et al. (US 2021/0384197 A1, hereinafter Jung’197, of record).
Re Claim 7, Lee teaches the capacitor structure of claim 1, but does not state that the support layer (226P+242P+244P, Figs. 7B and 10) further includes the first metal and the second metal.
Related art, Moon discloses that the dielectric structure of the capacitor can be annealed at an elevated temperature to improve the performance of the capacitor structure (para [0120]). Furthermore, Jung’197 teaches that during the annealing step, metals from the metal-oxides layers near the dielectric structure may diffuse or migrate into nearby layers (paras [0010] – [0011]). Therefore, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, that during the annealing step of the dielectric structure (260, Fig. 10, Lee) of Lee modified by Moon and Jung’197, the first and second metals (from layers 250C2+250C3, Fig. 10, Lee) can diffuse or migrate into the nearby support layer (226P+242P+244P, Figs. 7B and 10), thus satisfying the claim limitation.
Re Claim 14, Lee teaches the capacitor structure of claim 9, but does not state that the support layer (226P+242P+244P, Figs. 7B and 10) further includes the first metal and the second metal.
Related art, Moon discloses that the dielectric structure of the capacitor can be annealed at an elevated temperature to improve the performance of the capacitor structure (para [0120]). Furthermore, Jung’197 teaches that during the annealing step, metals from the metal-oxides layers near the dielectric structure may diffuse or migrate into nearby layers (paras [0010] – [0011]). Therefore, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, that during the annealing step of the dielectric structure (260, Fig. 10, Lee) of Lee modified by Moon and Jung’197, the first and second metals (from layers 250C2+250C3, Fig. 10, Lee) can diffuse or migrate into the nearby support layer (226P+242P+244P, Figs. 7B and 10), thus satisfying the claim limitation.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2022/0416010 A1, newly cited) and further in view of Moon et al. (US 2020/0091279 A1, of record).
Re Claim 16, Lee teaches the capacitor structure of claim 1, but does not disclose that it further comprises an interface oxide layer between the dielectric pattern (260, Fig. 10) and the upper electrode (UE2).
Related art, Moon teaches a similar capacitor structure (Fig. 7B), which further comprises an interface oxide layer (580, Fig. 7B, para [0064]) between the dielectric pattern (170) and the upper electrode (640). The interfacial film 580 functions as a barrier preventing diffusion of oxygen from the dielectric structure toward the top electrode (para [0065]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to modify the capacitor structure of Lee such that to include an interface oxide layer between the dielectric pattern and the upper electrode, as taught by Moon, because the interfacial oxide layer functions as a barrier preventing diffusion of oxygen from the dielectric structure toward the top electrode (para [0065], Moon).
Response to Arguments
Applicant’s arguments with respect to claims 1, 9 and 17 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/P.D./Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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