DETAILED ACTION
Claim Rejections - 35 USC § 103
1. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
2. Claim(s) 1 – 4, 6 - 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (20210375826) in view of Chang et al. (11424212).
With regard to claim 1, Chen et al. disclose a semiconductor package (for example, see fig. 5) comprising:
a chip structure (a chip structure including chips 100, 200) comprising a first stack semiconductor chip (100, 200), which comprises a first sub-chip (200) and a second sub-chip (100) that is bonded to the first sub-chip (200) and is of a different type (different size chips functioning as different type chips) from the first sub-chip (200),
a first molding layer (300) configured to mold the second sub-chip (100) on the first sub-chip (200), and
a first redistribution structure (606) arranged above the first stack semiconductor chip (100, 200) and the first molding layer (300);
a second redistribution structure (612) arranged under the chip structure (the chip structure including chips 100, 200) and bonded to the chip structure (the chip structure including chips 100, 200);
a second molding layer (an insulating encapsulation 610 functioning as a second molding layer) sealing, on the second redistribution structure (612), the chip structure (the chip structure including chips 100, 200) and the bonding wire (a metal layer, forming in vias 608 to create electrical and thermal connections between semiconductor chips, functioning as a bonding wire; for example, see paragraph [0073]).
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Chen et al. do not clearly disclose a bonding wire electrically connecting the second redistribution structure to the first redistribution structure wherein the bonding wire has a bent shape and extends non-linearly.
However, Chang et al. a bonding wire (50) electrically connecting the second redistribution structure (4) to the first redistribution structure (9) wherein the bonding wire (50) has a bent shape and extends non-linearly (for example, see fig. 5).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the Chen et al.’s device to have a bonding wire electrically connecting the second redistribution structure to the first redistribution structure wherein the bonding wire has a bent shape and extends non-linearly as taught by Chang et al. in order to secure electrical connection efficiency between the redistribution structures enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
With regard to claim 2, Chen et al. disclose the first sub-chip (200) comprises a first sub-chip pad (referred to as “200A” by examiner’s annotation shown in fig. 5 below) and a sub-through via (referred to as “V1” by examiner’s annotation shown in fig. 5 below), the second sub-chip (100) comprises a second sub-chip pad (referred to as “100A” by examiner’s annotation shown in fig. 5 below), and the first sub-chip pad (200A) is bonded to the second sub-chip pad (100A) through an internal connection terminal (an interconnect structure 204 functioning as an internal connection terminal).
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With regard to claim 3, Chen et al. disclose the first sub-chip (200) comprises a first sub-chip pad (referred to as “200A” by examiner’s annotation shown in fig. 5 below) and a sub-through via (referred to as “V1” by examiner’s annotation shown in fig. 5 below), the second sub-chip (100) comprises a second sub-chip pad (referred to as “100A” by examiner’s annotation shown in fig. 5 below; wherein the second sub-chip pad 100A including conductive layers), and the first sub-chip pad (200A) is directly bonded to the second sub-chip pad (100A).
With regard to claim 4, Chen et al. disclose the first sub-chip (200) comprises a first sub-chip pad (referred to as “200A” by examiner’s annotation shown in fig. 5 below) and a sub-through via (referred to as “V1” by examiner’s annotation shown in fig. 5 below) which are arranged on a first active surface (a top surface) of a first semiconductor substrate (a semiconductor layer 202 functioning as a first semiconductor substrate), the second sub-chip (100) comprises a second sub-chip pad (referred to as “100A” by examiner’s annotation shown in fig. 5 below) arranged on a second active surface (a bottom surface) of a second semiconductor substrate (102 as shown in fig. 5 below; or see fig. 9), and the first sub-chip pad (200A) and the second sub-chip pad (200A) bond between the first active surface and the second active surface.
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With regard to claim 6, Chen et al. disclose the first redistribution structure (606) comprises a first redistribution layer (606b) and a first redistribution bonding pad (a bond pad 770, forming in the first redistribution structure 606, functioning as a first redistribution bonding pad) electrically connected to the first redistribution layer (606b), the second redistribution structure (612) comprises a second redistribution layer pad (referred to as “612b1” by examiner’s annotation shown in fig. 5 below) and a second redistribution bonding pad (referred to as “612b2” by examiner’s annotation shown in fig. 5 below) electrically connected to the second redistribution layer (612b1), and the bonding wire (the metal layer, forming in vias 608 to create electrical and thermal connections between semiconductor chips, functioning as a bonding wire; for example, see paragraph [0073]) electrically connects the second redistribution bonding pad (612b2) to the first redistribution bonding pad (770).
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With regard to claim 7, Chen et al. disclose the first molding layer (300) is arranged on sidewalls of the second sub-chip (100) and between the first sub-chip (200) and the second sub-chip (100).
With regard to claim 8, Chen et al. disclose wherein, on the second redistribution structure (612), the second molding layer (encapsulating layers 610 or 780, 610 also functioning as the second molding layer) is arranged on (on the top or bottom surface) sidewalls of the first stack semiconductor chip (the first stack semiconductor chip including chips 100, 200), sidewalls of the first molding layer (300), and a top and side surfaces of the first redistribution structure (606).
With regard to claim 9, Chen et al. disclose the first redistribution structure (606) is arranged on an upper surface of the first molding layer (300) and an upper surface of the second sub-chip (100).
With regard to claim 10, Chen et al. disclose a first chip connection terminal (a connection distribution layer 400 functioning as a first chip connection terminal) is further arranged under the first sub-chip (200), the first chip connection terminal (400) being connected to the second redistribution structure (612), and an underfill layer (a dielectric layer 530 functioning as an underfill layer) supporting the first chip connection terminal (400) is further arranged under the first sub-chip (200).
3. Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (20210375826) in view of Chang et al. (11424212) and further in view of Kawaminami (10103124).
With regard to claim 5, Chen et al. do not clearly disclose the first sub-chip comprises a first lower sub-chip and a second lower sub-chip which are spaced apart from each other in a horizontal direction, the first lower sub-chip comprises a first lower sub-chip pad and a sub-through via, the second lower sub-chip comprises a second lower sub-chip pad, the second sub-chip comprises second sub-chip pads, and the first lower sub-chip pad and the second lower sub-chip pad are directly bonded to the second sub-chip pads respectively.
However, Kawaminami discloses the first sub-chip (12) comprises a first lower sub-chip (referred to as “12A1” by examiner’s annotation shown in fig. 17 below) and a second lower sub-chip (referred to as “12A2” by examiner’s annotation shown in fig. 17 below) which are spaced apart from each other in a horizontal direction, the first lower sub-chip (12A1) comprises a first lower sub-chip pad (referred to as “16A1” by examiner’s annotation shown in fig. 17 below) and a sub-through via (referred to as “V2” by examiner’s annotation shown in fig. 17 below), the second lower sub-chip (16A2) comprises a second lower sub-chip pad (referred to as “16A2” by examiner’s annotation shown in fig. 17 below), the second sub-chip (the second sub-chip comprising layers 41, 46) and comprises second sub-chip pads (conductive portions 47 functioning as second sub-chip pads), and the first lower sub-chip pad (16A1) and the second lower sub-chip pad (16A2) are directly bonded to the second sub-chip pads (47) respectively.
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the Chen et al. and Chang et al.’s device to have the first sub-chip comprises a first lower sub-chip and a second lower sub-chip which are spaced apart from each other in a horizontal direction, the first lower sub-chip comprises a first lower sub-chip pad and a sub-through via, the second lower sub-chip comprises a second lower sub-chip pad, the second sub-chip comprises second sub-chip pads, and the first lower sub-chip pad and the second lower sub-chip pad are directly bonded to the second sub-chip pads respectively as taught by Kawaminami in order to secure electrical connection efficiency for minimizing the signal interference and enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
Allowable Subject Matter
4. Claims 11 - 15 are allowable over the prior art of record because none of these references disclose or can be combined to yield the claimed invention such as a first redistribution structure comprising a fan-in region and fan-out regions, which surround the fan-in region, the first redistribution structure further comprising first redistribution bonding pads arranged in the fan-out regions; the second redistribution structure comprising a second redistribution bonding pad in the fan-in region; a bonding wire electrically connecting the second redistribution bonding pad in the fan-in region to a first redistribution bonding pad in one of the fan-out regions; and a second molding layer molding the chip structure and the bonding wire on the first redistribution structure in the fan-in region and the fan-out regions as recited in claim 11.
5. Claims 16 - 20 are allowable over the prior art of record because none of these references disclose or can be combined to yield the claimed invention such as a first redistribution structure comprising a fan-in region and fan-out regions, which are located on opposite sides of the fan-in region, the first redistribution structure further comprising a first redistribution bonding pad in the fan-out regions; a chip structure arranged on the first redistribution structure in the fan-in region; the second redistribution structure comprising a second redistribution bonding pad in the fan-in region; a bonding wire electrically connecting the second redistribution bonding pad in the fan-in region to the first redistribution bonding pad in the fan-out regions; and a second molding layer molding the chip structure and the bonding wire above the first redistribution structure in the fan-in region and the fan-out regions; second widths of the second redistribution structure and the first sub-chip are less than a first width of the first redistribution structure as recited in claim 16.
Response to Amendment
6. Applicant's arguments with respect to claims have been considered but are moot in view of the new ground(s) of rejection.
Conclusion
7. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
8. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TAN N TRAN whose telephone number is (571) 272 - 1923. The examiner can normally be reached on 8:30-5:00PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached on (571) 272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TAN N TRAN/
Primary Examiner, Art Unit 2812
Prosecution Insights