Detailed Office Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restriction
Applicant’s election without traverse of claims 1-13 in the reply filed on 9 January 2026 is acknowledged.
In addition, new claims 21-24 are examined.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-13 and 21-24
Claims 1-13 and 21-24 are rejected under 35 U.S.C. 103 as being unpatentable over Jalili et al. (2022/0247075; “Jalili”) in view of Kuznia et al. (2010/0067853; “Kuznia”), and further in view of Yu et al. (2019/0162901; “Yu”).
Regarding claim 1, Jalili discloses in figure 1, and related figures and text, embodiments of silicon lenses 106 integrated onto the surfaces of a transparent silicon substrates/wafers 104. Jalili, paragraph (“FIG. 1A shows a schematic diagram of a disclosed lens-integrated THz radiator source 100 that includes a radiator-array chip 102, a wafer 104 and a silicon lens 106 for fast high-resolution THz imaging and sensing applications in accordance with some embodiments. As can be seen in FIG. 1A, lens-integrated THz radiator source 100 generates a radiation beam 108 that is emitted from radiator-array chip 102, transmitted through wafer 104 (e.g., a silicon wafer), and focused by silicon lens 106 into a narrower radiation beam pattern and higher beam directivity. Note that while the directivity of a radiation beam emitted by radiator-array chip 102 can be boosted by lens 106, lens 106 has a limiting effect on the scanning range of the radiation beam. Generally speaking, the radiation pattern of radiation beam 108 is primarily determined by the following factors: (1) the on-chip antenna that emits the output power; (2) the size of the lens defined by lens radius denoted as R.sub.lens; (3) the thickness of the silicon wafer between the substrate 110 of chip 102 and base-surface of the hemispherical lens 106, denoted as L.sub.ext; and (4) the displacement/offset of a given on-chip antenna from the center of lens 106. Note that the thickness of the wafer 104 L.sub.ext, can be equivalently viewed as an extension length of a hyper hemispherical lens. Note that the disclosed lens-integrated THz radiator source 100 is configured to generate a wide-angle high-directivity electronic beam steering capable of imaging and scanning an object or a sample under test with fine resolution. Note that the field of view and scanning resolution of the lens-integrated THz radiator source 100 are generally determined by beam directivity, steering resolution and steering range of radiation beam 108.”).
Jalili – Figure 1A
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Further regarding claim 1, Kuznia discloses in figure 6, and related figures and text, for example, Kuznia – Selected Text, embodiments of lenses 2 and 3 disposed on opposing surfaces of transparent substrate 92.
Kuznia – Figure 6
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Kuznia – Selected Text
Abstract. A component system and method is described that is made of components for transmitting, routing and receiving "in-air" optical signals for placement on printed wiring boards (PWBs). The transmitters are components including a light source attached to a transparent substrate and aligned to a coupling lens. The transparent substrate can contain circuitry for controlling the light source, or the circuitry could be attached to the transparent substrate. The receivers include a light detector attached to a transparent substrate with circuitry for converting optical signals to electrical circuitry (integrated onto the transparent substrate or separately attached). The routing components include a lens for coupling light into an optical waveguide, an optical waveguide and, optionally, a second lens for coupling light from the optical waveguide. The component system allows in-air optical communication between PWBs, without requiring traditional connections and harnesses between the PWBs, thus increasing their reliability and throughput.
[0027] In various embodiments, light emitters, such as vertical-cavity-surface-emitting-lasers (VCSELs), and photodetectors can be, for example, flip-chip mounted to transparent substrates that contain integrated circuitry. Of course, other devices, whether light emitting or not may be found to be suitable, as well as other mounting approaches, and therefore may be used without departing from the spirit and scope of this disclosure. For example, integrated circuitry can be implemented directly on the substrate using a process such as silicon-on-sapphire, as one possible approach. For a silicon-on-sapphire approach, light emitters and photodetectors operating at wavelengths transparent to silicon can be directly mounted on silicon to form silicon supported circuitry. Alternatively, an integrated circuit device can be flip-chip mounted on the transparent sapphire substrate. The transparent substrate can have features to make electrical interconnections to a PWB. For example, these features might be solder balls, solder bumps, conductive epoxy, wire-bonds or leads, and so forth.
[0035] FIGS. 2A-C are perspective, side and bottom views, respectively, of an exemplary single data channel surface mount optical transmitter 2. The optical transmitter 2 configuration is in many respects, similar to the configuration described for the receiver 1 of FIGS. 1A-C. A lens 20 is disposed over transparent or light-transmittive substrate 24. Electrical conduits 28 provide electrical connection between the substrate 24 and the PWB. The substrate 24 contains integrated circuitry 33 that supports electrical to optical signal conversion. This circuitry 33 can be formed directly on the substrate, such as in a silicon-on-sapphire integrated circuitry process, or flip-chip bonded as a separate integrated circuit, or any other applicable method. An optical light emitter 32 is attached, using flip-chip technology or other technology, and is in electrical communication with circuitry 33 on the substrate 24. Lens 20 forms the optical power from the light emitter 32 into a beam that is transmitted from the package and can be coupled efficiently into another component.
[0037] FIGS. 3A-B are perspective and cross-sectional views of an exemplary single data channel optical through-board via 3. Lens elements 36, 48 operate to focus light into optical waveguide 40 that is held within mechanical support 44. Lenses 36, 48 may be symmetrical in shape or different in shape, depending on design preference. In operation, light transmitted by an optical transmitter (not shown) will be received by a lens 36, 48 and, being focused by lens 36, 48, will travel through waveguide 40 to the other lens 48, 36 for transmission off-via to another component (not shown). In some instances, the mechanical support 44 may operate as the waveguide 40. Also, in some instances, the via 3 may be configured in a non-fixed-linear manner, so as to allow light to be transmitted in an off-axis orientation.
[0040] FIG. 6 is side view illustration of an exemplary optical data communications embodiment 78 on PWBs in a layered configuration. A series of PWBs 90, 91, and 92 are stacked or layered so as to align respective optical transmitters 2, receivers 1, and vias 3. The various PWBs contain circuitry which supports communication with the optical transmitters 2 and receivers 1. For example, PWB 90 contains integrated circuits 82 that source data in an electrical format to surface mount optical transmitters 2 located on PWB 90. The integrated circuits 82 can also receive data in an electrical format from surface mount optical receivers 1, also located on PWB 90. PWB 91 contains integrated circuits 83, 85 and also surface mount optical receiver 1, transmitters 2, and optical through-board vias 3. PWB 92 contains optical vias 3, a surface mount optical receiver 1, and circuit 86.
[0041] In operation, optical signals from the surface mount transmitter 2 on PWB 90 can be transmitted to surface mount receiver 1 on PWB 92 via optical through-board vias 3 on PWB 91. Light passing through the optical through-board vias 3 on PWB 91 can be transmitted to surface mount optical receivers 1 on PWB 92. Conversely, light passing through optical through-board vias 3 on PWB 92 and optical through-board vias 3 on PWB 91 can be detected by surface mount optical receivers 1 on PWB 90. PWB 91 can also send and receive signals using its transmitters 2 and receiver 1. Combinations of receivers 1, transmitters 2, and vias 3 enable the PWBs to efficiently transmit/receive information from neighboring PWBs without resorting to heavy electrical cabling or even temperamental fiber optic lines. Additional PWBs (not shown) can be optionally placed above PWB 92 to form an arbitrarily high stack of PWBs in optical communication with one another.
Consequently, in light of Kuznia’s disclosures of stacked transparent substrates coupled by optically coupled lens disposed on opposing sides of the transparent substrates, it would have been obvious to one of ordinary skill in the art to modify Jalili’s silicon-integrated substrate and lens to disclose: a semiconductor device, comprising: a silicon substrate having a first side and a second side opposite to each other, and further having a first region and a second region; a first silicon lens formed in the first region and along a first surface of the silicon substrate on the first side of the silicon substrate; a second silicon lens formed in the first region and along a second surface of the silicon substrate on the second side of the silicon substrate; and a photonic die disposed in the first region and on the second side of the silicon substrate; Jalili, figure 1, and related figures and text; Kuznia, figure 6, and related figures and text, for example, Kuznia – Selected Text; because the resulting configuration would facilitate designing, fabricating, and deploying 3D packages with electrical devices, optical devices, hybrid interconnects, and grating couplers. Yu, figures 24A and 24B, and related figures and text, for example, Yu – Selected Text. Yu, paragraph [0012] (“Three-dimensional (3D) packages including both optical devices and electrical devices, and the method of forming the same are provided, in accordance with some embodiments. In particular, a hybrid interconnect is formed having conductive features for transmitting electrical signals and waveguides for transmitting optical signals. Dies for forming different computing sites are attached to the hybrid interconnect.”).
Yu – Figures 24A and 24B
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Abstract. In an embodiment, a method includes: forming an interconnect including waveguides and conductive features disposed in a plurality of dielectric layers, the conductive features including conductive lines and vias, the waveguides formed of a first material having a first refractive index, the dielectric layers formed of a second material having a second refractive index less than the first refractive index; bonding a plurality of dies to a first side of the interconnect, the dies electrically connected by the conductive features, the dies optically connected by the waveguides; and forming a plurality of conductive connectors on a second side of the interconnect, the conductive connectors electrically connected to the dies by the conductive features.
[0012] Three-dimensional (3D) packages including both optical devices and electrical devices, and the method of forming the same are provided, in accordance with some embodiments. In particular, a hybrid interconnect is formed having conductive features for transmitting electrical signals and waveguides for transmitting optical signals. Dies for forming different computing sites are attached to the hybrid interconnect. The different sites are optically and electrically connected by the hybrid interconnect. The intermediate stages of forming the packages are illustrated, in accordance with some embodiments. Some variations of some embodiments are discussed. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements.
[0013] FIGS. 1A and 1B illustrate a multi-chip system 100, in accordance with some embodiments. The multi-chip system 100 is, e.g., a high performance computing (HPC) system, and includes a plurality of sites 102, each of which is a separate computing system. FIG. 1A shows all of the sites 102, and FIG. 1B is a detailed view of a region 100A that shows four sites 102A through 102D.
[0014] The sites 102 are interconnected by an optical pathway 104, which allows the separate computing systems to communicate. In particular, the optical pathway 104 is a closed loop (or ring) that connects to each site 102 of the multi-chip system 100. As such, each site 102 may communicate with any of the other sites 102 via the optical pathway 104. In an embodiment, the optical pathway 104 includes a plurality of waveguides, and each waveguide connects two of the sites 102 in a peer-to-peer manner. In some embodiments the optical pathway 104 is a silicon photonic interconnect, although other types of optical pathways could be used. Each site 102 includes a processor die 106, memory dies 108, an electronic die 110, and a photonic die 112. The optical pathway 104 extends under one or more components of each site 102, but at least extends under the photonic die 112 of each site 102. The sites 102 are interconnected by an electrical pathway (not shown in FIGS. 1A and 1B, but described below).
[0015] The processor die 106 may be a central processing unit (CPU), graphics processing unit (GPU), application-specific integrated circuit (ASIC), or the like. The memory dies 108 may be volatile memory such as dynamic random-access memory (DRAM), static random-access memory (SRAM), or the like. In the embodiment shown, each site includes one processor die 106 and four memory dies 108, although it should be appreciated that each site 102 may include more or less memory dies 108.
[0016] The photonic die 112 transmits and receives optical signals. In particular, the photonic die 112 converts electrical signals from the processor die 106 to optical signals, and convert optical signals from the optical pathway 104 to electrical signals. Accordingly, the photonic die 112 is responsible for the input/output (I/O) of optical signals to/from the optical pathway 104. The photonic die 112 may be a photonic integrated circuit (PIC). The photonic die 112 is optically coupled to the optical pathway 104 and electrically coupled to the electronic die 110 by an optical I/O port 118 (illustrated below in FIGS. 8A and 8B). The electronic die 110 includes the electronic circuits needed to interface the processor die 106 with the photonic die 112. For example, the electronic die 110 may include controllers, transimpedance amplifiers, and the like. The electronic die 110 controls high-frequency signalling of the photonic die 112 according to electrical signals (digital or analog) received from the processor die 106. The electronic die 110 may be an electronic integrated circuit (EIC).
[0019] FIGS. 2A through 12B are various views of intermediate steps during a process for forming the multi-chip system 100, in accordance with some embodiments. FIGS. 2A through 12B are cross-sectional views, where figures ending with an “A” designation are illustrated along cross-section A-A of FIG. 1B (e.g., along the processor dies 106 and memory dies 108), and figures ending with a “B” designation are illustrated along cross-section B-B of FIG. 1B (e.g., along the memory dies 108, photonic dies 112, and electronic dies 110).
[0020] In FIGS. 2A and 2B, a substrate 202 is provided. The substrate 202 may be a semiconductor substrate, such as a bulk semiconductor or the like, which may be doped (e.g., with a p-type or an n-type dopant) or undoped. The substrate 202 may be a wafer, such as a silicon wafer. Other substrates, such as a multi-layered or gradient substrate may also be used. In some embodiments, the semiconductor material of the substrate 202 may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or combinations thereof. In an embodiment, the substrate 202 is a silicon wafer, e.g., a 12 inch silicon wafer. The substrate may be referred to as having a front side or surface (e.g., the side facing upwards in FIGS. 2A and 2B), and a back side or surface (e.g., the side facing downwards in FIGS. 2A and 2B). The substrate 202 has several regions, including a first region where the site 102A will be formed, and the second region where the site 102B will be formed.
[0033] The photonic dies 112 are bonded to the hybrid interconnect 220 such that the optical I/O port 118 of each photonic die 112 is disposed along the respective optical transmission path 218. Because the optical transmission paths 218 are substantially free of the conductive features 214, the optical I/O ports 118 have a clear line of sight to the respective grating coupler 206 of the waveguides 204.
[0054] In FIGS. 24A and 24B, the conductive pads 228 are formed on the exposed vias 212, and the back side of the remaining semiconductor material 302C. The passivation film 230 is formed on the conductive pads 228 and the back side of the remaining semiconductor material 302C. Openings are formed through the passivation film 230 to expose central portions of the conductive pads 228. The UBM 232 is formed on the conductive pads 228 and passivation film 230. The conductive connectors 234 are formed on the UBM 232.
[0055] After formation, the multi-chip systems 100 formed in the wafer may be singulated. Each singulated multi-chip system 100 includes multiple sites 102.
[0057] Embodiments may achieve advantages. Transmitting optical signals in the hybrid interconnect 220 may have less signal attenuation at high frequencies, lower crosstalk, and less switching noise than transmitting electrical signals with TSVs. Optical communication may allow for lower-latency and higher-bandwidth communication between some of the sites 102. The conductive features 214 allow electrical signals to also be transmitted between the sites 102. Allowing both electrical and optical interconnectivity in the same hybrid interconnect 220 may allow increased device performance in, e.g., HPC applications that include many interconnected computer systems.
[0058] In an embodiment, an interconnect includes: a first dielectric layer including a first material having a first refractive index, the first dielectric layer having a first surface and a second surface opposite the first surface; a waveguide in the first dielectric layer, the waveguide having a grating coupler defined by recesses in the waveguide, the waveguide including a second material having a second refractive index greater than the first refractive index; a plurality of second dielectric layers on the first surface of the first dielectric layer, the second dielectric layers each including the first material; a plurality of conductive features in the second dielectric layers, the conductive features including conductive lines and vias, an optical transmission path extending from the grating coupler to a top surface of the second dielectric layers being free from the conductive features; a plurality of vias extending through the first dielectric layer; and a plurality of conductive connectors on the second surface of the first dielectric layer, the vias electrically connecting the conductive connectors to the conductive features.
[0059] In some embodiments, the first material is silicon and the second material is silicon oxide. In some embodiments, the interconnect further includes: pads in a topmost layer of the second dielectric layers, the pads electrically connected to the vias. In some embodiments, no conductive features are disposed in each of the second dielectric layers along the optical transmission path. In some embodiments, top surfaces of the vias are level with the first surface of the first dielectric layer, and bottom surfaces of the vias are level with the second surface of the first dielectric layer. In some embodiments, a bottom surface of the waveguide is level with the second surface of the first dielectric layer. In some embodiments, the first dielectric layer is on and surrounds and the waveguide. In some embodiments, the first dielectric layer is disposed in the recesses of the waveguide defining the grating coupler. In some embodiments, the interconnect further includes: an insulator layer having a first side and a second side opposite the first side, the waveguide disposed on the first side of the insulator layer, the vias extending through the insulator layer; and a semiconductor material, the semiconductor material disposed on the second side of the insulator layer, the vias extending through the semiconductor material.
[0063] In some embodiments, the waveguides include grating couplers, and where the interconnect is substantially free of conductive features in regions extending between the grating couplers of the waveguides and respective photonic integrated circuits. In some embodiments, the bonding the plurality of dies to the first side of the interconnect includes: bonding the plurality of dies to the first side of the interconnect with hybrid bonding. In some embodiments, the bonding the plurality of dies to the first side of the interconnect includes: bonding the plurality of dies to the first side of the interconnect with conductive connectors.
Regarding dependent claims 2-13, it would have been obvious to one of ordinary skill in the art to modify Jalili in view of Kuznia and further in view of Yu’s embodiments, as applied in the rejection of claim 1, to disclose:
2. The semiconductor device of claim 1, further comprising a waveguide disposed on the second side of the silicon substrate and having a grating coupler. Jalili, figure 1, and related figures and text; Kuznia, figure 6, and related figures and text, for example, Kuznia – Selected Text; Yu, figures 24A and 24B, and related figures and text, for example, Yu – Selected Text.
3. The semiconductor device of claim 2, wherein the grating coupler is configured to allow the waveguide to receive light through both of the first silicon lens and the second silicon lens. Jalili, figure 1, and related figures and text; Kuznia, figure 6, and related figures and text, for example, Kuznia – Selected Text; Yu, figures 24A and 24B, and related figures and text, for example, Yu – Selected Text.
4. The semiconductor device of claim 2, wherein the first silicon lens and the second silicon lens are configured to collectively provide a focal point at the grating coupler. Jalili, figure 1, and related figures and text; Kuznia, figure 6, and related figures and text, for example, Kuznia – Selected Text; Yu, figures 24A and 24B, and related figures and text, for example, Yu – Selected Text.
5. The semiconductor device of claim 1, further comprising an electronic die disposed in the second region and on the second side of the silicon substrate. Jalili, figure 1, and related figures and text; Kuznia, figure 6, and related figures and text, for example, Kuznia – Selected Text; Yu, figures 24A and 24B, and related figures and text, for example, Yu – Selected Text.
6. The semiconductor device of claim 1, wherein the photonic die comprises a plurality of conductive features. Jalili, figure 1, and related figures and text; Kuznia, figure 6, and related figures and text, for example, Kuznia – Selected Text; Yu, figures 24A and 24B, and related figures and text, for example, Yu – Selected Text.
7. The semiconductor device of claim 6, wherein an optical transmission path extending from the first silicon lens, through the second silicon lens, to a grating coupler of the photonic die is free from the plurality of conductive features. Jalili, figure 1, and related figures and text; Kuznia, figure 6, and related figures and text, for example, Kuznia – Selected Text; Yu, figures 24A and 24B, and related figures and text, for example, Yu – Selected Text.
8. The semiconductor device of claim 1, further comprising a plurality of conductive connectors disposed on a first side of the photonic die opposite to its second side that faces the silicon substrate. Jalili, figure 1, and related figures and text; Kuznia, figure 6, and related figures and text, for example, Kuznia – Selected Text; Yu, figures 24A and 24B, and related figures and text, for example, Yu – Selected Text.
9. The semiconductor device of claim 8, further comprising a package substrate coupled to the photonic die via at least the plurality of conductive connectors. Jalili, figure 1, and related figures and text; Kuznia, figure 6, and related figures and text, for example, Kuznia – Selected Text; Yu, figures 24A and 24B, and related figures and text, for example, Yu – Selected Text.
10. The semiconductor device of claim 1, wherein the first silicon lens has a first curvature radius and the second silicon lens has a second curvature radius, and wherein the first curvature radius is identical to the second curvature radius. Jalili, figure 1, and related figures and text; Kuznia, figure 6, and related figures and text, for example, Kuznia – Selected Text; Yu, figures 24A and 24B, and related figures and text, for example, Yu – Selected Text.
11. The semiconductor device of claim 1, wherein the first silicon lens has a first curvature radius and the second silicon lens has a second curvature radius, and wherein the first curvature radius is different from the second curvature radius. Jalili, figure 1, and related figures and text; Kuznia, figure 6, and related figures and text, for example, Kuznia – Selected Text; Yu, figures 24A and 24B, and related figures and text, for example, Yu – Selected Text.
12. The semiconductor device of claim 1, wherein the first silicon lens has a first thickness and the second silicon lens has a second thickness, and wherein the first thickness is identical to the second thickness. Jalili, figure 1, and related figures and text; Kuznia, figure 6, and related figures and text, for example, Kuznia – Selected Text; Yu, figures 24A and 24B, and related figures and text, for example, Yu – Selected Text.
13. The semiconductor device of claim 1, wherein the first silicon lens has a first thickness and the second silicon lens has a second thickness, and wherein the first thickness is different from the second thickness. Jalili, figure 1, and related figures and text; Kuznia, figure 6, and related figures and text, for example, Kuznia – Selected Text; Yu, figures 24A and 24B, and related figures and text, for example, Yu – Selected Text.
because the resulting configurations would facilitate designing, fabricating, and deploying 3D packages with electrical devices, optical devices, hybrid interconnects, and grating couplers. Yu, figures 24A and 24B, and related figures and text, for example, Yu – Selected Text.
Regarding dependent claims 21-24, it would have been obvious to one of ordinary skill in the art to modify Jalili in view of Kuznia and further in view of Yu’s embodiments, as applied in the rejection of claims 1-13, to disclose:
21. A semiconductor package, comprising: a substrate disposed over a package substrate; a first silicon lens formed along a first surface of a silicon substrate; and a second silicon lens formed along a second surface of the silicon substrate, the second surface opposite to the first surface; and a photonic die formed on the second surface of the silicon substrate and comprising a grating coupler. Jalili, figure 1, and related figures and text; Kuznia, figure 6, and related figures and text, for example, Kuznia – Selected Text; Yu, figures 24A and 24B, and related figures and text, for example, Yu – Selected Text.
22. The semiconductor package of claim 21, wherein at least one of the first silicon lens or the second silicon lens is vertically aligned with the grating coupler. Jalili, figure 1, and related figures and text; Kuznia, figure 6, and related figures and text, for example, Kuznia – Selected Text; Yu, figures 24A and 24B, and related figures and text, for example, Yu – Selected Text.
23. The semiconductor package of claim 21, wherein the first silicon lens and the second silicon lens are laterally shifted from each other with a distance, wherein the distance is between about 0 micrometers ( m) and about 100 m, and wherein the first silicon lens and the second silicon lens are configured to collectively provide a focal point at the grating coupler, and wherein the first silicon lens and the second silicon lens each have a hemispheric profile. Jalili, figure 1, and related figures and text; Kuznia, figure 6, and related figures and text, for example, Kuznia – Selected Text; Yu, figures 24A and 24B, and related figures and text, for example, Yu – Selected Text.
24. The semiconductor package of claim 21, comprising: a plurality of first conductive features disposed over the grating coupler; and an electronic die disposed over the plurality of first conductive features and including a plurality of second conductive features, wherein the electronic die is formed along the second surface of the silicon substrate. Jalili, figure 1, and related figures and text; Kuznia, figure 6, and related figures and text, for example, Kuznia – Selected Text; Yu, figures 24A and 24B, and related figures and text, for example, Yu – Selected Text.
because the resulting configurations would facilitate designing, fabricating, and deploying 3D packages with electrical devices, optical devices, hybrid interconnects, and grating couplers. Yu, figures 24A and 24B, and related figures and text, for example, Yu – Selected Text.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETER RADKOWSKI whose telephone number is (571)270-1613. The examiner can normally be reached on M-Th 9-5. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thomas Hollweg, can be reached on (571) 270-1739. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/PETER RADKOWSKI/Primary Examiner, Art Unit 2874