DETAILED ACTION
This action is responsive to the amendments filed May 14, 2026. Prior to entry, claims 1-17 were pending with claims 6 and 13 withdrawn as being drawn to a nonelected invention. Claims 1, 4, 7, and 15 have been amended. Claims 18 and 19 are new. Thus, upon entry, claims 1-19 are presently pending. Claims 1, and 7 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
Applicant's amendment to the title of the invention is acknowledged and accepted. The objection to the title has been withdrawn.
Response to Amendment
Applicant's amendments clarifying claim 4 is acknowledged and accepted. The 112(b) indefiniteness rejections for claim 4 has been withdrawn. However, applicant's amendment for claim 15 shifting the terminology toward "the select gate for the second memory transistor" does not cure the deficiency (see new 112(b) rejection below).
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the following must be shown or the features canceled from the claims:
The specific disconnected sense amplifier of claim 18. No figure illustrates or depicts a sense amplifier in an electrically disconnected state relative to the first wiring (bit line) during an erase operation. Figs. 10 and 11 show a sense amplifier connected to the bit line but do not indicate any conditional mode or operation settings for the various control signals.
The specific decoder configuration comprising six connection transistors and four block selection lines with defined parallel groupings and connections to the first gate wiring, second wiring, second gate wiring, and third wiring of claim 19. Fig. 18 shows only the simpler two-block-select-line architecture.
No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112 – Written description
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 18 and 19 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claim 18, Applicant asserts on pg. 16 of Remarks that support for its features "are believed to be clear from the original disclosure, see for example Figure 11". The original specification does not provide adequate written description for a sense amplifier that is affirmatively "electrically disconnected" during erase as a positive structural or operational feature of the device. Figure 11 is a schematic circuit diagram of the sense amplifier circuit SA. It shows the internal transistors, including high-breakdown-voltage transistor 45 whose gate is controlled by signal line BLS and which sits in the path between the bit line and the remainder of the sense amplifier circuitry.
While transistor 45 is present in the path, the original specification never states that transistor 45 is turned off during erase, never describes controlling signal BLS during erase to isolate the sense amplifier from the bit line, and never describes the sense amplifier as being electrically disconnected from the first wiring during an erase operation. The mere existence of a transistor that could be turned off does not constitute a description of the positive claim limitation requiring that the sense amplifier is electrically disconnected from the first wiring during erase.
Regarding claim 19, the claim requires a specific decoder configuration comprising six connection transistors and four block selection lines with defined parallel groupings and connections to the first gate wiring, second wiring, second gate wiring, and third wiring. Applicant asserts on pg. 17 of Remarks that these features are supported by the original disclosure, see for example, Figure 18. Figure 18 and the corresponding description of the row decoder show a block select circuit that uses two block select lines (BLKSEL_A and BLKSEL_B) and two corresponding groups of block select transistors (35A and 35B). The original disclosure does not describe or illustrate the six-transistor, four-block-selection line network, the particular parallel pairings of transistors, or the specific connection topology recited in claim 19.
Claim Rejections - 35 USC § 112 – Indefiniteness
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 11, 15, 18, and 19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 11, the claim recites "… from a fourth timing before the first timing to the first timing." There is no figure or description in the specification that clearly identifies a fourth timing point occurring before a first timing point.
Regarding claim 15, the phrase "the select gate for the second memory transistor" lacks clear antecedent basis and creates ambiguity. It is unclear whether the phrase is intended to refer to the fourth gate wiring just introduced in the claim, the second gate wiring previously recited in claim 7, or some other element. The claim introduces the term "fourth gate wiring" and then uses different terminology ("the select gate for the second memory transistor") without establishing any relationship between the two. As a result, one of ordinary skill the art cannot determine the metes and bounds of the claim with reasonable certainty.
Regarding claim 18, the claim recites "a sense amplifier that is electrically disconnected from the first wiring during an erase operation." The limitation is indefinite because it uses purely functional language to define the relationship between the sense amplifier and the first wiring without reciting sufficient structure, material, or acts that perform the claimed function. It is unclear as to what structure or control mechanism achieves the electrical disconnection and whether the disconnection is performed by a specific switch or transistor within the sense amplifier, by an external isolation element, by control of an existing signal (such as BLS), or by some other means.
Regarding claim 19, the claim recites a decoder configuration comprising six connection transistors and four block selection lines with specific parallel groupings and connections to the first gate wiring, second wiring, second gate wiring and third wiring. The claim is indefinite because it does not clearly define the structural or operational relationships among the recited elements. In particular:
The claim does not specify how the first through sixth connection transistors are arranged relative to one another or relative to the voltage generation / voltage select circuitry already present in the device (e.g., whether they are connected in series or in parallel with the other select transistors, what their second ends are connected to, or how they transfer voltages during the erase operation).
The claim does not clarify the functional relationship between the four block selection lines and the control of the gate wirings during the erase operation performed with the first memory transistor selected.
As a result, one of ordinary skill in the art cannot determine with reasonable certainty the precise configuration being claimed or how the recited transistors and block selection lines interact to achieve the voltage relationships required by claim 1.
Claims 18 and 19 being rejected under 35 U.S.C. § 112(a) and § 112(b) as set forth above, are indefinite to the extent that their scope cannot be reasonably determined. Therefore, no prior-art rejection is made against claims 18 and 19 at this time. See MPEP 2173.06. Should Applicant amend the claims to overcome the indefiniteness rejections, prior-art rejections may be applied in a subsequent Office action.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-4, 7-11, and 14-17 are rejected under 35 U.S.C. 103 as being unpatentable over Maeda (US 8537615 – of record), in view of Nam et al. (US 20150029790; "Nam").
Regarding independent claim 1, Maeda discloses a semiconductor memory device comprising:
a first wiring (Fig. 1: source line SL);
a first memory transistor connected to the first wiring (Fig. 1: MTr8 in sub-block 1);
a first transistor connected between the first wiring and the first memory transistor (Fig. 1: SSTr2 in sub-block 1);
a second memory transistor connected to the first wiring in parallel with the first memory transistor (Fig. 1: Mtr8 in sub-block 2);
a second transistor connected between the first wiring and the second memory transistor (Fig. 1: SSTr2 in sub-block 2);
a second wiring connected to a gate electrode of the first memory transistor (Fig. 1: word line connected to MTr8 in sub-block 1);
a third wiring connected to a gate electrode of the second memory transistor (Fig. 1: word line connected to MTr8 in sub-block 2);
a first gate wiring connected to a gate electrode of the first transistor (Fig. 1: SGS22);
a second gate wiring connected to a gate electrode of the second transistor (Fig. 1: SGS21);
and a control circuit configured to execute an erase operation that selects the first memory transistor or the second memory transistor and erases data (Fig. 1: Row Decoder 2B. See also col. 10, ln. 51-52; "the row decoder 2B has a substantially similar configuration, hence only the row decoder 2A is described"),
wherein the control circuit is configured to be able to control a voltage of the first gate wiring to become larger than a voltage of the second wiring (Fig. 8 where it illustrates the select line for the selected block (first gate wiring) larger than the select line for the word line of the selected block (second wiring) during an erase operation. See also col. 9, ln. 51- ; "Next, the erase operation in the nonvolatile semiconductor device in accordance with the present embodiment is described with reference to FIGS. 6-8". It is noted the erase operation limitations appear to be directed to Fig. 16 of the instant application.),
control a voltage of the second gate wiring to become larger than the voltage of the first gate wiring in the erase operation performed with the first memory transistor selected (Fig. 8 where it illustrates the select line for the unselected block (second gate wiring) larger (Vera') than the select line for the selected block (Vera-ΔV) during an erase operation. It is noted that the voltage generation circuits of Vera' and Vera-ΔV are illustrated in Fig. 9A and indicate that Vera' is necessarily a higher voltage than Vera-ΔV),
Maeda discloses the semiconductor memory device with the structure and the erase operation that selects the first memory transistor and applies the recited voltage relationships to the first and second gate wirings as set forth above, but is silent with respect to controlling a voltage of the third wiring to a floating state in the erase operation.
However, Nam teaches and control a voltage of the third wiring to bring the third wiring into a floating state (Fig. 11. See also para. 6; " The erase method includes supplying an erase voltage to the substrate, supplying a selection word line voltage to word lines connected with a selected sub-block within the memory block, and, after supplying a non-selection word line voltage to word lines connected with an unselected sub-block within the memory block during a first delay time from a point of time when the erase voltage is supplied, floating the word lines connected with the unselected sub-block).
Maeda and Nam are from the same field of endeavor directed to the erasing of memory cells. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Maeda's selective sub-block erase scheme by floating the word lines of the unselected sub-block as taught by Nam. Doing so would improve erase selectivity, reduce disturb, and optimize power consumption in GIDL based erase operations
Regarding claim 2 and 9, Maeda and Nam combined disclose the limitations of claims 1 and 7 respectively,
As applied, Maeda further discloses wherein the control circuit is configured to be able to apply a first voltage to the second gate wiring from a first timing to a second timing after the first timing (Fig. 22A where it illustrates SGS22 (second gate wiring) ramping up from VSS between time t1 and t2 during an erase operation)
and apply a second voltage larger than the first voltage to the second gate wiring from the second timing to a third timing after the second timing in the erase operation performed with the first memory transistor selected (Fig. 22A where it illustrates SGS22 (second gate wiring) ramping up to Vmid (which is larger) between time t2 and t3 during an erase operation with the first memory transistor selected).
Regarding claim 3 and 10, Maeda and Nam combined disclose the limitations of claims 2 and 9 respectively.
As applied, Maeda further discloses wherein the control circuit is configured to be able to apply a voltage smaller than the second voltage to the first gate wiring from the first timing to the third timing (Fig. 28 where it illustrates SGS11' (first gate wiring) ramping to Vmid2 (which is smaller than the second voltage Vmid1) between time t1 and t3. See also col. 15, ln. 44-45; "voltage Vmid2 (<Vmid1)").
Regarding claim 4, Maeda and Nam combined disclose the limitations of claim 2.
As applied, Maeda further discloses wherein the control circuit is configured to be able to apply a third voltage to the first gate wiring and apply a fourth voltage larger than the third voltage to the first wiring at a fourth timing after a third timing (Fig. 28 where it illustrates SGS21 (first gate wiring) ramping to Vera-ΔV (third voltage) and SL (first wiring) ramping to Vera at a fourth timing. It is noted from Fig. 9A that Vera is larger than Vera-ΔV).
Regarding claim 11, Maeda and Nam combined disclose the limitations of claim 9.
As applied, Maeda further discloses wherein the control circuit is configured to be able to apply a
third voltage to the first gate wiring and apply a fourth voltage larger than the third voltage to the first wiring from a fourth timing before the first timing to the first timing (Fig. 28 where it illustrates SGS21 (first gate wiring) ramping to Vera-AV (third voltage) and SL (first wiring) ramping to Vera at a fourth
timing. It is noted from Fig. 9A that Vera is larger than Vera-AV).
Regarding claim 16, Maeda and Nam combined disclose the limitations of claim 1.
As applied, Maeda further discloses wherein the control circuit includes:
a voltage generation circuit configured to be able to generate a plurality of voltage levels (Fig. 17A where it depicts generated Vera, Vera' and Vmid voltages);
a voltage select circuit connected to the voltage generation circuit and selecting the plurality of voltage levels (Fig. 18B 111 circuit which selects from the plurality of the voltages generated by the voltage generation circuit);
a first select transistor and a second select transistor connected in parallel between the voltage select circuit and the first transistor (Fig. 18B: transistors 112a and 112b in parallel which are connected to the voltage select circuit 111 and drive SSGD21 (first transistor));
and a third select transistor and a fourth select transistor connected in parallel between the voltage generation circuit and the second transistor (Fig. 18B: transistors below 112a and 112b which are connected to the voltage select circuit 111 and drive SSGD22 (second transistor)).
Regarding claim 17, Maeda and Nam combined disclose the limitations of claim 16.
As applied, Maeda further discloses wherein in a read operation performed with the first memory transistor selected, the control circuit is configured to be able to set (Fig. 18A where a memory cell in the left MU in SB2 is selected for reading. See also col. 4, ln. 57-60; "The sense amplifier circuit 3 determines data stored in memory cells during a read operation. In addition, the sense amplifier 3 drives bit lines BL and a source line SL in accordance with an address signal supplied from the control circuit AR2." It is noted that in a read operation, for data continuity only 1 memory cell on a given bitline would drive data to the sense amp):
the first select transistor to an ON state; the second select transistor to an OFF state (Fig. 18B 111 circuit. It is noted that the two outputs are mutually exclusive resulting in a first select transistor being on while a second select transistor is off);
the third select transistor to an OFF state; and the fourth select transistor to an OFF state (Fig. 18A where a memory cell in the left MU in SB1 is unselected for reading. It is noted that in a read operation, for data continuity only 1 memory cell on a given bitline would drive data to the sense amp and so an unselected memory cell on the bitline would necessarily have select lines off);
in the read operation performed with the second memory transistor selected, the control circuit is configured to be able to set (Fig. 18A where a memory cell in the left MU in SB1 is selected for reading) the first select transistor to an OFF state; the second select transistor to the OFF state (Fig. 18A where a memory cell in the left MU in SB2 is unselected for reading. It is noted that in a read operation, for data continuity only 1 memory cell on a given bitline would drive data to the sense amp and so an unselected memory cell on the bitline would necessarily have select lines off);
the third select transistor to an ON state; and the fourth select transistor to the OFF state (Fig. 18B 111 circuit. It is noted that the two outputs are mutually exclusive resulting in a first select transistor being on while a second select transistor is off),
and in the erase operation performed with the first memory transistor selected, the control circuit is configured to be able to set (Fig. 18A. See also col. 5, ln. 1-3; "The control circuit AR2 executes", "an erase operation of data in the memory transistors MTr"):
the first select transistor to the ON state; the second select transistor to the OFF state; the third select transistor to the OFF state; and the fourth select transistor to an ON state (Fig. 18A. See also col. 2, ln. 3-6; "semiconductor memory device which", "is also capable of an erase operation to selectively erase only a part of the memory cells in a memory block." It is noted that this combination of select voltages to select transistors 1-4 appear directed to pg. 40-41 of applicant's specification which disclose the application of the various erase voltages for sub-block erase in selected and unselected blocks and which is analogous to Maeda's select transistor voltages for the erase operation depicted in the timing diagram of Fig. 28).
Regarding independent claim 7, Maeda discloses a semiconductor memory device comprising:
a first wiring (Fig. 1: source line SL);
a first voltage supply line (Fig. 9B. where it illustrates the voltage supply lines (VDD, Vera-ΔV, Vera' and Ground. See also col. 10, ln. 49-56; "One example of the row decoder 2A for performing such voltage control is shown in FIG. 9B. This row decoder 2A includes an address determining circuit 111 and a transfer transistor group 112. The address determining circuit 111 turns on a transfer transistor 112a configured to switch supply of the voltage Vera' or Vera-.DELTA.V in the selected block". It is noted that this voltage effectively becomes the select transistor voltage for the erase operation);
a first memory transistor connected between the first wiring and the first voltage supply line (Fig. 1: MTr8 in sub-block 1);
a first transistor connected between the first wiring and the first memory transistor (Fig. 1: SSTr2 in sub-block 1);
a second memory transistor connected between the first wiring and the first voltage supply line in parallel with the first memory transistor (Fig. 1: Mtr8 in sub-block 2);
a second transistor connected between the first wiring and the second memory transistor (Fig. 1: SSTr2 in sub-block 2);
a second wiring connected to a gate electrode of the first memory transistor (Fig. 1: word line connected to MTr8 in sub-block 1);
a third wiring connected to a gate electrode of the second memory transistor (Fig. 1: word line connected to MTr8 in sub-block 2);
a first gate wiring connected to a gate electrode of the first transistor (Fig. 1: SGS22);
a second gate wiring connected to a gate electrode of the second transistor (Fig. 1: SGS21);
and a control circuit configured to be able to execute an erase operation that selects the first memory transistor or the second memory transistor and erases data (Fig. 1: Row Decoder 2B. See also col. 10, ln. 51-52; "the row decoder 2B has a substantially similar configuration, hence only the row decoder 2A is described"),
wherein the control circuit is configured to be able to control a voltage of the second gate wiring to become the same as or larger than a voltage of the first voltage supply line in the erase operation performed with the first memory transistor selected (Fig. 8 where it illustrates the select line for the unselected block (second gate wiring) larger (Vera') than the select line for the selected block (Vera-ΔV) during an erase operation. It is noted that the voltage generation circuits of Vera' and Vera-ΔV are illustrated in Fig. 9A and indicate that Vera' is necessarily a higher voltage than Vera-ΔV. Also, Fig. 9B depicts the route of the first voltage supply line to the select gate).
Maeda discloses the semiconductor memory device with the structure and the erase operation that selects the first memory transistor and applies the recited voltage relationships to the first and second gate wirings as set forth above, but is silent with respect to controlling a voltage of the third wiring to a floating state in the erase operation.
However, Nam teaches and control a voltage of the third wiring to bring the third wiring into a floating state (Fig. 11. See also para. 6; " The erase method includes supplying an erase voltage to the substrate, supplying a selection word line voltage to word lines connected with a selected sub-block within the memory block, and, after supplying a non-selection word line voltage to word lines connected with an unselected sub-block within the memory block during a first delay time from a point of time when the erase voltage is supplied, floating the word lines connected with the unselected sub-block).
Maeda and Nam are from the same field of endeavor directed to the erasing of memory cells. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Maeda's selective sub-block erase scheme by floating the word lines of the unselected sub-block as taught by Nam. Doing so would improve erase selectivity, reduce disturb, and optimize power consumption in GIDL based erase operations
Regarding claim 8, Maeda and Nam combined disclose the limitations of claim 7.
As applied, Maeda further discloses wherein the control circuit is configured to be able to control the voltage of the second gate wiring to become larger than a voltage of the first gate wiring in the erase operation performed with the first memory transistor selected (Fig. 8 where it illustrates the select line for the unselected block (second gate wiring) larger (Vera') than the select line for the selected block (Vera-ΔV) during an erase operation. It is noted that the voltage generation circuits of Vera' and Vera-ΔV are illustrated in Fig. 9A and indicate that Vera' is necessarily a higher voltage than Vera-ΔV).
Regarding claim 14, Maeda and Nam combined disclose the limitations of claim 7.
As applied, Maeda further discloses comprising:
a third transistor connected between the first voltage supply line and the first memory transistor (Fig. 17B: upper transistor 112c which connects between the first voltage supply line and the first memory transistor);
and a third gate wiring connected to a gate electrode of the third transistor (Fig. 17B where it illustrates the line to the gate of transistor 112c),
wherein the control circuit is configured to be able to control a voltage of the third gate wiring to become smaller than a voltage of the first voltage supply line in the erase operation (Fig. 17B where it illustrates that the output of the inverter in circuit 111 which can be ground drives the gate line of transistor 112c. It is noted that the ground voltage is necessarily smaller than the voltages of the voltage supply lines).
Regarding claim 15, Maeda and Nam combined disclose the limitations of claim 14.
As applied, Maeda further discloses comprising:
a fourth transistor connected between the first voltage supply line and the second memory transistor (Fig. 9B. transistor 112b);
and a fourth gate wiring connected to a gate electrode of the fourth transistor (Fig. 9B where it illustrates the wire connected to the gate of transistor 112b),
wherein the control circuit is configured to set the select gate for the second memory transistor in a floating state (col. 10, ln. 63-67; "the voltage of the select gate lines SGD2 and SGS2 rise due to capacitive coupling, thereby causing the transfer transistor 112b to be turned off. As a result, the select gate lines SGD2 and SGS2 attain the floating state.").
Claims 5 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Maeda (US 8537615 – of record), in view of Nam et al. (US 20150029790), and further in view of Seo (US 20210104281- of record).
Regarding claims 5 and 12, Maeda and Nam combined disclose the limitations of claims 1 and 7 respectively.
Madea and Nam are silent with respect to floating the source line.
However, Seo teaches wherein the control circuit is configured to be able to set the first wiring in a floating state in the erase operation (para. 88; "In the second erase operation, the source select lines SSL0 and SSL1 and the source line SL may be controlled to a floating state").
Maeda, Nam and Seo are from the same field of endeavor as applicant’s invention directed to an erase operation on a non-volatile memory array. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the memory array taught by Maeda and Nam with the teachings of Seo’s peripheral circuits to apply GIDL current erase from the drain side. Doing so would speed up the erase operation of the memory device.
Response to Arguments
Applicant's arguments have been fully considered but they are not persuasive. Applicant contends on pg. 15 of Remarks that the anticipation rejection of independent claims 1 and 7 is improper because none of the previously applied references disclose or suggest the newly recited feature of "control a voltage of the third wiring to bring the third wiring into a floating state".
The amendments to claims 1 and 7 do not overcome the rejection under 35 U.S.C. § 103 in view of Maeda and the newly applied reference, Nam.
Applicant's reliance on Fig. 16 of the present specification is not persuasive as it does not distinguish from the prior art combination of Maeda and Nam as set forth above. Accordingly, the rejection of claims 1 and 7 are maintained.
Applicant's subsequent request for reinstatement of dependent claims 6 and 13 based on the allowability of claims 1 and 7 is premature and therefore denied.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to James S. Wells whose telephone number is (703)756-1413. The examiner can normally be reached M-F 8:30-5.
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/James S. Wells/Examiner, Art Unit 2825
/Alfredo Bermudez Lozada/Primary Examiner, Art Unit 2825
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