DETAILED ACTION
This action is responsive to the Response to Restriction filed December 1, 2025. Claims 1-17 are pending. Claims 1, and 7 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
Acknowledgment is made of applicant’s Information Disclosure Statement (IDS) filed on January 19, 2024. This IDS has been considered.
However it is noted that citation No. 1 of the U.S. Patent Application Publications (US 20210017487) section of the IDS lists a publication number which appears to inadvertently contain a minor clerical error as it does not appear to refer to subject matter relevant to applicant’s invention. Based on cross-reference indications supplied in column seven of citation No. 2 of the Foreign Patent Documents section (JP 2021093230) of the IDS, it appears applicant intended to list Hioka et al. (US20210174879).
As such, US 20210017487 has been struck-though on the IDS to reflect that it is not considered. Instead, US 20210174879 (which corresponds to JP 2021093230, foreign patent document citation 2) has been cited on form PTO-892 to reflect its consideration. Applicant is thanked for providing the additional comments on the IDS indicating how the cited foreign and domestic references correspond to each other because it aided the examiner in easily identifying the correction and considering the intended references.
Election/Restrictions
Applicant’s election without traverse of Group II (claims 1-5, 7-12, and 14-17) in the reply filed on December 1, 2025, is acknowledged.
Claims 6, and 13 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: 3D Nonvolatile Memory Device And Method of Erase.
Claim Rejections - 35 USC § 112 – Indefiniteness
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4 and 15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 4, the phrase “from a fourth timing before the first timing to the first timing” is unclear. There is no figure in the drawings or indication in the specification of the instant application which disclose a fourth timing point being prior in time to anything considered a first timing point. Additionally, the repetition of the term “first timing” in the claim element does not make evident which path is being described on the timing chart.
For purposes of compact prosecution, the phrase “from a fourth timing before the first timing to the first timing” will be interpreted to mean “at a fourth timing after a third timing” (See MPEP 2173.06).
Regarding claim 15, the phrase “the control circuit is configured to be able to set the fourth gate wiring in a floating state” is unclear because the fourth gate wiring is recited to the gate of the fourth transistor which according to another element in the claim is also apparently connected between the second memory transistor and the first voltage supply line. This component appears to possibly be directed to the transistors depicted in select circuits 24 and/or 23 of Fig. 5, which are driven by address decoder 22. However, there is no indication within the disclosure of the signals driven from the address decoder to the select circuits which float.
For purposes of compact prosecution, the phrase “to set the select gate for the second memory transistor in a floating state” (See MPEP 2173.06).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 7-11, and 14-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Maeda (US 8537615).
Regarding independent claim 1, Maeda discloses a semiconductor memory device comprising:
a first wiring (Fig. 1: source line SL);
a first memory transistor connected to the first wiring (Fig. 1: MTr8 in sub-block 1);
a first transistor connected between the first wiring and the first memory transistor (Fig. 1: SSTr2 in sub-block 1);
a second memory transistor connected to the first wiring in parallel with the first memory transistor (Fig. 1: Mtr8 in sub-block 2);
a second transistor connected between the first wiring and the second memory transistor (Fig. 1: SSTr2 in sub-block 2);
a second wiring connected to a gate electrode of the first memory transistor (Fig. 1: word line connected to MTr8 in sub-block 1);
a third wiring connected to a gate electrode of the second memory transistor (Fig. 1: word line connected to MTr8 in sub-block 2);
a first gate wiring connected to a gate electrode of the first transistor (Fig. 1: SGS22);
a second gate wiring connected to a gate electrode of the second transistor (Fig. 1: SGS21);
and a control circuit configured to be able to execute an erase operation that selects the first memory transistor or the second memory transistor and erases data (Fig. 1: Row Decoder 2B. See also col. 10, ln. 51-52; "the row decoder 2B has a substantially similar configuration, hence only the row decoder 2A is described"),
wherein the control circuit is configured to be able to control a voltage of the first gate wiring to become larger than a voltage of the second wiring (Fig. 8 where it illustrates the select line for the selected block (first gate wiring) larger than the select line for the word line of the selected block (second wiring) during an erase operation. See also col. 9, ln. 51- ; "Next, the erase operation in the nonvolatile semiconductor device in accordance with the present embodiment is described with reference to FIGS. 6-8". It is noted the erase operation limitations appear to be directed to Fig. 16 of the instant application.)
and control a voltage of the second gate wiring to become larger than the voltage of the first gate wiring in the erase operation performed with the first memory transistor selected (Fig. 8 where it illustrates the select line for the unselected block (second gate wiring) larger (Vera') than the select line for the selected block (Vera-ΔV) during an erase operation. It is noted that the voltage generation circuits of Vera' and Vera-ΔV are illustrated in Fig. 9A and indicate that Vera' is necessarily a higher voltage than Vera-ΔV).
Regarding claim 2 and 9, Maeda discloses the limitations of claims 1 and 7 respectively,
As applied, Maeda further discloses wherein the control circuit is configured to be able to apply a first voltage to the second gate wiring from a first timing to a second timing after the first timing (Fig. 22A where it illustrates SGS22 (second gate wiring) ramping up from VSS between time t1 and t2 during an erase operation)
and apply a second voltage larger than the first voltage to the second gate wiring from the second timing to a third timing after the second timing in the erase operation performed with the first memory transistor selected (Fig. 22A where it illustrates SGS22 (second gate wiring) ramping up to Vmid (which is larger) between time t2 and t3 during an erase operation with the first memory transistor selected).
Regarding claim 3 and 10, Maeda discloses the limitations of claims 2 and 9 respectively,
As applied, Maeda further discloses wherein the control circuit is configured to be able to apply a voltage smaller than the second voltage to the first gate wiring from the first timing to the third timing (Fig. 28 where it illustrates SGS11' (first gate wiring) ramping to Vmid2 (which is smaller than the second voltage Vmid1) between time t1 and t3. See also col. 15, ln. 44-45; "voltage Vmid2 (<Vmid1)").
Regarding claim 4 and 11, Maeda discloses the limitations of claims 2 and 9 respectively,
As applied, Maeda further discloses wherein the control circuit is configured to be able to apply a third voltage to the first gate wiring and apply a fourth voltage larger than the third voltage to the first wiring from a fourth timing before the first timing to the first timing (Fig. 28 where it illustrates SGS21 (first gate wiring) ramping to Vera-ΔV (third voltage) and SL (first wiring) ramping to Vera at a fourth timing. It is noted from Fig. 9A that Vera is larger than Vera-ΔV).
Regarding claim 16, Maeda discloses the limitations of claim 1.
As applied, Maeda further discloses wherein the control circuit includes:
a voltage generation circuit configured to be able to generate a plurality of voltage levels (Fig. 17A where it depicts generated Vera, Vera' and Vmid voltages);
a voltage select circuit connected to the voltage generation circuit and selecting the plurality of voltage levels (Fig. 18B 111 circuit which selects from the plurality of the voltages generated by the voltage generation circuit);
a first select transistor and a second select transistor connected in parallel between the voltage select circuit and the first transistor (Fig. 18B: transistors 112a and 112b in parallel which are connected to the voltage select circuit 111 and drive SSGD21 (first transistor));
and a third select transistor and a fourth select transistor connected in parallel between the voltage generation circuit and the second transistor (Fig. 18B: transistors below 112a and 112b which are connected to the voltage select circuit 111 and drive SSGD22 (second transistor)).
Regarding claim 17, Maeda discloses the limitations of claim 16.
As applied, Maeda further discloses wherein in a read operation performed with the first memory transistor selected, the control circuit is configured to be able to set (Fig. 18A where a memory cell in the left MU in SB2 is selected for reading. See also col. 4, ln. 57-60; "The sense amplifier circuit 3 determines data stored in memory cells during a read operation. In addition, the sense amplifier 3 drives bit lines BL and a source line SL in accordance with an address signal supplied from the control circuit AR2." It is noted that in a read operation, for data continuity only 1 memory cell on a given bitline would drive data to the sense amp):
the first select transistor to an ON state; the second select transistor to an OFF state (Fig. 18B 111 circuit. It is noted that the two outputs are mutually exclusive resulting in a first select transistor being on while a second select transistor is off);
the third select transistor to an OFF state; and the fourth select transistor to an OFF state (Fig. 18A where a memory cell in the left MU in SB1 is unselected for reading. It is noted that in a read operation, for data continuity only 1 memory cell on a given bitline would drive data to the sense amp and so an unselected memory cell on the bitline would necessarily have select lines off);
in the read operation performed with the second memory transistor selected, the control circuit is configured to be able to set (Fig. 18A where a memory cell in the left MU in SB1 is selected for reading) the first select transistor to an OFF state; the second select transistor to the OFF state (Fig. 18A where a memory cell in the left MU in SB2 is unselected for reading. It is noted that in a read operation, for data continuity only 1 memory cell on a given bitline would drive data to the sense amp and so an unselected memory cell on the bitline would necessarily have select lines off);
the third select transistor to an ON state; and the fourth select transistor to the OFF state (Fig. 18B 111 circuit. It is noted that the two outputs are mutually exclusive resulting in a first select transistor being on while a second select transistor is off),
and in the erase operation performed with the first memory transistor selected, the control circuit is configured to be able to set (Fig. 18A. See also col. 5, ln. 1-3; "The control circuit AR2 executes", "an erase operation of data in the memory transistors MTr"):
the first select transistor to the ON state; the second select transistor to the OFF state; the third select transistor to the OFF state; and the fourth select transistor to an ON state (Fig. 18A. See also col. 2, ln. 3-6; "semiconductor memory device which", "is also capable of an erase operation to selectively erase only a part of the memory cells in a memory block." It is noted that this combination of select voltages to select transistors 1-4 appear directed to pg. 40-41 of applicant's specification which disclose the application of the various erase voltages for sub-block erase in selected and unselected blocks and which is analogous to Maeda's select transistor voltages for the erase operation depicted in the timing diagram of Fig. 28).
Regarding independent claim 7, Maeda discloses a semiconductor memory device comprising:
a first wiring (Fig. 1: source line SL);
a first voltage supply line (Fig. 9B. where it illustrates the voltage supply lines (VDD, Vera-ΔV, Vera' and Ground. See also col. 10, ln. 49-56; "One example of the row decoder 2A for performing such voltage control is shown in FIG. 9B. This row decoder 2A includes an address determining circuit 111 and a transfer transistor group 112. The address determining circuit 111 turns on a transfer transistor 112a configured to switch supply of the voltage Vera' or Vera-.DELTA.V in the selected block". It is noted that this voltage effectively becomes the select transistor voltage for the erase operation);
a first memory transistor connected between the first wiring and the first voltage supply line (Fig. 1: MTr8 in sub-block 1);
a first transistor connected between the first wiring and the first memory transistor (Fig. 1: SSTr2 in sub-block 1);
a second memory transistor connected between the first wiring and the first voltage supply line in parallel with the first memory transistor (Fig. 1: Mtr8 in sub-block 2);
a second transistor connected between the first wiring and the second memory transistor (Fig. 1: SSTr2 in sub-block 2);
a first gate wiring connected to a gate electrode of the first transistor (Fig. 1: SGS22);
a second gate wiring connected to a gate electrode of the second transistor (Fig. 1: SGS21);
and a control circuit configured to be able to execute an erase operation that selects the first memory transistor or the second memory transistor and erases data (Fig. 1: Row Decoder 2B. See also col. 10, ln. 51-52; "the row decoder 2B has a substantially similar configuration, hence only the row decoder 2A is described"),
wherein the control circuit is configured to be able to control a voltage of the second gate wiring to become the same as or larger than a voltage of the first voltage supply line in the erase operation performed with the first memory transistor selected (Fig. 8 where it illustrates the select line for the unselected block (second gate wiring) larger (Vera') than the select line for the selected block (Vera-ΔV) during an erase operation. It is noted that the voltage generation circuits of Vera' and Vera-ΔV are illustrated in Fig. 9A and indicate that Vera' is necessarily a higher voltage than Vera-ΔV. Also, Fig. 9B depicts the route of the first voltage supply line to the select gate).
Regarding claim 8, Maeda discloses the limitations of claim 7.
As applied, Maeda further discloses wherein the control circuit is configured to be able to control the voltage of the second gate wiring to become larger than a voltage of the first gate wiring in the erase operation performed with the first memory transistor selected (Fig. 8 where it illustrates the select line for the unselected block (second gate wiring) larger (Vera') than the select line for the selected block (Vera-ΔV) during an erase operation. It is noted that the voltage generation circuits of Vera' and Vera-ΔV are illustrated in Fig. 9A and indicate that Vera' is necessarily a higher voltage than Vera-ΔV).
Regarding claim 14, Maeda discloses the limitations of claim 7.
As applied, Maeda further discloses comprising:
a third transistor connected between the first voltage supply line and the first memory transistor (Fig. 17B: upper transistor 112c which connects between the first voltage supply line and the first memory transistor);
and a third gate wiring connected to a gate electrode of the third transistor (Fig. 17B where it illustrates the line to the gate of transistor 112c),
wherein the control circuit is configured to be able to control a voltage of the third gate wiring to become smaller than a voltage of the first voltage supply line in the erase operation (Fig. 17B where it illustrates that the output of the inverter in circuit 111 which can be ground drives the gate line of transistor 112c. It is noted that the ground voltage is necessarily smaller than the voltages of the voltage supply lines).
Regarding claim 15, Maeda discloses the limitations of claim 14.
As applied, Maeda further discloses comprising:
a fourth transistor connected between the first voltage supply line and the second memory transistor (Fig. 9B. transistor 112b);
and a fourth gate wiring connected to a gate electrode of the fourth transistor (Fig. 9B where it illustrates the wire connected to the gate of transistor 112b),
wherein the control circuit is configured to be able to set the fourth gate wiring in a floating state in the erase operation (col. 10, ln. 63-67; "the voltage of the select gate lines SGD2 and SGS2 rise due to capacitive coupling, thereby causing the transfer transistor 112b to be turned off. As a result, the select gate lines SGD2 and SGS2 attain the floating state." As noted in the indefiniteness rejection above, this limitation is interpreted to mean "the select gate for the second memory transistor is in a floating state").
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Maeda (US 8537615) in view of Seo (US 20210104281).
Regarding claims 5 and 12, Maeda discloses the limitations of claims 1 and 7 respectively.
Madea is silent with respect to floating the source line.
However, Seo teaches wherein the control circuit is configured to be able to set the first wiring in a floating state in the erase operation (para. 88; "In the second erase operation, the source select lines SSL0 and SSL1 and the source line SL may be controlled to a floating state").
Maeda and Seo are from the same field of endeavor as applicant’s invention directed to an erase operation on a non-volatile memory array. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Maeda’s memory array with the teachings of Seo’s peripheral circuits to apply GIDL current erase from the drain side. Doing so would speed up the erase operation of the memory device.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Sakaguchi et al. (US 20200286564) - Similar structure as fig 5 and similar element nomenclature.
Lee et al. (US 20210165603) - Floating select lines during erase.
Hioka et al. (US 20210174879) – 3D NVM with similar SU & BLK organization as well as elements of physical structure (US version of JP from IDS)
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/James S. Wells/Examiner, Art Unit 2825
/ALEXANDER SOFOCLEOUS/Supervisory Patent Examiner, Art Unit 2825