Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant’s election without traverse of Invention 1 in the reply filed on 6/29/2026 is acknowledged.
Claims 17-20 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on6/29/2026.
Claims 6, 12 and 13 withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected species, there being no allowable generic or linking claim. Applicant timely traversed the election requirement in the reply filed on 6/29/2026.
Applicant's election with traverse of Species 1 in the reply filed on 6/29/2026 is acknowledged. The traversal is on the grounds that Examiner has not found established a serious search or examination burden because the species would be classified in the same class/subclass. This is not found persuasive because a search directed to one method of integration , i.e. face to face, would be unlikely to yield results reading on another method of integration, i.e. face to back. .
The requirement is still deemed proper and is therefore made FINAL.
Examiner notes that applicant stated that claim 6 did not read on the elected species. Examiner has also noted that claims 12 and 13 do not read on the elected species because:
In claim 12 the active frontsides of the first logic chiplet, the bridging chiplet and the auxiliary chiplet are all facing the first direction, while per paras. 32-33 of the application the active frontsides of the logic chiplets should be facing a different direction from the bridging chiplet.
In claim 13 the active frontsides of the first logic chiplet and the memory chiplet face the same direction while per paras. 32-33 of the application the active frontsides of the logic chiplets should be facing a different direction from the memory chiplet.
Objections
Claim 7 objected to because of the following informalities:
Claim 7 recites “the multi-chiplet assembly of claim 1 further comprising at least one memory chiplet.” In claim 1, there is already a memory chiplet.
For examination purposes this is being interpreted to read “the multi-chiplet assembly of claim 1 further comprising at least one additional memory chiplet.”
Appropriate correction is required.
Claim Rejections 35 U.S.C. § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 7 and 8is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Lee et al. (US 20210043557), hereinafter referred to as Lee
Regarding claim 1, Lee teaches a multi-chiplet assembly comprising: a first logic chiplet (Lee, 399-1, Fig. 32, para. 461); a memory chiplet (Lee, 159, Fig. 32, para, 456, Fig. 32 shows two instances of 159, this refers to the one stacked beneath 399-1, additionally, 159 is a memory module containing multiple instances of memory chip 251-see Lee, Fig. 19A, para. 313) electrically coupled to the first logic chiplet; a second logic chiplet (Lee, 399-2, Fig. 32, para. 461); and a bridging chiplet (Lee, 690, Fig. 32, para. 458) electrically coupling the first logic chiplet to the second logic chiplet.
Regarding claim 2, Lee teaches the multi-chiplet assembly of claim 1 further comprising an additional memory chiplet (Lee, 159, Fig. 32, para, 456, Fig. 32 shows two instances of 159, this refers to the one stacked beneath 399-2).
Regarding claim 3, Lee teaches the multi-chiplet assembly of claim 2 further comprising: a first sub-package (Lee, 565-1, Fig. 32, para. 464, the sub assembly is not explicitly shown, but 399-1 and 399-2 are bonded into the same layer using polymer layer 565-1) comprising the first logic chiplet and the second logic chiplet; and a second sub-package (Lee, 565-2, Fig. 32, para. 459, the sub assembly is not explicitly shown, but 690 and both instances of 159 are bonded into the same layer using polymer layer 565-2) comprising the memory chiplet, the additional memory chiplet, and the bridging chiplet.
Regarding claim 4, Lee teaches the multi-chiplet assembly of claim 3, wherein: the first logic chiplet comprises an active frontside having first active circuitry (Lee, 399-1, Fig. 32, para. 472); the second logic chiplet comprises an active frontside having second active circuitry (Lee, 399-2, Fig. 32, para. 472); the memory chiplet comprises an active frontside having third active circuitry (Lee, 159, Fig. 32, para. 46); the additional memory chiplet comprises an active frontside having fourth active circuitry (Lee, para. 460); the active frontside of the first logic chiplet and the active frontside of the second logic chiplet face a first direction (Lee, Fig. 32, see diagram below); and the active frontside of the memory chiplet and the active frontside of the additional memory chiplet face a second direction opposite the first direction (Lee, Fig. 32, see diagram below).
Regarding claim 5, Lee teaches the multi-chiplet assembly of claim 4, wherein: the bridging chiplet comprises an active frontside having fifth active circuitry (Lee, 690, Fig. 2, para. 461); and the active frontside of the bridging chiplet faces the second direction opposite the first direction (Lee, Fig. 32, see diagram below).
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Regarding claim 7, Lee teaches the multi-chiplet assembly of claim 1 further comprising at least one additional memory chiplet (Lee, 159, Fig. 32, 159 is a memory module containing multiple instances of memory chip 251-see Lee, Fig. 19A, para. 313), wherein the first logic chiplet, the memory chiplet, and the memory chiplet are stacked (Lee, Fig. 32, instances of 251 are stacked inside 159 and 399-1 is stacked above 159).
Regarding claim 8, Lee teaches the multi-chiplet assembly of claim 1 further comprising at least one additional memory chiplet (Lee, 159, Fig. 32, 159 is a memory module containing multiple instances of memory chip 251-see Lee, Fig. 19A, para. 313), wherein the first logic chiplet, the memory chiplet, the bridging chiplet, and the at least one additional memory chiplet are stacked (Lee, Fig. 32, the memory chiplets are stacked inside 159, and 399-1 is stacked on top of them and the bridging chiplet 690).
. Claim Rejections 35 U.S.C. § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 9-11 and 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Lee.
Regarding claim 9, Lee teaches the multi-chiplet assembly of claim 2. Lee, in another embodiment, teaches an auxiliary chiplet (Lee, 411, Fig. 33, paras. 261, 476) electrically coupled to logic chiplet (Lee, 399, Fig. 33, para. 476).
Therefore it would have been obvious to one having ordinary skill in the art before the filing date of the invention to combine the auxiliary chip of Fig. 33 with the embodiment of Fig. 33 in order to provide the configuration of Fig. 32 with a voltage regulation capability (Lee, para. 261) or cryptographic capabilities (Lee, para. 484).
Regarding claim 10, Lee teaches the multi-chiplet assembly of claim 9, wherein the auxiliary chiplet comprises one of: an integrated voltage regulator; and a deep trench capacitor (Lee 411, Fig. 33, detailed in Fig. 13, contains a voltage regulating block 415, para. 261).
Regarding claim 11, Lee teaches the multi-chiplet assembly of claim 9, wherein: the first logic chiplet comprises: an active frontside having first active circuitry; and through-silicon vias (Lee, 399-1, Fig. 32, para. 472); the memory chiplet comprises an active frontside having second active circuitry( Lee, 159, Fig. 32, para. 46); the bridging chiplet comprises an active frontside having third active circuitry (Lee, 690, Fig. 2, para. 461); and the auxiliary chiplet comprises an active frontside having fourth active circuitry (Lee, 411, Fig. 33, para. 261).
Regarding claim 14, Lee teaches the multi-chiplet assembly of claim 9, wherein the auxiliary chiplet (Lee, 411, Fig. 33) and the bridging chiplet (Lee, 690, Fig. 32) are directly bonded to the first logic chiplet.
Regarding claim 15, Lee teaches the multi-chiplet assembly of claim 9 but does not explicitly teach wherein it further comprises: a first sub-package comprising the auxiliary chiplet and the bridging chiplet; a second sub-package comprising the first logic chiplet and the second logic chiplet; and a third sub-package comprising the memory chiplet.
However, Lee does teach that the Fine-line interconnection bridge (Lee, 690, Fig. 32) is used for “high speed, high density interconnection” between neighboring logic chips (Lee, para. [0025]). To maintain signal integrity and low latency, the bridge must be immediately adjacent to the logic chips.
Additionally, in Fig. 33 Lee teaches where the auxiliary chip shares a layer with two memory chiplets. Lee teaches that the Auxiliary Supporting (AS) chip (Lee, 411, Fig. 3) includes a “regulating block (Lee, Fig. 3)415 configured to regulate a voltage of power supply… to be delivered to the logic integrated-circuit (IC) chip” (Lee, para. [0284]). To minimize Power Delivery Network (PDN) impedance (IR drop), the voltage regulator must also be positioned as close to the logic chips as possible.
Therefore a person of ordinary skill in the art would be motivated to place the auxiliary chiplet and the Fine-Line Interconnection Bridge on the same sub-package as the auxiliary chiplet to simultaneously optimize the high speed signal routing and low-impedance power.
Lee discusses the need for thermal management in these dense 3D packages, explicitly teaching the use of heat dissipaters, thermoelectric (TE) coolers (Lee, 633, Fig. 32, para. 307), and heat sinks (Lee, 316, Fig. 26I, para. 349) to pull heat away from the logic chips (Lee, paras. 20, 349). Because the auxiliary chip (voltage regulator) and logic chips generate significant heat, a POSITA would be motivated to physically separate the thermally sensitive memory chiplet into a third sub-package. Moving the memory out of the bridge/auxiliary layer and into its own sub-package provides necessary thermal isolation, preventing the memory from being degraded by the heat of the voltage regulator and logic cores.
Regarding claim 16, Lee teaches the multi-chiplet assembly of claim 9 further comprising: a first sub-package comprising the memory chiplet and the bridging chiplet (Lee, 565-2, Fig. 32, para. 459, the sub assembly is not explicitly shown, but 690 and both instances of 159 are bonded into the same layer using polymer layer 565-2); a second sub-package comprising the first logic chiplet and the second logic chiplet (Lee, 565-1, Fig. 32, para. 464, the sub assembly is not explicitly shown, but 399-1 and 399-2 are bonded into the same layer using polymer layer 565-1); and a third sub-package comprising the auxiliary chiplet. Lee, Fig 32 does not show the auxiliary chiplet, however, it does show a thermoelectric cooler configured to attach to the backside of the logic circuits, this shows that a third sub-package can be added to the configuration of Lee Fig. 32. Additionally, in Fig. 33 the auxiliary chip 411 is positioned between the memory chips 159, but in 32 that is the location of the bridging chiplet. Therefore it would have been obvious to one having ordinary skill in the art before the filing date of the invention to further modify the configuration of Lee Fig. 32 by placing the auxiliary chip 411 on the backside of the logic chiplets in order to provide the configuration of Fig. 32 with a voltage regulation capability (Lee, para. 261) or cryptographic capabilities (Lee, para. 484).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Choi et al. (US 20240119996) teaches a memory package which has two pairs of logic chiplets and memory chiplets stacked over a substrate.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIERAN M CUNNINGHAM whose telephone number is (571)272-9654. The examiner can normally be reached Mon-Fri 8:30-5:30.
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/KIERAN M. CUNNINGHAM/Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893
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