DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s amendment to the claims, filed on August 22, 2021, is acknowledged. Entry of amendment is accepted and made of record.
Response to Arguments/Remarks
Applicant’s arguments/remarks, see pgs. 5-7, with respect to the immediate allowance of the current application have been fully considered but are not persuasive.
The Examiner notes that a new combination of prior art is presented in light of the amendments, such that arguments directed solely to the previously presented combination of prior art are now moot.
Note by the Examiner
For clarity, references to specific claim numbers are presented in bold. Cited claim limitations are presented in bold the first time they are associated with a particular prior art disclosing the cited limitations, and subsequent reference to the already disclosed claim limitations are presented un-bolded. Certain elements from prior art which are not required by the claims are also presented bolded if they are particularly pertinent to understanding how the references are being combined. Item-to-item matching and examiner explanations for 102 and/or 103 rejections are provided in parenthesis.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1 is rejected under 35 U.S.C. 103 as obvious over Yu et al. (US 20130037950 A1), hereinafter referred to as “Yu”, in view of Beroz et al. (US 2004/0238857 A1), hereinafter as B1
PNG
media_image1.png
476
1188
media_image1.png
Greyscale
Yu discloses an interposer (see Yu fig. 2; see [0021] and note that the device shown in fig. 2 is similar to the device shown in fig. 1 except for encapsulation layer 109) having a first surface (see Yu fig. 2) as a mounting surface, and a second surface (see Yu fig. 2) where an object (see annotated Yu fig. 2 above) is to be mounted, the second surface being opposite to the first surface, the interposer comprising:
a first component (Yu fig. 2, Chip 3; see [0015]) included in the interposer and connected to the first surface via a conductor (Yu fig. 1, 116; see [0018]: TAVs 116 electrically connect Chip 3 with solder balls 110 at the first surface (via RDL 114 and UBM structures 112)), the first component having a first surface side closer to the first surface and a second surface side closer to the second surface (see labeled “Yu. fig. 2” above);
a second component (Yu fig. 2, Chip 2; see [0015]) arranged to overlap the first component on a second surface side of the first component, and the second component being in contact with the first component (see Yu fig. 2 and [0013]), included in the interposer, and connected to the second surface via a conductor (Yu fig. 1, 122; see [0018]: metal bumps 122 electrically connect Chip 2 with RDL 126 at the second surface); and
a sealing resin layer (Yu fig. 2, 106; see [0016] and [0029]: material layer 106 is similar to material layer 108 (through a similar formation process); see [0023]: material layer 108 is formed of photo-sensitive epoxy (i.e. a resin) or non photo-sensitive molding compounds) sealing the first component and the second component (see Yu [0017]).
Yu does not disclose a third component arranged to overlap the first component on the second surface side of the first component and being in contact with the first component, included in the interposer, and having an electrode directly exposed on the second surface or connected to the second surface via a conductor; the sealing resin layer sealing the third component, wherein the second component and the third component are spaced apart from each other.
PNG
media_image2.png
402
1050
media_image2.png
Greyscale
B1 discloses (see “Labeled Fig. 29”) a third component (labeled element “third component, right element 2414, see [0123] “active chips 2414”) arranged to overlap the first component (labeled element “first component”, element 2415, see [0123] “passive chip 2415”) on the second surface side of the first component and being in contact with the first component, included in the interposer (see “Labeled Fig. 29” above); the sealing resin layer (element 100, see Fig. 8 for the labeling of the element, and [0071] “encapsulant mass 100” and [0069] “encapsulated by overmolding with a protective resin as, for example, an epoxy, polyimide or other dielectric composition”) sealing the third component, wherein the second component and the third component are spaced apart from each other (see “Labeled Fig. 29” above).
The third component and surrounding resin material as taught by B1 is incorporated as a third component and surrounding resin material of Yu (see Yu fig. 2 above, an identical element “Chip 2” is provided adjacent in the same manner as B1 having two elements 2414), wherein the combination further discloses having an electrode directly exposed on the second surface or connected to the second surface via a conductor (see Yu identical duplicate connection for the third component as the second component [0018]: metal bumps 122 electrically connect Chip 2 with RDL 126 at the second surface).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of B1 with Yu because the combination allows for a plurality of chips to be connected in a multi-layer substrate-type carrier (see B1 Fig. 29 and [0123]); and
the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known number of chips for another for which the alternatives are provided as selectable options in a similar device to obtain predictable results (see B1 at least Fig. 15-18, 32 showing single stacked chips versus Fig. 29-30 showing two adjacent chips in the stacked chips).
Claims 2-7 and 9-20 are rejected under 35 U.S.C. 103 as being unpatentable over Yu, in view of Beroz et al. (US 2004/0238857 A1), hereinafter as B1, in view of Elsherbini et al. (US 20200273839 A1), hereinafter referred to as “Elsherbini”;
[Sugioka et al. (US 20200335504 A1), hereinafter referred to as “Sugioka”, is utilized herein as evidence].
PNG
media_image3.png
476
1168
media_image3.png
Greyscale
PNG
media_image4.png
465
778
media_image4.png
Greyscale
Regarding claim 2, the previously combined device of Yu and B1 disclose the interposer according to claim 1, wherein in the first surface (see Yu fig. 2), a 1st unlabeled layer (see Yu figs. 1-2; the 1st unlabeled layer is included with RDL 114) is arranged so as to cover the sealing resin layer (see Yu fig. 2), and a first-surface-side wiring layer (Yu fig. 1, 114; see [0018]) is arranged between the 1st unlabeled layer and the sealing resin layer, and electrical connection from the first component (Yu fig. 2, Chip 3) to the first surface is made via the first-surface-side wiring layer (see Yu [0018]).
The previously-combined device fails to explicitly disclose first-surface-side outer resin layer.
Elsherbini discloses a first-surface-side outer resin layer (Elsherbini fig. 21, 102; see [0034]) being arranged so as to cover a sealing resin layer (Elsherbini fig. 21, 132) on a first surface (see Elsherbini fig. 21) of an interposer (Elsherbini fig. 21: 148, 151, 153).
The first-surface-side outer resin layer of Elsherbini is incorporated as the 1st unlabeled layer in the previously combined device wherein the combination discloses a first-surface-side outer resin layer.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the previously-combined device with the first-surface-side outer resin layer of Elsherbini to further insulate the components included in the interposer (see Elsherbini [0034]);
and the combination is a simple substitution of one known element for another to obtain predictable results – simple substitution of the 1st unlabeled layer of the previously-combined device (see Yu fig. 2) with the first-surface-side outer resin layer of Elsherbini (Elsherbini fig. 21, 102) to obtain predicable results (the use of resin to encapsulate wiring layers and the associated benefits are well known in the art).
PNG
media_image3.png
476
1168
media_image3.png
Greyscale
Regarding claim 3, the previously combined device of Yu, B1, Elsherbini disclose the interposer according to claim 1, wherein in the second surface (see Yu fig. 2), a 2nd unlabeled layer (see Yu figs. 1-2; the 2nd unlabeled layer is included with RDL 126) is arranged so as to cover the sealing resin layer (see Yu fig. 2, 106), and a second-surface-side wiring layer (Yu fig. 1, 126; see [0018]) is arranged between the 2nd unlabeled layer and the sealing resin layer,
and electrical connection from the second component (Yu fig. 2, Chip 2) to the first surface is made via the second-surface-side wiring layer (see Yu [0018]).
The previously-combined device fails to explicitly disclose a second-surface-side outer resin layer.
Elsherbini discloses a second-surface-side outer resin layer (Elsherbini fig. 21, 148; see [0105]: package substrate portion 148 is formed in a similar manner as package substrate portion 115 of fig. 19G; see [0089]: package substrate portion 115 and 113 together form package substrate 102; therefore, the material of package substrate portion 148 is the same as the material of package substrate 102 (i.e. resin according to [0034])) being arranged so as to cover a sealing resin layer (Elsherbini fig. 21, 132) on a second surface (see Elsherbini fig. 21) of an interposer (Elsherbini fig. 21: 148, 151, 153).
The second-surface-side outer resin layer of Elsherbini is incorporated as the 2nd unlabeled layer in the previously combined device wherein the combination discloses a second-surface-side outer resin layer.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the previously-combined device with the second-surface-side outer resin layer of Elsherbini to further insulate the components included in the interposer (see Elsherbini [0034]);
and the combination is a simple substitution of one known element for another to obtain predictable results – simple substitution of the 2nd unlabeled layer of the previously-combined device (see Yu fig. 2) with the second-surface-side outer resin layer of Elsherbini (Elsherbini fig. 21, 148) to obtain predicable results (the use of resin to encapsulate wiring layers and the associated predictable benefits are well known in the art).
Regarding claim 4, Yu, B1, Elsherbini disclose the interposer according to claim 1, wherein the first component (Yu fig. 2, Chip 3) is an IC (see Yu [0015]).
Regarding claim 5, Yu, B1, Elsherbini disclose the interposer according to claim 1, wherein the second component (Yu fig. 2, Chip 2) is a capacitor (see Yu [0015]: Chip 2 comprises a plurality of DRAM memory circuits; see evidentiary reference Sugioka [0003] which teaches that DRAM memory cells each include a capacitor; therefore, the teachings of Yu in light of evidentiary reference Sugioka disclose that the second component includes a capacitor).
Regarding claim 6, Yu, B1, Elsherbini disclose the interposer according to claim 1, wherein the second component (Yu fig. 2, Chip 2) is an IC (see Yu [0015]).
Regarding claim 7, Yu, B1, Elsherbini disclose the interposer according to claim 1, wherein the object (see Yu fig. 2) is a coreless substrate (the package layer including Chip 1 and encapsulation layer 109 is a coreless substrate (since it has no rigid core)).
PNG
media_image3.png
476
1168
media_image3.png
Greyscale
Regarding claim 9, the previously combined device of Yu, B1, Elsherbini discloses the interposer according to claim 2, wherein in the second surface (see Yu fig. 2), a 2nd unlabeled layer (see Yu figs. 1-2; the 2nd unlabeled layer is included with RDL 126) is arranged so as to cover the sealing resin layer (see Yu fig. 2, 106), and a second-surface-side wiring layer (Yu fig. 1, 126; see [0018]) is arranged between the 2nd unlabeled layer and the sealing resin layer,
and electrical connection from the second component (Yu fig. 2, Chip 2) to the second surface is made via the second-surface-side wiring layer (see Yu [0018]).
The previously-combined device fails to explicitly disclose a second-surface-side outer resin layer.
Elsherbini discloses a second-surface-side outer resin layer (Elsherbini fig. 21, 148; see [0105]: package substrate portion 148 is formed in a similar manner as package substrate portion 115 of fig. 19G; see [0089]: package substrate portion 115 and 113 together form package substrate 102; therefore, the material of package substrate portion 148 is the same as the material of package substrate 102 (i.e. resin according to [0034])) being arranged so as to cover a sealing resin layer (Elsherbini fig. 21, 132) on a second surface (see Elsherbini fig. 21) of an interposer (Elsherbini fig. 21: 148, 151, 153).
The second-surface-side outer resin layer of Elsherbini is incorporated as the 2nd unlabeled layer in the previously combined device wherein the combination discloses a second-surface-side outer resin layer.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the previously-combined device with the second-surface-side outer resin layer of Elsherbini to further insulate the components included in the interposer (see Elsherbini [0034]);
and the combination is a simple substitution of one known element for another to obtain predictable results – simple substitution of the 2nd unlabeled layer of the previously-combined device (see Yu fig. 2) with the second-surface-side outer resin layer of Elsherbini (Elsherbini fig. 21, 148) to obtain predicable results (the use of resin to encapsulate wiring layers and the associated predictable benefits are well known in the art).
Regarding claim 10, Yu, B1, Elsherbini disclose the interposer according to claim 2, wherein the first component (Yu fig. 2, Chip 3) is an IC (see Yu [0015]).
Regarding claim 11, Yu, B1, Elsherbini disclose the interposer according to claim 3, wherein the first component (Yu fig. 2, Chip 3) is an IC (see Yu [0015]).
Regarding claim 12, Yu, B1, Elsherbini disclose the interposer according to claim 2, wherein the second component (Yu fig. 2, Chip 2) is a capacitor (see Yu [0015]: Chip 2 comprises a plurality of DRAM memory circuits; see evidentiary reference Sugioka [0003] which teaches that DRAM memory cells each include a capacitor; therefore, the teachings of Yu in light of evidentiary reference Sugioka disclose that the second component includes a capacitor).
Regarding claim 13, Yu, B1, Elsherbini disclose the interposer according to claim 3, wherein the second component (Yu fig. 2, Chip 2) is a capacitor (see Yu [0015]: Chip 2 comprises a plurality of DRAM memory circuits; see evidentiary reference Sugioka [0003] which teaches that DRAM memory cells each include a capacitor; therefore, the teachings of Yu in light of evidentiary reference Sugioka disclose that the second component includes a capacitor).
Regarding claim 14, Yu, B1, Elsherbini disclose the interposer according to claim 4, wherein the second component (Yu fig. 2, Chip 2) is a capacitor (see Yu [0015]: Chip 2 comprises a plurality of DRAM memory circuits; see evidentiary reference Sugioka [0003] which teaches that DRAM memory cells each include a capacitor; therefore, the teachings of Yu in light of evidentiary reference Sugioka disclose that the second component includes a capacitor).
Regarding claim 15, Yu, B1, Elsherbini disclose the interposer according to claim 2, wherein the second component (Yu fig. 2, Chip 2) is an IC (see Yu [0015]).
Regarding claim 16, Yu, B1, Elsherbini disclose the interposer according to claim 3, wherein the second component (Yu fig. 2, Chip 2) is an IC (see Yu [0015]).
Regarding claim 17, Yu, B1, Elsherbini disclose the interposer according to claim 4, wherein the second component (Yu fig. 2, Chip 2) is an IC (see Yu [0015]).
PNG
media_image3.png
476
1168
media_image3.png
Greyscale
Regarding claim 18, Yu, B1, Elsherbini disclose the interposer according to claim 2, wherein the object (see Yu fig. 2) is a coreless substrate (the package layer including Chip 1 and encapsulation layer 109 is a coreless substrate (since it has no rigid core)).
Regarding claim 19, Yu, B1, Elsherbini disclose the interposer according to claim 3, wherein the object (see Yu fig. 2) is a coreless substrate (the package layer including Chip 1 and encapsulation layer 109 is a coreless substrate (since it has no rigid core)).
Regarding claim 20, Yu, B1, Elsherbini disclose the interposer according to claim 4, wherein the object (Yu fig. 2) is a coreless substrate (the package layer including Chip 1 and encapsulation layer 109 is a coreless substrate (since it has no rigid core)).
PNG
media_image5.png
413
454
media_image5.png
Greyscale
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Yu, in view of Beroz et al. (US 2004/0238857 A1), hereinafter as B1, in view of Elsherbini, further in view of Kelkar et al. (US 20130105966 A1), hereinafter referred to as “Kelkar”.
Yu, B1, Elsherbini disclose the interposer according to claim 1.
Yu, B1, Elsherbini fail to disclose wherein the second component is directly in contact with the first component.
Kelkar discloses a semiconductor chip package (Kelkar fig. 5, 100; see [0011]) including a first component (Kelkar fig. 5, bottom 102; see [0020]) and a second component (Kelkar fig. 5, top 102; see [0020]), wherein the second component overlaps the first component (see Kelkar fig. 5), and wherein the second component is directly in contact with the first component (see Kelkar fig. 5; see [0023]).
The direct contact teachings of Kelkar are incorporated into the previously combined device of Yu, B1, Elsherbini wherein the present combination discloses wherein the second component is directly in contact with the first component.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the previously-combined device with the direct contact teachings of Kelkar to reduce manufacturing costs by using less adhesive material.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMUEL PARK whose telephone number is (303)297-4277. The examiner can normally be reached Normal Schedule: M-F Sometime between 6:30 a.m. - 7:00 p.m..
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven H. Loke can be reached at (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SAMUEL PARK/Primary Examiner, Art Unit 2818
Prosecution Insights