DETAILED ACTION
This action is responsive to the following communication: the response filed 3/25/26. The changes and remarks disclosed therein have been considered.
Claim(s) status: 1-16 and 18-20 pending.
Claim Objections
The claim(s) is/are objected to because of the following informalities:
Claim 1: it appears that “the plurality of program loops” in line(s) 8 was meant to be -- a plurality of program loops --.
Claim 11: it appears that “a plurality of program loops” in line(s) 2 was meant to be -- the plurality of program loops --.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 11, 18-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cho et al. (US 2011/0158000 ‒hereinafter Cho).
Regarding claim 1, Cho discloses a memory device comprising:
a memory cell (any selected memory cell of memory array 110; fig. 1);
a page buffer (PB; fig. 2) comprising a latch (LAT1/LAT2/LAT3; fig. 2) storing a result of comparing a threshold voltage of the memory cell to a pre-verify voltage and a main verify voltage (“page buffers configured to latch first data according to results from comparing threshold voltages of the selected memory cells with the sub-verification voltage [i.e. pre-verify voltage VP1’; fig. 3] and latch second data according to results from comparing the threshold voltages of the memory cells with the target verification voltage [i.e. main verify voltage VP1; fig. 3]” para 0013, further fig. 2 para 0034); and
a program operation control circuit (120; fig. 1) configured to control the page buffer (PB) to apply a first program control voltage to a bit line (S529; fig. 5) connected to the memory cell while a program voltage is applied (S510; fig. 5) to a word line connected to the memory cell (“supplying a program voltage to the word line of selected memory cells” para 0070) based on a cumulative number of times (a cumulative number of times of performing/repeating operation S524 successively until a maximum number is reached in an incremental step pulse programming (ISPP); fig. 5), across the plurality of program loops (plurality of program loops including programming steps and verifications in the ISPP; fig. 3), pass data (first data; para 0035) indicating that the threshold voltage of the memory cell exceeds the pre-verify voltage (the first data indicating “a case where all the threshold voltages of the selected memory cells are higher than the sub-verification voltage” para 0045, i.e. passes sub-verification verify; para 0059) is sensed by the page buffer (the first data is sensed by page buffer PB each time of performing/repeating operation S524; fig. 5, para 0038-0039, 0076).
Regarding claim 2, Cho discloses the memory device, wherein the program operation control circuit is configured to control the page buffer to apply a program allowable voltage (i.e. Vcc; para 0075) to the bit line in a second program loop (i.e. a second iteration of a first program loop in the ISPP; fig. 5) when the pass data is sensed by the page buffer (fig. 2) in a first program loop (first program loop of the ISPP; fig. 5).
Regarding claim 11, Cho discloses the memory device, wherein the program operation control circuit performs a plurality of program loops in which a program voltage applied to the word line increases by a step voltage (ΔISPP; fig. 5) when a program loop count increases (fig. 5).
Regarding claim 18, Cho discloses a method of operating a memory device, the method comprising:
applying a program voltage to a word line connected to a memory cell (“supplying a program voltage to the word line of selected memory cells at step S510 ” para 0070) in a first program loop (i.e. a first loop in starting an incremental step pulse programming (ISPP); fig. 5);
identifying (S512; fig. 5) a threshold voltage (Vth; fig. 3) of the memory cell using a pre-verify voltage (PV1’; fig. 3) in the first program loop (i.e. identifying whether there is any memory cell having threshold voltage Vth lower than PV1’; fig. 3, 5); and
applying a bit line voltage to a bit line (S529; fig. 5) connected to the memory cell in a second program loop (i.e. a second iteration of the first program loop in the ISPP) based on a cumulative number of times (a cumulative number of times of performing/repeating operation S524 successively until a maximum number is reached in an incremental step pulse programming (ISPP); fig. 5), across a plurality of program loops (plurality of program loops including programming steps and verifications in the ISPP; fig. 3), the threshold voltage (Vth) of the memory cell is identified as a threshold voltage greater than the pre-verify voltage (first data identifies “a case where all the threshold voltages of the selected memory cells are higher than the sub-verification voltage” para 0045, i.e. passes sub-verification verify; para 0059).
Regarding claim 19, Cho discloses the method, wherein applying the bit line voltage to the bit line in the second program loop further comprises applying a program allowable voltage (i.e. Vcc; para 0075) to the bit line connected to the memory cell of which the threshold voltage is identified as the threshold voltage greater than the pre-verify voltage (“a case where all the threshold voltages of the selected memory cells are higher than the sub-verification voltage” para 0045, i.e. passes sub-verification verify; para 0059), in the second program loop (the second iteration of the first program loop).
Regarding claim 20, Cho discloses the method, wherein applying the program allowable voltage to the bit line in the second program loop comprises applying a program control voltage (S529; fig. 5) to the bit line connected to the memory cell of which the threshold voltage is identified as the threshold voltage greater than the pre-verify voltage (“a case where all the threshold voltages of the selected memory cells are higher than the sub-verification voltage” para 0045, i.e. passes sub-verification verify; para 0059).
Claim(s) 3-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cho et al. (US 2011/0158000 ‒hereinafter Cho) in view of An et al. (US 2015/0364208 ‒hereinafter An).
Regarding claim 3, Cho discloses the memory device, wherein the program operation control circuit is configured to control the page buffer to apply the first program control voltage to the bit line (para 0075-0076).
Cho does not expressly disclose in a third program loop when the pass data is sensed by the page buffer in the second program loop.
An discloses apply the first program control voltage to the bit line (i.e. in a third program loop after verify in fig. 5E, the program inhibition voltage will apply to the bit line of the program fail cell which is now program pass cell) in a third program loop (i.e. a third iteration of program loop S401 after verify (fig. 5E)) when the pass data is sensed by the page buffer (fig. 5E) in the second program loop (i.e. second iteration S401).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Cho is modifiable as taught by An for the purpose of facilitating data accessing schemes by reducing widening of threshold voltage distribution (para 0078 of An), which is common and well known to secure the integrity of data storage.
Regarding claim 4, Cho discloses the memory device, wherein the first program control voltage is greater than the program allowable voltage (program allowable voltage, i.e. Vcc, is lower than a first program control voltage, i.e. program-inhibition voltage; para 0075).
Regarding claim 5, Cho discloses the memory device, wherein the program allowable voltage is at least of: a ground voltage and a reference potential voltage (para 0075).
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cho et al. (US 2011/0158000 ‒hereinafter Cho) in view of Sim (US 2008/0253194).
Regarding claim 12, Cho does not expressly disclose the memory device, wherein a difference between the main verify voltage and the pre-verify voltage is greater than the step voltage.
Sim discloses a difference between the main verify voltage (i.e. between a second voltage and target verify voltage Vvfy or a second verify voltage Vvfy2; para 0011, 0054) and the pre-verify voltage (Vvfyi; fig. 2) is greater than the step voltage (ΔV; fig. 2).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Cho is further modifiable as taught by Sim for the purpose of facilitating data accessing schemes by securing sufficient read margins and optimizing threshold voltage distribution (para 0009 of Sim).
Allowable Subject Matter
Claim(s) 13-16 are allowed.
The following is an examiner’s statement of reasons for allowance: the prior art of record and considered pertinent to the applicant's disclosure does not teach or suggest the claimed invention having the following limitation, in combination with the remaining claimed limitations.
With respect to independent claim 13 (and all dependent claim(s) therefrom), the prior art fails to teach or suggest the claimed limitations, namely a second main sensing latch configured to store the fail data indicating the failure of the main verify operation on the memory cell in the second program loop.
The allowable claims are supported in at least fig. 13 of the instant application.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Claim(s) 6-10 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record and considered pertinent to the applicant's disclosure does not teach or suggest the claimed invention having the following limitation, in combination with the remaining claimed limitations.
With respect to dependent claim 6 (and all dependent claim(s) therefrom), the prior art fails to teach or suggest the claimed limitations, namely apply a second program control voltage greater than the first program control voltage to the bit line in a fourth program loop when the pass data is sensed by the page buffer in the third program loop.
With respect to dependent claim 8 (and all dependent claim(s) therefrom), the prior art fails to teach or suggest the claimed limitations, namely a second main sensing latch configured to store the main verify data indicating whether the threshold voltage of the memory cell exceeds the main verify voltage in the second program loop.
The allowable claims are supported in at least fig. 9-10 of the instant application.
Response to Arguments
Applicant’s arguments with respect to the pending claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
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/UYEN SMET/
Primary Examiner, Art Unit 2824______