Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to the Application filed January 19, 2024.
Status of claims to be treated in this office action:
a. Independent: 1, 11, 16
b. Pending: 1-20
Specification
The disclosure is objected to because of the following informalities:
On p.1, line 5, make the following change:
“Aspects of the present disclosure were disclosed in…”
On p.2, line 16, make the following change:
“(as shown in FIG. 1A), defined in the literature as…”
On p.2, line 21, make the following change:
“Reported implementations of p-bits[[,]] demonstrate…”
On p.3, line 15, make the following change:
“a stochastic response, without addressing the staircase behavior[[,]] that originates from…”
On p.5, line 7, make the following change:
“FIG. 2A depicts a conventional [[a]] one transistor one MTJ (1T1M) probabilistic bit…”
On p.6, line 19, make the following change:
“defined in the literature as a low barrier magnet (LBM)”
On p.7, line 23 through p.8, line 1, the phrase “almost binary MTJs” is not well defined and may be a mistake. Please revise the sentence for clarity.
On p.8, line 19, make the following change:
“MTJ (using either perpendicular or in-plane magnetic anisotropy (PMA/IMA) magnets)…”
On p.11, lines 19, 20, and 21, change “corresponding” to “corresponds”
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 11, and 16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. The preambles of claims 1, 11, and 16 recite “An apparatus for implementing a probabilistic bit (p-bit) circuit with enhanced tunability”. Examiner asserts that the word “enhanced” renders this claim indefinite. MTJs are tunable because they turn on and off, but the adjective “enhanced” is vague, and it is unclear what component or functionality makes the tunability “enhanced”. Examiner recommends removing the word “enhanced” from the preambles of independent claims 1, 11, and 16.
Claim 11 recites the limitation "receive a first voltage from the drain at an inverting terminal" in line 1 of p.3. There is insufficient antecedent basis for this limitation in the claim. Examiner recommends changing “the drain” to “the drain of the transistor”.
Claim 16 recites the limitations "comparing the fluctuating voltage with a reference voltage" in line 23 of p.3. There is insufficient antecedent basis for this limitation in the claim. Examiner recommends changing “the fluctuating voltage” to “the drain voltage”.
All the dependent claims 2-10, 12-15 and 17-20 carry the same deficit due to dependency and henceforth rejected.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4, and 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Ranjan et al. (US Pub. 20130258764 A1; “Ranjan”) in view of Boujamaa et al. (US Pub. 20200372942 A1; “Boujamaa”) and Zhang et al. (CN 104134461 A; “Zhang”).
Regarding independent claim 1, Ranjan discloses an apparatus for implementing a probabilistic bit (p-bit) circuit with enhanced tunability (Fig. 9: read circuit 1000; [0091]: FIG. 9 is shown to include a memory cell 1002 coupled to a sense amplifier circuit 1004…memory cell 1002 is shown to include an access transistor 1008, an MTJ 1010 and an MTJ 1012. Per the Specification of the present application, p.3, lines 5-11, the p-bit circuit is simply an “an NMOS transistor with a stochastic MTJ connected in series, with its output at the drain side in a 1T1M structure”. Further, the preamble is not given weight because the other limitations of claim 1 have the same meaning if we replace the preamble), the apparatus comprising:
multiple magnetic tunnel junctions (MTJs) connected in series (MTJ 1010, MTJ 1012) to a drain of a transistor (access transistor 1008);
the resistor is of a resistance value that is selected based on an average equivalent resistance value of a series combination of the multiple MTJs; and ([0098]: Examples of resistance values of the reference resistors are averages of the resistances of the MTJs 1010 and 1012. For example, the resistance of the resistor 1026 is the average of the resistances of the MTJs 1010 and 1012 at the states 1 and 4, as indicated in Table 1)
a comparator (sense amplifier circuit 1004; [0096]: The circuit 1004 compares the total resistance of the MTJs 1010 and 1012 with the resistances of the reference resistors of the state reference circuits) configured to receive voltage from the drain (“drain voltage”) (drain of 1008) and generate an output voltage (Fig. 9: “Data out”) based on a reference voltage (Vcc) and the drain voltage.
Ranjan does not explicitly disclose:
a resistor connected to a source of the transistor, wherein the resistor is of a resistance value that is selected based on an average equivalent resistance value of a combination of the multiple MTJs; and
a comparator configured to receive voltage from the drain (“drain voltage”) and generate an output voltage based on a reference voltage and the drain voltage.
However, Boujamaa teaches:
a resistor (Fig. 6B: voltage drop element is 620; [0037]) connected to a source of the transistor (since the ground 102 is depicted at the top of the page, the source of the transistor may be at the “top” of the depicted transistor (see annotated screenshot below), and also the resistor 620 may be connected to the source even if the source is at the bottom of the transistor because the source and drain of a transistor are electrically connected), wherein the resistor is of a resistance value that is selected based on an average equivalent resistance value of a combination of the multiple MTJs ([0025]: the CMOS resistor 140 serves as a resistive offset that is coupled in series to the LRS MTJ 122 and the first access device 124, such that a total reference impedance of the reference path 160 is in between an LRS and a HRS. Examiner notes that LRS is a low-resistance state and HRS is a high-resistance state, per [0025]); and
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It would have been obvious to one with ordinary skill in the art before the earliest
effective filing date of the claimed invention to apply the teachings of Boujamaa to Ranjan wherein the apparatus comprises a resistor connected to a source of the transistor, wherein the resistor is of a resistance value that is selected based on an average equivalent resistance value of a combination of the multiple MTJs in order to implement a sense amplifier with reference and bit path circuits that allow for accurate tracking of MTJ parameters with fewer components and lower complexity (Boujamaa, [0006], [0026]).
Also, Zhang teaches:
a comparator (Fig. 2: sense amplifier (S.A.); [0012]: This sensing amplifier can be a traditional voltage comparator amplifier, whose function is to
amplify and compare two input voltage signals and output the corresponding logic value) configured to receive voltage from the drain (“drain voltage”) (connection point X; [0010]: One of the two input terminals of the sense amplifier is
connected to the reference voltage signal, and the other is also connected to the drain of the selected transistor in the hybrid memory cell, i.e., connection point X) and generate an output voltage based on a reference voltage and the drain voltage (Out_C; [0017]).
It would have been obvious to one with ordinary skill in the art before the earliest
effective filing date of the claimed invention to apply the teachings of Zhang to modified Ranjan wherein the apparatus comprises a comparator configured to receive voltage from the drain (“drain voltage”) and generate an output voltage based on a reference voltage and the drain voltage in order to provide a read circuit structure to quickly and accurately read the hybrid memory cell operating mode and logic value (Zhang, [0007]).
Regarding claim 2, Ranjan, Boujamaa, and Zhang together disclose the limitations of claim 1, and further through Ranjan:
wherein the MTJs are bipolar MTJs whose resistance value fluctuates to any one of two resistance states ([0111]: the parallel and anti-parallel states define the logical state of a free layer which define the logical state of the corresponding MTJ. For example, free layer 1118's magnetization state being in a parallel state relative to fixed layer 1108 defines a different logical state than free layer 1118's magnetization direction being in an anti-parallel state relative to fixed layer 1108. An example of logic states are `0` or `1`).
Regarding claim 4, Ranjan, Boujamaa, and Zhang together disclose the limitations of claim 2, and further through Ranjan:
wherein the bipolar MTJs ([0111]) are non-identical MTJs ([0060]: In other embodiments, some of which will be shortly presented and discussed, the size of the barrier layers of the MTJs are changed to effectuate different resistances. In yet other embodiments, the size of the MTJs are changed to the same), wherein resistance states of the non-identical MTJs are spaced non-uniformly (Fig. 3 shows non-uniform spacing of states), and wherein a number of resistance states is equal to 2N where N is the number of MTJs ([0058]: FIG. 2 shows various states of the memory element 100. Due to the use of two MTJs, four different states or two bits may be stored, therefore, the states 1-4 are shown).
Regarding claim 8, Ranjan, Boujamaa, and Zhang together disclose the limitations of claim 1. Zhang teaches a comparator, and further through Ranjan:
wherein the comparator (Fig. 9: 1004) is configured to receive an input voltage (voltage from the selected state reference circuit 1020, 1022, or 1024) as the reference voltage (Vcc), and wherein the output voltage varies as the input voltage provided to the comparator varies ([0097]: to compare the resistance of the MTJs to the resistance of the resistor 1026, the signal 1040 is activated thereby turning on the transistor 1028).
Regarding claim 9, Ranjan, Boujamaa, and Zhang together disclose the limitations of claim 8, and further through Zhang:
wherein the drain voltage (Fig. 2: connection point X) is determined based on a voltage provided to a gate of the transistor (WL), and wherein the voltage input to the gate is fixed to a particular value (it is known in the art that word lines are fixed because they select a row of a memory array).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Zhang to modified Ranjan wherein the drain voltage is determined based on a voltage provided to a gate of the transistor, and wherein the voltage input to the gate is fixed to a particular value in order to provide a read circuit structure to quickly and accurately read the hybrid memory cell operating mode and logic value (Zhang, [0007]).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Ranjan (US Pub. 20130258764 A1), Boujamaa (US Pub. 20200372942 A1), and Zhang (CN 104134461 A) as applied to claim 2 above, and further in view of Ohmori et al. (US Pub. 20200013443 A1; “Ohmori”).
Regarding claim 3, Ranjan, Boujamaa, and Zhang together disclose the limitations of claim 1, and further through Ranjan:
wherein the bipolar MTJs ([0111]) are identical MTJs ([0060]),
However, neither Ranjan, Boujamaa, nor Zhang discloses:
wherein resistance states of the identical MTJs are spaced uniformly, and wherein a number of resistance states is equal to N+1 where N is the number of MTJs.
However, Ohmori teaches:
wherein resistance states of the identical MTJs are spaced uniformly ([0101]: since the MTJ elements 100a and 100b have substantially identical magnetic characteristics, in a case where the resistance state of the memory cell 10 is the HL state or the LH state, it is not possible to determine in the step which of the HL state and the LH state the resistance state of the memory cell 10 is), and wherein a number of resistance states is equal to N+1 where N is the number of MTJs (Fig. 5: HH state, HL/LH state, LL state).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Ohmori to modified Ranjan wherein resistance states of the identical MTJs are spaced uniformly, and wherein a number of resistance states is equal to N+1 where N is the number of MTJs in order to provide a magnetic memory and reading method of the memory that can record multivalued information in one memory cell (Ohmori, [0007]).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Ranjan (US Pub. 20130258764 A1), Boujamaa (US Pub. 20200372942 A1), and Zhang (CN 104134461 A) as applied to claim 1 above, and further in view of Zhang et al. (CN 113744777 A; “Zhang-777”).
Regarding claim 5, Ranjan, Boujamaa, and Zhang together disclose the limitations of claim 1. Neither Ranjan, Boujamaa, nor Zhang discloses:
wherein the MTJs are continuous MTJs whose resistance value fluctuates to any value between two resistance states.
However, Zhang-777 teaches:
wherein the MTJs are continuous MTJs whose resistance value fluctuates to any value between two resistance states ([n0028]: The storage cell adopts a specific MTJ structure and realizes multiple different resistance states in a single storage cell through current control, thereby truly realizing multi-bit storage of a single device and effectively improving storage density).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Zhang-777 to modified Ranjan wherein the MTJs are continuous MTJs whose resistance value fluctuates to any value between two resistance states in order to implement a device that provides multi-bit storage with improved storage density (Zhang-777, [n0015]).
Claims 6-7 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Ranjan (US Pub. 20130258764 A1), Boujamaa (US Pub. 20200372942 A1), and Zhang (CN 104134461 A) as applied to claims 1 and 8 above, respectively, and further in view of Hong et al. (KR 20220136595 A; “Hong”).
Regarding claim 6, Ranjan, Boujamaa, and Zhang together disclose the limitations of claim 1. Neither Ranjan, Boujamaa, nor Zhang discloses:
wherein the drain voltage varies as an input voltage provided to a gate of the transistor varies.
However, Hong teaches:
wherein the drain voltage (Fig. 6: Vout; [0061]) varies as an input voltage (Vi) provided to a gate of the transistor varies (in reference to Figs. 6 and 7, per [0064]: As shown in Fig. 7, the average value of the output voltage…can change depending on the input voltage).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Hong to modified Ranjan wherein the drain voltage varies as an input voltage provided to a gate of the transistor varies in order to implement a p-bit device that can control the magnetization direction of an MTJ in an unstable state (Hong, [0010]).
Regarding claim 7, Ranjan, Boujamaa, Zhang, and Hong together disclose the limitations of claim 6. Zhang teaches the output voltage of the comparator and further through Hong:
wherein the output voltage varies as the input voltage provided to the gate of the transistor varies (Figs. 6-7 and [0064]. Examiner asserts that if the variable drain voltage Vout of Hong were provided as an input to the comparator of Zhang, one with ordinary skill in the art would know that the output voltage of the comparator will vary).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Hong to modified Ranjan wherein the output voltage varies as the input voltage provided to the gate of the transistor varies in order to implement a p-bit device that can control the magnetization direction of an MTJ in an unstable state (Hong, [0010]).
Regarding claim 10, Ranjan, Boujamaa, and Zhang together disclose the limitations of claim 8. Neither Ranjan, Boujamaa, nor Zhang disclose:
configuring the resistance value of the resistor to 0.
However, Hong teaches:
configuring the resistance value of the resistor to 0 (in Fig. 6, Hong teaches a p-bit circuit that does not include a resistor, and that is equivalent to configuring a resistance value of a resistor to 0 ohms).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Hong to modified Ranjan wherein the resistance value of the resistor is configured to 0 in order to implement a p-bit device that can control the magnetization direction of an MTJ in an unstable state (Hong, [0010]).
Claims 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Ranjan (US Pub. 20130258764 A1) in view of Zhang-777 (CN 113744777 A) and Gogl et al. (20040120200 A1; “Gogl”).
Regarding independent claim 11, Ranjan discloses an apparatus for implementing a probabilistic bit (p-bit) circuit with enhanced tunability (Fig. 9: read circuit 1000; [0091]), the apparatus comprising:
multiple magnetic tunnel junctions (MTJs) connected in series (MTJ 1010, MTJ 1012) to a drain of a transistor (1008); and
a comparator (1004) configured to:
Ranjan does not explicitly disclose:
continuous magnetic tunnel junctions (MTJs)
a comparator configured to:
receive a first voltage from the drain at an inverting terminal as a drain voltage,
receive an input voltage at a non-inverting terminal, and
generate an output voltage based on the input voltage and the drain voltage.
However, Zhang-777 teaches:
continuous magnetic tunnel junctions (MTJs) ([n0028])
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Zhang-777 to Ranjan wherein the apparatus comprises continuous magnetic tunnel junctions (MTJs) in order to implement a device that provides multi-bit storage with improved storage density (Zhang-777, [n0015]).
Also, through Gogl:
a comparator (Fig. 6: voltage comparator 34; [0053]) configured to:
receive a first voltage from the drain at an inverting terminal as a drain voltage,
receive an input voltage at a non-inverting terminal ([0053]: The drains of bitline clamping devices T.sub.1 and T.sub.2, which preferably comprise transistors, are coupled to the positive and negative inputs, respectively, of the voltage comparator 34), and
generate an output voltage based on the input voltage and the drain voltage ([0062]: The input signals inputA and inputB are kept at the read voltage of the memory cell by source follower clamping devices T.sub.1 and T.sub.2 that are controlled by the gate reference voltage V.sub.analog1…the voltage comparator 34 is adapted to output (e.g., at "OUT") a logic state of the selected memory cell).
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Gogl to modified Ranjan wherein the apparatus comprises a comparator configured to: receive a first voltage from the drain at an inverting terminal as a drain voltage, receive an input voltage at a non-inverting terminal, and generate an output voltage based on the input voltage and the drain voltage in order to implement a current sense amplifier that eliminates capacitive mismatch, performs at a high speed, and is compatible with MTJ memory (Gogl, [0013], [0037]).
Regarding claim 12, Ranjan, Zhang-777, and Gogl together disclose all the limitations of claim 11. Claim 12 recites substantially the same subject matter as the last limitation of claim 8, and henceforth is rejected for the same reasons.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Ranjan (US Pub. 20130258764 A1), Zhang-777 (CN 113744777 A), and Gogl (20040120200 A1) as applied to claim 12 above, and further in view of Zhang (CN 104134461 A).
Regarding claim 13, Ranjan, Zhang-777, and Gogl together disclose all the limitations of claim 12. Claim 13 recites substantially the same subject matter as claim 9, and henceforth is rejected for the same reasons.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Ranjan (US Pub. 20130258764 A1), Zhang-777 (CN 113744777 A), and Gogl (20040120200 A1) as applied to claim 11 above, and further in view of Boujamaa (US Pub. 20200372942 A1).
Regarding claim 14, Ranjan, Zhang-777, and Gogl together disclose all the limitations of claim 11. Claim 14 recites exactly the same subject matter as second limitation of claim 1, and henceforth is rejected for the same reasons.
Claims 15 is rejected under 35 U.S.C. 103 as being unpatentable over Ranjan (US Pub. 20130258764 A1), Zhang-777 (CN 113744777 A), and Gogl (20040120200 A1) as applied to claim 11 above, and further in view of Hong (KR 20220136595 A) and Zhang (CN 104134461 A).
Regarding claim 15, Ranjan, Zhang-777, and Gogl together disclose all the limitations of claim 11. Claim 15 recites a second limitation that is substantially the same as claim 7, and henceforth is rejected for the same reasons. Neither Ranjan, Zhang-777, Gogl, nor Hong discloses:
wherein the input voltage is fixed at a reference voltage, and
However, Zhang teaches:
wherein the input voltage is fixed at a reference voltage (Fig. 2: the reference voltage Vref; [0034]), and
It would have been obvious to one with ordinary skill in the art before the earliest effective filing date of the claimed invention to apply the teachings of Zhang to modified Ranjan wherein the input voltage is fixed at a reference voltage in order to provide a read circuit structure to quickly and accurately read the hybrid memory cell operating mode and logic value (Zhang, [0007]).
Claims 16-17 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Ranjan (US Pub. 20130258764 A1) in view of Boujamaa (US Pub. 20200372942 A1), Zhang (CN 104134461 A), and Hong (KR 20220136595 A).
Independent claim 16 contains limitations that are substantially the same in claimed subject matter as limitations of claims 1, 6, and 7, and therefore claim 16 is rejected for the same reasons.
Regarding claim 17, Ranjan, Boujamaa, Zhang, and Hong together disclose all the limitations of claim 16. Claim 17 recites substantially the same subject matter as claim 6 and the first limitation of claim 1, and henceforth is rejected for the same reasons.
Regarding claim 19, Ranjan, Boujamaa, Zhang, and Hong together disclose all the limitations of claim 17. The first limitation of claim 19 is substantially the same subject matter as claim 7 and the second limitation is substantially the same subject matter as the first limitation of claim 15, and henceforth claim 15 is rejected for the same reasons.
Regarding claim 20, Ranjan, Boujamaa, Zhang, and Hong together disclose all the limitations of claim 17. The first limitation of claim 20 recites substantially the same subject matter as claim 8, and the second limitation of claim 20 recites substantially the same subject matter as claim 9. Further, it is known in the art that fixing the gate voltage of a transistor controls the fluctuation range of the voltage on the drain. Henceforth, claim 20 is rejected for the same reasons as claims 8 and 9.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Ranjan (US Pub. 20130258764 A1), Boujamaa (US Pub. 20200372942 A1), Zhang (CN 104134461 A), and Hong (KR 20220136595 A) as applied to claim 16 above, and further in view of Gogl (20040120200 A1).
Regarding claim 18, Ranjan, Boujamaa, Zhang, and Hong together disclose all the limitations of claim 16. Claim 18 recites substantially the same subject matter as the third and fourth limitations of claim 11, and henceforth is rejected for the same reasons.
Conclusion
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/E.R.A./Examiner, Art Unit 2824
/SULTANA BEGUM/Primary Examiner, Art Unit 2824
6/11/2026
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