DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 8 and 15 have been considered but are moot because the new ground of rejection does not rely on how any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1 – 3, 6 – 10, 13 – 16, 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 10,595,394 B1) in view of Reynov (US 2022/0141952 A1) and Benedict (US 2024/0098898 A1).
Regarding Claim 1, Kim (US 10,595,394 B1) discloses a printed circuit board (Fig 5), comprising: a first group (70) of layers laminated together, the first group (70) of layers (S1-S6) being directed to high speed (Abstract, Column 1, lines 30-48, Claim 1) signal (S1-S6) routing; and a second group (80) of layers laminated together, the second group (80) of layers (PWR,S7-S8) being directed to delivering power (see Fig 5 showing PWR layer), wherein when the second group (80) of layers are laminated to the first group (70) of layers, the first group (70) of layers and the second group (80) of layers collectively form a multi-lamination structure (10) and wherein the second group of layers (80) includes power layer (PWR).
Kim does not explicitly disclose wherein the second group of layers includes power layers and one of the power layers is an outermost layer of the multi-lamination structure.
Reynov (US 2022/0141952 A1) teaches of a printed circuit board (Fig 5), comprising: a first group (220(1)) of layers (104,106) laminated together, the first group of layers (220(1)) being directed to signal routing (106; [0035]); and a second group (220(2)) of layers (106,102) laminated together, the second group (220(2)) of layers being directed to delivering power (102; [0036]), wherein when the second group (220(2)) of layers are laminated to the first group (220(1)) of layers, the first group (220(1)) of layers and the second group (220(2)) of layers collectively form a multi- lamination structure (see Fig 5), and wherein the second group (220(2)) of layers includes power layers (102(1)-102(4)).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the board as disclosed by Kim, wherein the second group of layers includes power layers as taught by Reynov, in order to meet demands, provide a high-current board and form conductive paths capable of carrying higher amounts of current through the board necessitated by an increase power consumption (Reynov, [0001-0003,0016]).
Benedict (US 2024/0098898 A1) teaches of a printed circuit board (Fig 4A), comprising: a first group (upper plurality of layers as seen in Fig 4A) of layers laminated together, the first group (upper plurality of layers as seen in Fig 4A) of layers being directed to high speed ([0003,0022,0023,0046]) signal routing; and a second group (lower plurality of layers as seen in Fig 4A) of layers laminated together, the second group (lower plurality of layers as seen in Fig 4A) of layers being directed to delivering power (408; [0032-0033]), wherein when the second group (lower plurality of layers as seen in Fig 4A) of layers are laminated to the first group (upper plurality of layers as seen in Fig 4A) of layers, the first group (upper plurality of layers as seen in Fig 4A) of layers and the second group (lower plurality of layers as seen in Fig 4A) of layers collectively form a multi- lamination structure (400), and wherein the second group (lower plurality of layers as seen in Fig 4A) of layers includes one (408) of the power layer is an outermost layer (see Fig 4A) of the multi-lamination structure.
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the board with the second group of layers includes power layers as taught by Kim in view of Reynov, wherein one of the power layers is an outermost layer of the multi-lamination structure as taught by Benedict, in order to improve signal quality (Benedict, [0033]).
Regarding Claim 2, Kim further discloses the printed circuit board (Fig 5) of claim 1, wherein the first group (70) of layers is coupled to the second group (80) of layers through (a lamination process after the first group (70) of layers is laminated together and the second group (80) of layers is laminated together).
Claim 2 states “a lamination process after the first group of layers is laminated together and the second group of layers is laminated together”. In accordance to MPEP 2113, the method of forming the device is not germane to the issue of patentability of the device itself. Therefore, this limitation has not been given patentable weight. Please note that even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product, i.e. “a lamination process after the first group of layers is laminated together and the second group of layers is laminated together”, does not depend on its method of production, i.e. laminating after a specific earlier lamination. In re Thorpe, 227 USPQ 964, 966 (Federal Circuit 1985).
Regarding Claim 3, Kim further discloses the printed circuit board (Fig 5) printed circuit board of claim 1, wherein the first group (70) of layers is located on top of the second group (80) of layers.
Regarding Claim 6, Kim further discloses the printed circuit board (Fig 5) the printed circuit board of claim 1, wherein the high speed (Abstract, Column 1, lines 30-48, Claim 1) signal (S1-S6) routing is separated (located in 70) from a power delivery plane (PWR is located in 80).
Regarding Claim 7, Kim in view of Reynov and Benedict teaches the limitations of the preceding claim and Kim discloses the limitations of the preceding claim and Kim further discloses the printed circuit board (Fig 5) of claim 1, wherein the first group (70) of layers includes layers (S-S6), and the second group (80) of layers includes layers (PWR,S7-S8).
Kim does not explicitly disclose wherein the first group of layers includes 32 layers, and the second group of layers includes 12 layers.
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the board as taught by Kim in view of Reynov and Benedict, wherein the first group of layers includes 32 layers, and the second group of layers includes 12 layers, in order to provide sufficient wiring routing paths to meet a desired board application, in order to provide a desired electrical density within the board and to form adequate signal and power wirings, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8. Please note that in the instant application, page 11 [0066], Applicant has not disclosed any criticality for the claimed limitations.
Regarding Claim 8, Kim discloses a printed circuit board (Fig 5), comprising: a first plurality of layers (S1-S6), the first plurality of layers being laminated together to form a first lamination structure (70), the first lamination structure (70) being directed to high speed (Abstract, Column 1, lines 30-48, Claim 1) signal routing (S1-S6), the first plurality of layers includes several signal VIAs (40,S) extending therethrough; and a second plurality of layers (PWR,S7-S8), the second plurality of layers being laminated together to form a second lamination structure (80), the second lamination structure (80) being directed to delivering power (see Fig 5 showing PWR layer) for the printed circuit board, wherein when the second lamination structure (80) is laminated to the first lamination structure (70), the first lamination structure (70) and the second lamination structure (80) collectively form a multi-lamination structure (10).
Kim does not disclose the first plurality of layers includes several power VIAs extending therethrough and wherein only the power VIAs extend through the second plurality of layers to an outermost layer of the multi-lamination structure, the outermost layer being a power layer.
Reynov (US 2022/0141952 A1) teaches of a printed circuit board (Fig 5), comprising: a first plurality (220(1)) of layers (104,106), the first plurality (220(1)) of layers being laminated together to form a first lamination structure (220(1)), the first lamination structure being directed to signal routing (106; [0035]), the first plurality of layers (220(1)) includes several signal VIAs (502(1-502(8))) extending therethrough and several power VIAs (302(1)-302(4)) extending therethrough; and a second plurality (220(2)) of layers (106,102), the second plurality (220(2)) of layers being laminated together to form a second lamination structure (220(2)), the second lamination structure (220(2)) being directed to delivering power (102; [0036]) for the printed circuit board, wherein when the second lamination structure (220(2)) is laminated to the first lamination structure (220(1)), the first lamination structure and the second lamination structure collectively form a multi-lamination structure (500), and wherein only the power VIAs (302) extend through the second plurality (220(2)) of layers to an outermost layer (see Fig 5) of the multi-lamination structure.
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the board as disclosed by Kim, wherein the first plurality of layers includes several power VIAs extending therethrough and wherein only the power VIAs extend through the second plurality of layers to an outermost layer of the multi-lamination structure as taught by Reynov, in order to carry or transfer power or current from power layers to components, to meet demands, provide a high-current board and form conductive paths capable of carrying higher amounts of current through the board necessitated by an increase power consumption, improve board real estate and prevent a Swiss cheese effect in the board (Reynov, [0001-0003,0016,0041,0045-0048]).
Benedict (US 2024/0098898 A1) teaches of a printed circuit board (Fig 4A), comprising: a first plurality (upper plurality of layers as seen in Fig 4A) of layers, the first plurality of layers being laminated together to form a first lamination structure (upper plurality of layers as seen in Fig 4A), the first lamination structure being directed to high speed ([0003,0022,0023,0046]) signal routing, the first plurality of layers includes several signal VIAs (124,126) extending therethrough and several power VIAs (128,130) extending therethrough; and a second plurality (lower plurality of layers as seen in Fig 4A) of layers, the second plurality (lower plurality of layers as seen in Fig 4A) of layers being laminated together to form a second lamination structure, the second lamination structure being directed to delivering power (408; [0032-0033]) for the printed circuit board, wherein when the second lamination structure is laminated to the first lamination structure, the first lamination structure and the second lamination structure collectively form a multi-lamination structure (400), and wherein the outermost layer (408) being a power layer ([0033]).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the board as taught by Kim in view of Reynov, wherein the outermost layer being a power layer as taught by Benedict, in order to improve signal quality (Benedict, [0033]).
Regarding Claim 9, Kim further discloses the printed circuit board (Fig 5) of claim 8, wherein the first lamination structure (70) is coupled to the second lamination structure (80) (through a lamination process after the first lamination structure (70) is formed and after the second lamination structure (80) is formed).
Claim 9 states “through a lamination process after the first lamination structure is formed and after the second lamination structure is formed”. In accordance to MPEP 2113, the method of forming the device is not germane to the issue of patentability of the device itself. Therefore, this limitation has not been given patentable weight. Please note that even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product, i.e. “through a lamination process after the first lamination structure is formed and after the second lamination structure is formed”, does not depend on its method of production, i.e. laminating after a specific earlier lamination. In re Thorpe, 227 USPQ 964, 966 (Federal Circuit 1985).
Regarding Claim 10, Kim further discloses the printed circuit board (Fig 5) of claim 8, wherein the first lamination structure (70) is located on top of the second lamination structure (80).
Regarding Claim 13, Kim further discloses the printed circuit board (Fig 5) the printed circuit board of claim 8, wherein the high speed (Abstract, Column 1, lines 30-48, Claim 1) signal (S1-S6) routing is separated (located in 70) from a power delivery plane (PWR is located in 80).
Regarding Claim 14, Kim further discloses the printed circuit board (Fig 5) of claim 8, wherein a quantity of layers (S1-S6) in the first lamination structure (70) is greater than a quantity of layers (S7-S8) in the second lamination structure (80).
Regarding Claim 15, Kim discloses a method (Column 3, lines 16-51; “PCB fabrication process” “merging” “drilled”) of manufacturing a printed circuit board (PCB) (Fig 5), comprising: selecting a first plurality of layers (S1-S6); laminating the first plurality of layers (S1-S6) together to form a first lamination structure (70); selecting a second plurality of layers (S7-S8 PWR); laminating the second plurality of layers together to form a second lamination structure (80); and laminating (Column 3, lines 16-51; “After merging these two separate PCB portions 70 and 80”) the first lamination structure (70) and the second lamination structure (80) together, wherein the first plurality of layers (S1-S6) is directed to high speed (Abstract, Column 1, lines 30-48, Claim 1) signal routing (S1-S6), the second plurality of layers (S7-S8 PWR) is directed to delivering power (see Fig 5 showing PWR layer) for the PCB, and the first lamination structure (70) and the second lamination structure (80) collectively form a multi-lamination structure (10).
Kim does not disclose wherein the second plurality of layers includes power layers and one of the power layers is an outermost layer of the multi-lamination structure.
Reynov (US 2022/0141952 A1) teaches of a printed circuit board (Fig 5), comprising: a first plurality (220(1)) of layers (104,106) laminated together, the first plurality of layers (220(1)) being directed to signal routing (106; [0035]); and a plurality group (220(2)) of layers (106,102) laminated together, the second plurality (220(2)) of layers being directed to delivering power (102; [0036]), wherein when the second plurality (220(2)) of layers are laminated to the first plurality (220(1)) of layers, the first plurality (220(1)) of layers and the second plurality (220(2)) of layers collectively form a multi- lamination structure (see Fig 5), and wherein the second plurality (220(2)) of layers includes power layers (102(1)-102(4)).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the board as disclosed by Kim, wherein the second plurality of layers includes power layers as taught by Reynov, in order to meet demands, provide a high-current board and form conductive paths capable of carrying higher amounts of current through the board necessitated by an increase power consumption (Reynov, [0001-0003,0016]).
Benedict (US 2024/0098898 A1) teaches of a printed circuit board (Fig 4A), comprising: a first plurality (upper plurality of layers as seen in Fig 4A) of layers laminated together, the first plurality (upper plurality of layers as seen in Fig 4A) of layers being directed to high speed ([0003,0022,0023,0046]) signal routing; and a second plurality (lower plurality of layers as seen in Fig 4A) of layers laminated together, the second plurality (lower plurality of layers as seen in Fig 4A) of layers being directed to delivering power (408; [0032-0033]), wherein when the second plurality (lower plurality of layers as seen in Fig 4A) of layers are laminated to the first plurality (upper plurality of layers as seen in Fig 4A) of layers, the first plurality (upper plurality of layers as seen in Fig 4A) of layers and the second plurality (lower plurality of layers as seen in Fig 4A) of layers collectively form a multi- lamination structure (400), and wherein the second plurality (lower plurality of layers as seen in Fig 4A) of layers includes one (408) of the power layer is an outermost layer (see Fig 4A) of the multi-lamination structure.
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the board with the power layers as taught by Kim in view of Reynov, wherein one of the power layers is an outermost layer of the multi-lamination structure as taught by Benedict, in order to improve signal quality (Benedict, [0033]).
Regarding Claim 16, Kim further discloses the method (Fig 5; Column 3, lines 16-51; “PCB fabrication process” “merging” “drilled”) of claim 15, further comprising: positioning the first lamination structure (70) on top of the second lamination structure (80) prior to the step of laminating (Column 3, lines 16-51) the first lamination structure and the second lamination structure together (see Fig 5 showing 70 over 80).
Regarding Claim 19, Kim further discloses the method (Fig 5; Column 3, lines 16-51; “PCB fabrication process” “merging” “drilled”) of claim 15, wherein the high speed (Abstract, Column 1, lines 30-48, Claim 1) signal (S1-S6) routing is separated (located in 70) from a power delivery plane (PWR is located in 80).
Regarding Claim 20, Kim in view of Reynov and Benedict teaches the limitations of the preceding claim and Kim discloses the limitations of the preceding claim and Kim further discloses the method (Fig 5) of claim 15, wherein the first plurality of layers (at 70) of layers includes layers (S-S6), and the second plurality of layers (at 80) of layers includes layers (PWR,S7-S8).
Kim does not explicitly disclose wherein the first plurality of layers includes 32 layers, and the second plurality of layers includes 12 layers.
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the method as taught by Kim in view of Reynov and Benedict, wherein the first plurality of layers includes 32 layers, and the second plurality of layers includes 12 layers, in order to provide sufficient wiring routing paths to meet a desired board application, in order to provide a desired electrical density within the board and to form adequate signal and power wirings, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8. Please note that in the instant application, page 11 [0066], Applicant has not disclosed any criticality for the claimed limitations.
Claim(s) 4, 11 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 10,595,394 B1) in view of Reynov (US 2022/0141952 A1) and Benedict (US 2024/0098898 A1) as applied to claims 1, 8 and 15 above, and further in view of Komiya (US 2002/0011662 A1).
Regarding Claim 4, Kim in view of Reynov and Benedict teaches the limitations of the preceding claim and Kim further discloses the printed circuit board (Fig 5) of claim 1, wherein the first group (70) of layers has a ball grid array area (see Fig 1 showing 44 on upper surface, which is part or area of the upper portion, equivalent to 70; Column 2, line 58-Column 3, line 51; “BGA”), the printed circuit board (10) has a through hole (see aperture going through layers at 40), and the through hole (40) extends through the first group (70) of layers and through the second group (80) of layers.
Kim does not explicitly disclose the printed circuit board has a through hole that is used for a power connection at the ball grid array area, and the through hole extends through the first group of layers and through the second group of layers.
Komiya (US 2002/0011662 A1) teaches of a printed circuit board (Fig 8), wherein a first group (801) of layers has a ball grid array area ([0024] “BGA”), the printed circuit board has a through hole (109) that is used for a power connection ([0024] “respectively connected via through-holes 109 to a power supply wiring layer 105”) at the ball grid array area (area under 101), and the through hole (109) extends through the first group of layers (layers of 801) and through the second group of layers (layers of 103).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the board as taught by Kim in view of Reynov and Benedict, wherein the printed circuit board has a through hole that is used for a power connection at the ball grid array area, and the through hole extends through the first group of layers and through the second group of layers as taught by Komiya, in order to provide power to the mounted component, to allow for current flow, to control inductance, reduce effects of noise and to control impedance (Komiya [0001-0008,0024, 0036,0043,0051]).
Regarding Claim 11, Kim in view of Reynov and Benedict teaches the limitations of the preceding claim and Kim further discloses the printed circuit board (Fig 5) of claim 8, wherein the first lamination structure (70) has a ball grid array area (see Fig 1 showing 44 on upper surface, which is part or area of the upper portion, equivalent to 70; Column 2, line 58-Column 3, line 51; “BGA”), each of the first lamination structure (70) and the second lamination structure (80) has a hole (see aperture going through layers at 40) extending therethrough.
Kim does not explicitly disclose a hole extending therethrough hat is used for a power connection at the ball grid array area.
Komiya (US 2002/0011662 A1) teaches of a printed circuit board (Fig 8), wherein a first group (801) of layers has a ball grid array area ([0024] “BGA”), the printed circuit board has a through hole (109) that is used for a power connection ([0024] “respectively connected via through-holes 109 to a power supply wiring layer 105”) at the ball grid array area (area under 101), and the through hole (109) extends through the first group of layers (layers of 801) and through the second group of layers (layers of 103).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the board as taught by Kim in view of Reynov and Benedict, wherein the printed circuit board has a hole hat is used for a power connection at the ball grid array area as taught by Komiya, in order to provide power to the mounted component, to allow for current flow, to control inductance, reduce effects of noise and to control impedance (Komiya [0001-0008,0024, 0036,0043,0051]).
Regarding Claim 17, Kim in view of Reynov and Benedict teaches the limitations of the preceding claim and Kim further discloses the method (Fig 5; Column 3, lines 16-51; “PCB fabrication process” “merging” “drilled”) of claim 15, wherein the first plurality of layers has a ball grid array area (see Fig 1 showing 44 on upper surface, which is part or area of the upper portion, equivalent to 70; Column 2, line 58-Column 3, line 51; “BGA”), and each of the first plurality of layers (S1-S6) and the second plurality of layers (S7-S8 PWR) has a through hole (40).
Kim does not explicitly disclose that is used for a power connection at the ball grid array area.
Komiya (US 2002/0011662 A1) teaches of a printed circuit board (Fig 8), wherein a first group (801) of layers has a ball grid array area ([0024] “BGA”), the printed circuit board has a through hole (109) that is used for a power connection ([0024] “respectively connected via through-holes 109 to a power supply wiring layer 105”) at the ball grid array area (area under 101), and the through hole (109) extends through the first group of layers (layers of 801) and through the second group of layers (layers of 103).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the method as taught by Kim in view of Reynov and Benedict, wherein a hole that is used for a power connection at the ball grid array area as taught by Komiya, in order to provide power to the mounted component, to allow for current flow, to control inductance, reduce effects of noise and to control impedance (Komiya [0001-0008,0024, 0036,0043,0051]).
Claim(s) 5, 12 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 10,595,394 B1) in view of Reynov (US 2022/0141952 A1) and Benedict (US 2024/0098898 A1) as applied to claims 1, 8 and 15 above, and further in view of Huang (US 2012/0132461 A1).
Regarding Claim 5, Kim in view of Reynov and Benedict teaches the limitations of the preceding claim and Kim discloses the limitations of the preceding claim.
Kim does not disclose the printed circuit board of claim 1, wherein the multi-lamination structure eliminates power planes introduced by micro cavity resonance.
Huang (US 2012/0132461 A1) teaches of a printed circuit board (Fig 2) wherein a multi-lamination structure (10-20) eliminates power planes introduced by micro cavity resonance (as power planes are 10 and 20, no cavities are formed in 10 or 20 to be avoided by passing vias that would create unwanted micro cavity resonances).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the board as taught by Kim in view of Reynov and Benedict, wherein the multi-lamination structure eliminates power planes introduced by micro cavity resonance as taught by Huang, in order to provide power to the mounted component and provide means to control temperatures (Huang, [0004, 0010-0016]) and furthermore since it has been held that rearranging parts of an invention involves only routine skill in the art, such as by having power planes on outer surfaces, the power sources are closer to mounted components. In re Japikse, 86 USPQ 70.
Regarding Claim 12, Kim in view of Reynov and Benedict teaches the limitations of the preceding claim and Kim discloses the limitations of the preceding claim.
Kim does not disclose the printed circuit board of claim 8, wherein the multi-lamination structure eliminates power planes introduced by micro cavity resonance.
Huang (US 2012/0132461 A1) teaches of a printed circuit board (Fig 2) wherein a multi-lamination structure (10-20) eliminates power planes introduced by micro cavity resonance (as power planes are 10 and 20, no cavities are formed in 10 or 20 to be avoided by passing vias that would create unwanted micro cavity resonances).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the board as taught by Kim in view of Reynov and Benedict, wherein the multi-lamination structure eliminates power planes introduced by micro cavity resonance as taught by Huang, in order to provide power to the mounted component and provide means to control temperatures (Huang, [0004, 0010-0016]) and furthermore since it has been held that rearranging parts of an invention involves only routine skill in the art, such as by having power planes on outer surfaces, the power sources are closer to mounted components. In re Japikse, 86 USPQ 70.
Regarding Claim 18, Kim in view of Reynov and Benedict teaches the limitations of the preceding claim and Kim discloses the limitations of the preceding claim.
Kim does not disclose the method of claim 15, wherein the multi-lamination structure eliminates power planes introduced by micro cavity resonance.
Huang (US 2012/0132461 A1) teaches of a printed circuit board (Fig 2) wherein a multi-lamination structure (10-20) eliminates power planes introduced by micro cavity resonance (as power planes are 10 and 20, no cavities are formed in 10 or 20 to be avoided by passing vias that would create unwanted micro cavity resonances).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the method taught by Kim in view of Reynov and Benedict, wherein the multi-lamination structure eliminates power planes introduced by micro cavity resonance as taught by Huang, in order to provide power to the mounted component and provide means to control temperatures (Huang, [0004, 0010-0016]) and furthermore since it has been held that rearranging parts of an invention involves only routine skill in the art, such as by having power planes on outer surfaces, the power sources are closer to mounted components. In re Japikse, 86 USPQ 70.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROSHN K VARGHESE whose telephone number is (571)270-7975. The examiner can normally be reached M-Th: 900 am-300 pm.
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/ROSHN K VARGHESE/Primary Examiner, Art Unit 2896