DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of claims 1-20 in the reply filed on 03/25/2026 is acknowledged.
Specification
The disclosure is objected to because of the following informalities: The specification fails to show corresponding explanation for reference numerals 242, 243, 340 as shown in Fig. 7. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4, 6, 12-15 & 17 are rejected under 35 U.S.C. 102(a)(1) and/or 102(a)(2) as being anticipated by KIM et al. (US Pub. 2021/0242175).
Regarding claim 1, KIM teaches a semiconductor memory device comprising:
a cell region MC on a cell substrate 10, and a peripheral circuit region PC on a peripheral circuit board 12 and connected to the cell region MC in a bonding manner (Fig. 3),
wherein the cell region MC includes
a plurality of gate electrodes 20 sequentially stacked on a first side of the cell substrate 10 (Fig. 3);
a first bypass cell contact plug (one of the 41, e.g., at the center) extended in a vertical direction in an extended region and connected to a first gate electrode of the plurality of gate electrodes 20 (Fig. 3);
a normal cell contact plug (an other one of 41, e.g. on the left) extended in the vertical direction in the extended region and connected to a second gate electrode of the plurality of gate electrodes 20 (Fig. 3);
a first metal wiring (one of ML1a, e.g. at the center) electrically connected to the first bypass cell contact plug (Fig. 3); and
a second metal wiring (one of ML2a, e.g., at the center) on the first metal wiring ML1a and electrically connected to the first metal wiring ML1a (Fig. 3),
wherein the peripheral circuit region PC includes
a plurality of circuit elements PTR on the peripheral circuit board 12 (Fig. 3);
a third metal wiring ML1b on a first circuit element PTR of the plurality of circuit elements PTR and electrically connected to the first circuit element PTR (Fig. 3); and
a fourth metal wiring ML2b on the third metal wiring ML1b and electrically connected to the third metal wiring ML1b (Fig. 3),
wherein the second metal wiring ML2a are connected with the fourth metal wiring ML2b through a first bypass path including a plurality of bonding metal pairs (PL1 & PL2, see Fig. 3).
Regarding claim 2, KIM teaches the semiconductor memory device of claim 1, wherein a wiring resistance between the first bypass cell contact plug 41 and the first circuit element PTR corresponds to a wiring resistance between the normal cell contact plug 41 and a second circuit element PTR of the plurality of circuit elements (Fig. 3).
Regarding claim 3, KIM teaches the semiconductor memory device of claim 1, wherein the first bypass path comprises: a first dummy metal wiring (one of the ML2a) on a same layer as the second metal wiring (ML2a); a first bonding metal (one of PL1) on the second metal wiring (M2L1); and a first dummy bonding metal (another of PL1) and a second dummy bonding metal (another of PL1) on the first dummy metal wiring (the one of ML2a) to be spaced apart from each other (note there are multiple of ML1a, ML2a, PL1 & PL2, similar to applicant’s device components shown in Fig. 7, and they meet the claim structural features as mapped above).
Regarding claim 4, KIM teaches the semiconductor memory device of claim 3, wherein the first bypass path comprises: a second dummy metal wiring (one of ML1b) on the same layer as the third metal wiring (ML1b); a second bonding metal (one of PL2) on the third metal wiring ML1b; and a third dummy bonding metal (another of PL2) and a fourth dummy bonding metal (one of PL1) on the second dummy metal wiring ML1b to be spaced apart from each other (Fig. 3, note there are multiple of ML1b, PL1 & PL2, similar to applicant’s device components shown in Fig. 7, and they meet the claim structural features as mapped above).
Regarding claim 6, KIM teaches the semiconductor memory device of claim 1, wherein the first bypass path is connected in an S shape that is bent twice or more in a vertical direction between the second metal wiring and the fourth metal wiring (Fig. 3).
Regarding claim 12, KIM teaches a semiconductor memory device comprising:
a plurality of gate electrodes 20 stacked on a cell substrate 10 in a vertical direction (Fig. 3);
a plurality of cell contact plugs 41 which extend in the vertical direction and have one end connected to each of the plurality of gate electrodes 20 (Fig. 3);
a plurality of first metal wirings ML1a on an other end of each of the plurality of cell contact plugs 41 and connected to each of the plurality of cell contact plugs 41 (Fig. 3);
a plurality of second metal wirings ML2a on the plurality of first metal wirings ML1a and electrically connected to each of the plurality of first metal wirings ML1a (Fig. 3);
a plurality of circuit elements PTR on a peripheral circuit board;
a plurality of third metal wirings ML1b on the plurality of circuit elements PTR and each connected to the plurality of circuit elements PTR (Fig. 3);
a plurality of fourth metal wirings ML2b on the plurality of third metal wirings ML1b and each electrically connected to the plurality of third metal wirings (Fig. 3); and
a plurality of bonding metal pairs (PL1 & PL2) on the plurality of second metal wirings and the plurality of fourth metal wirings, the plurality of bonding metal pairs including a plurality of first bonding metals PD1 and a plurality of second bonding metals PD2,
wherein each wiring resistance electrically connected from the plurality of cell contact plugs to the plurality of circuit elements is uniform (Fig. 3).
Regarding claim 13, KIM teaches the semiconductor memory device of claim 12, further comprising: a plurality of dummy bonding metal pairs (another pair/s of PL1 & PL2) on a same layer as the plurality of bonding metal pairs (PL1 & PL2) and electrically connected to at least one of the plurality of first bonding metals and at least one of the plurality of second bonding metals (when the transistors are on, the bonding metal pairs PL1 & PL2 are connected, see KIM’s Fig. 3).
Regarding claim 14, KIM teaches the semiconductor memory device of claim 13, further comprising: at least one first dummy metal wiring (e.g. one of ML2a) on a same layer as the plurality of second metal wirings (M2La); and at least one second dummy metal wiring (e.g. one of ML1b) on a same layer as the plurality of third metal wirings (ML1b, Fig. 3, any of said metal layers can perform as dummy wiring).
Regarding claim 15, KIM teaches the semiconductor memory device of claim 14, wherein any one of the plurality of first bonding metals PL1 is connected in series through the at least one first dummy metal wiring (M2La), the plurality of dummy bonding metal pairs (PL1 & PL2)_, and the at least one second dummy metal wiring (Ml1b), and is electrically connected any one of the plurality of second bonding metals PL2 (Fig. 3).
Regarding claim 17, KIM teaches the semiconductor memory device of claim 12, wherein wiring resistances between the plurality of cell contact plugs and the plurality of circuit elements are set to correspond to each other based on a length of a bypass path passing through at least two dummy bonding metal pairs (Fig. 3).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over KIM et al in view of HONG (10-2022-0149871) (US Pub. 2024/0159823 is provided for translation purposes).
Regarding claim 7, KIM teaches a semiconductor memory device comprising:
a plurality of gate electrodes 20 stacked on a cell substrate 10 in a vertical direction (Fig. 3);
a plurality of cell contact plugs 41 in the vertical direction and have one end connected to each of the plurality of gate electrodes 20 (Fig. 3);
a plurality of first metal wirings ML1a on an other end of each of the plurality of cell contact plugs 41 and connected to each of the plurality of cell contact plugs 41 (Fig. 3);
a plurality of second metal wirings ML2a on the plurality of first metal wirings ML1a and each electrically connected to the plurality of first metal wirings ML1a (Fig. 3);
a plurality of first bonding metals PL1 on the plurality of second metal wirings ML2a (Fig. 3);
a plurality of first dummy bonding metals (PL1 at the center) in a same layer as the plurality of first bonding metals (PL1 on the side);
a plurality of circuit elements PTR on a peripheral circuit board 12;
a plurality of third metal wirings ML1b on the plurality of circuit elements PTR and each connected to the plurality of circuit elements PTR (Fig. 3);
a plurality of fourth metal wirings ML2b on the plurality of third metal wirings ML1b and each electrically connected to the plurality of third metal wirings ML1b (Fig. 3);
a plurality of second bonding metals PL2 on the plurality of fourth metal wirings ML2b, each electrically connected to the plurality of fourth metal wirings ML2b, and each bonded to the plurality of first bonding metals PL1 (Fig. 3); and
a plurality of second dummy bonding metals (PL2 at the center) in the same layer as the plurality of second bonding metals (PL2 on the sides).
KIM is silent on wherein at least one first bonding metal and at least one second bonding metal are electrically connected through the plurality of first dummy bonding metals and the plurality of second dummy bonding metals. However, HONG discloses in Fig. 3 & Fig. 4-5 wherein at least one first bonding metal BP1 and at least one second bonding metal BP2 are electrically connected through the plurality of first dummy bonding metals (the other BP1) and the plurality of second dummy bonding metals (the other BP2, see Fig. 4-5). This has the advantage of efficiently detecting defects in contact, bonding structures and metal lines. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of KIM with the bonding structure arrangement, as taught by HONG, so as to efficiently detect defects within the semiconductor device.
Regarding claim 8, the combination of KIM and HONG teaches the semiconductor memory device of claim 7, further comprising: at least one first dummy metal wiring on a same layer as the plurality of second metal wirings; and at least one second dummy metal wiring on a same layer as the plurality of third metal wirings (KIM’s Fig. 3 & HONG’s Fig. 3).
Allowable Subject Matter
Claims 5, 9-11, 16 & 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TIMOR KARIMY whose telephone number is (571)272-9006. The examiner can normally be reached Monday - Friday: 8:30 AM -5:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TIMOR KARIMY/Primary Examiner, Art Unit 2818
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