DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
As per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
In responding to this Office action, the applicant is requested to include specific references (figures, paragraphs, lines, etc.) to the drawings/specification of the present application and/or the cited prior arts that clearly support any amendments/arguments presented in the response, to facilitate consideration of the amendments/arguments.
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on June 30, 2026 has been entered.
Response to Amendment
The amendment filed June 30, 2026 has been entered. Claims 1 and 13-30 remain pending in this application. Claims 26 and 28 drawn to non-elected invention have been withdrawn. Claims 1, 15, and 19 have been amended. No claims have been added. No new matter has been added.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 19-21, 24-25, 27, and 29-30 is/are rejected under 35 U.S.C. 103 as being unpatentable over non-patent literature Y. Kim, V. Seshadri, D. Lee, J. Liu and O. Mutlu, "A case for exploiting subarray-level parallelism (SALP) in DRAM," 2012 39th Annual International Symposium on Computer Architecture (ISCA), Portland, OR, USA, 2012, pp. 368-379 (hereafter Kim) in view of US 20200278923 A1 to Philip Jacob, et al. (hereafter Jacob).
Regarding Amended Independent Claim 1, Kim discloses a system, comprising:
a host device (Existence of a host device is inherent in a memory device, which must interface with a minimum of an input and output device);
a memory device (Disclosing a memory device: Kim, §2¶1) comprising:
a controller (Disclosing a controller: Kim, §4.3¶1) configured to:
receive, from the host device, a request for data stored in the memory device (Receiving a READ command from the host device: Kim, §4.3¶1);
activate a memory page of the memory device (Activating a page of memory: Kim, §1¶7).
Kim discloses a memory system wherein data may be distributed across different rows of the memory array, but fails to expressly disclose the further details of Claim 1, namely wherein the memory page is spread across a plurality of sections of a memory bank of the memory device, wherein each section is configured to be accessible via a separate memory address, and facilitate access to portions of the data stored in different memory rows across the plurality of sections of the memory bank based on the separate memory address. Jacob, however, discloses a distributed data memory system as in Claim 1, wherein:
wherein the memory page is spread across a plurality of sections of a memory bank of the memory device (Memory page is spread across multiple sub-arrays: Jacob, ¶[0032]),
wherein each section is configured to be accessible via a separate memory address (Wherein each section is accessed through different addresses for each tile: Jacob, ¶[0039]); and
facilitate access to portions of the data stored in different memory rows across the plurality of sections of the memory bank (Facilitating access to different memory rows across different tiles: Jacob, ¶[0038])
based on the separate memory address (Determining the individual tile addresses: Jacob, ¶[0039]).
Jacob teaches this distributed data system provides several advantages, including: avoiding page or column resource conflict during access to the data, high memory bandwidth, enabling simultaneous access to multiple data entries, and allowing independently activating segments of word lines in a sub-array (Jacob, ¶¶[0012-15]). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of this application to combine the distributed data system of Jacob with the distributed control sequence of Kim, with a reasonable expectation of success. Both inventions are well known in the field of distributed data memory arrays and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Amended Independent Claim 19, Kim discloses a method, comprising:
at a memory device (Disclosing a memory device: Kim, §2¶1), generating a programmable address map (Generating an address map: Kim, §8¶3)
Receiving, at the memory device, a plurality of requests for data (Receiving multiple requests for data: Kim, §1¶1);
in response to the plurality of requests (In response to a set of requests: Kim, §3¶2), activating sections of the memory bank not containing the data (Activating sections of memory not containing the data: Kim, §3¶2);
enabling
access to the data residing in different memory rows (Accessing data in different sections of the memory array: Kim, §3¶2)
within the sections that have been activated (Within the activated rows: Kim, §3¶2).
Kim discloses a memory system wherein data may be distributed across different rows of the memory array, but fails to expressly disclose the further details of Claim 1, namely wherein the memory page is spread across a plurality of sections of a memory bank of the memory device, wherein each section is configured to be accessible via a separate memory address, and using the programmable address map and separate memory addresses to access the data. Jacob, however, discloses a distributed data memory method as in Claim 1, configured:
to spread a memory page across a plurality of sections of a memory bank of the memory device (Memory page is spread across multiple sub-arrays: Jacob, ¶[0032]),
wherein each section is accessible via a separate memory address (Wherein each section is accessed through different addresses for each tile: Jacob, ¶[0039]);
using the programmable address map and separate memory addresses (Determining the individual tile addresses: Jacob, ¶[0039])
Jacob teaches this distributed data system provides several advantages, including: avoiding page or column resource conflict during access to the data, high memory bandwidth, enabling simultaneous access to multiple data entries, and allowing independently activating segments of word lines in a sub-array (Jacob, ¶¶[0012-15]). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of this application to combine the distributed data system of Jacob with the distributed control sequence of Kim, with a reasonable expectation of success. Both inventions are well known in the field of distributed data memory arrays and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 20, Kim discloses the method of claim 19, further comprising
latching the memory page in a page buffer that is shared across the sections of the memory bank (Latching the data cache data in a buffer from multiple sections: Kim, §1¶7).
Regarding Claim 21, Kim discloses the system of claim 1, wherein
the controller is further configured to selectively activate only a subset of the sections of the memory bank in response to the request (Disclosing selectively activating only a subset of the subarray: Kim, §5.2¶2).
Regarding Claim 24, Kim discloses the system of claim 1, wherein
the controller is further configured to close the memory page after the portions of the data stored across the sections of the memory bank are accessed (Teaching a ‘closed-row’ system in which a row is closed after reading: Kim, §9.3¶2).
Regarding Claim 25, Kim discloses the system of claim 1, wherein
the controller is further configured to issue write and read commands (Issuing read and write commands: Kim, §1¶9) to the memory page while the memory page is latched in a buffer shared across the sections of the memory bank (While accessing the sections across a buffer: Kim, §1¶9).
Regarding Claim 27, Kim discloses the system of claim 1, wherein the controller is further configured to
utilize a programmable address map (Generating an address map: Kim, §8¶3) to enable random access to data stored in different sections and rows of the memory page (Across different sections of a memory bank: Kim, §8¶3).
Regarding Claim 29, Kim discloses the system of claim 1, wherein the controller is further configured to
enable access to the portions of the data from different rows in the plurality of sections of the memory bank (Enabling access to different rows of data simultaneously: Kim, §4.3¶2).
Regarding Claim 30, Kim discloses the system of claim 1, wherein the controller is further configured to
issue a reduced activation for access that are spatially local (Disclosing reducing the activation time required for data located on the same row: Kim, §4.1¶1).
Claim(s) 13-15, 17-18, and 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Y. Kim, V. Seshadri, D. Lee, J. Liu and O. Mutlu, "A case for exploiting subarray-level parallelism (SALP) in DRAM," 2012 39th Annual International Symposium on Computer Architecture (ISCA), Portland, OR, USA, 2012, pp. 368-379 (hereafter Kim) and US 20200278923 A1 to Philip Jacob, et al. (hereafter Jacob) in view of US 8,314,807 B2 to Sukalpa Biswas, et al. (hereafter Biswas).
Regarding Claim 13, Kim discloses the system of claim 1, but fails to disclose the further limitations of Claim 13. Biswas, however, discloses a memory system, wherein the controller is further configured to
generate a priority queue including a plurality of requests including the request (Generating a priority queue for the requests: Biswas, col.6:27-32),
wherein the plurality of requests are scheduled (Scheduling requests based on the priority: Biswas, col.6:48-53)
based on a priority associated with each request of the plurality of requests (Ranking requested based on priority: Biswas, Figure 16),
an age of each request of the plurality of requests (Ranking based on age of the request: Biswas, col.7:21-25), or
a combination thereof (Ranking based on a combination of factors: Biswas, Figure 10).
Biswas teaches creating a priority queue allows the memory device to different traffic types in parallel and thus be capable of making better decisions about which memory operations to service prior to others based on the traffic type (Biswas, col.4:53-57). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the priority queue of Biswas with the cross section access method of Kim, with a reasonable expectation of success. Both inventions are well known in the field of memory data operation efficiency and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 14, Biswas discloses the system of claim 13, wherein the controller is configured to
compose the memory page based on the priority queue (Updating the memory page based on the priority queue: Biswas, col.13:61-14:4).
Regarding Amended Independent Claim 15, Kim discloses a memory device, comprising:
a controller (Disclosing a controller: Kim, §4.3¶1) configured to:
identify, based on the priority queue, a memory page (Activating a page of memory: Kim, §1¶7) of the memory device storing the data for a portion of the plurality of requests (Disclosing a memory device: Kim, §2¶1);
issue an activate command to activate the memory page storing the data for the portion of the plurality of requests (Activating a page of memory: Kim, §1¶7).
Kim does not expressly disclose the controller being configured to generate a priority queue. Biswas, however, discloses a controller configure to generate a priority queue for a plurality of requests for data stored in the memory device (Generating a priority queue for the requests: Biswas, col.6:27-32).
Biswas teaches generating a priority queue allows the memory device to different traffic types in parallel and thus be capable of making better decisions about which memory operations to service prior to others based on the traffic type (Biswas, col.4:53-57). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the priority queue of Biswas with the cross section access method of Kim, with a reasonable expectation of success. Both inventions are well known in the field of memory data operation efficiency and the combination of known inventions with predictable results is obvious and not patentable.
Kim discloses a memory system wherein data may be distributed across different rows of the memory array, but fails to expressly disclose the further details of Claim 1, namely wherein the memory page is spread across a plurality of sections of a memory bank of the memory device, wherein each section is configured to be accessible via a separate memory address, and facilitate access to portions of the data stored in different memory rows across the plurality of sections of the memory bank based on the separate memory address. Jacob, however, discloses a distributed data memory system as in Claim 1, wherein:
wherein the memory page is spread across a plurality of sections of a memory bank of the memory device (Memory page is spread across multiple sub-arrays: Jacob, ¶[0032]),
wherein each section is accessible via a separate memory address (Wherein each section is accessed through different addresses for each tile: Jacob, ¶[0039]); and
enable access to portions of the data stored across the sections of the memory bank (Enabling access to different memory rows across different tiles: Jacob, ¶[0038])
via the separate memory address for each section containing the portions of the data (Determining the individual tile addresses: Jacob, ¶[0039]).
Jacob teaches this distributed data system provides several advantages, including: avoiding page or column resource conflict during access to the data, high memory bandwidth, enabling simultaneous access to multiple data entries, and allowing independently activating segments of word lines in a sub-array (Jacob, ¶¶[0012-15]). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of this application to combine the distributed data system of Jacob with the distributed control sequence of Kim, with a reasonable expectation of success. Both inventions are well known in the field of distributed data memory arrays and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 17, Kim discloses the memory device of claim 15, wherein the controller is further configured to
close the memory page after the portions of the data stored across the sections of the memory bank are accessed (Teaching a ‘closed-row’ system in which a row is closed after reading: Kim, §9.3¶2).
Regarding Claim 18, Kim discloses the memory device of claim 15, wherein the controller is further configured to
enable access to the portions of the data from different rows in the sections of the memory bank (Enabling access to different rows of data simultaneously: Kim, §4.3¶2).
Regarding Claim 22, Kim discloses the system of claim 1 but fails to disclose the further limitations of Claim 22. Biswas, however, discloses a memory system as in Claim 1, wherein
the controller is further configured to maintain a priority queue for scheduling multiple requests for data stored in the memory device (Maintaining a priority queue for multiple requests for data operations in the memory array: Biswas, col.6:48-53).
Biswas teaches maintaining a priority queue allows the memory device to different traffic types in parallel and thus be capable of making better decisions about which memory operations to service prior to others based on the traffic type (Biswas, col.4:53-57). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the priority queue of Biswas with the cross section access method of Kim, with a reasonable expectation of success. Both inventions are well known in the field of memory data operation efficiency and the combination of known inventions with predictable results is obvious and not patentable.
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Y. Kim, V. Seshadri, D. Lee, J. Liu and O. Mutlu, "A case for exploiting subarray-level parallelism (SALP) in DRAM," 2012 39th Annual International Symposium on Computer Architecture (ISCA), Portland, OR, USA, 2012, pp. 368-379 (hereafter Kim), US 20200278923 A1 to Philip Jacob, et al. (hereafter Jacob), and US 8,314,807 B2 to Sukalpa Biswas, et al. (hereafter Biswas) in view of US 7,395,398 B2 to Min-kyu Kim (hereafter Min-Kyu Kim).
Regarding Claim 16, Kim discloses the memory device of claim 15 but fails to disclose the further limitations of Claim 16. Min-kyu Kim, however, discloses a memory array as in Claim 15, wherein the controller is further configured to
adjust a test clock frequency of the memory device (Teaching adjusting the clock frequency: Min-kyu Kim, col.6:7-18)
to increase a bandwidth associated with the memory address (Increasing the bandwidth associated with the address: Min-kyu Kim, col.9:5-8).
Min-kyu Kim teaches shifting the frequency of the clock signal prevents the deterioration in performance due to a slower read operation in the memory (Min-kyu Kim, col.9:8-12). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the performance enhancing variable clock speed of Min-kyu Kim with the cross section access method of Kim, with a reasonable expectation of success. Both inventions are well known in the field of efficient memory array reads and the combination of known inventions with predictable results is obvious and not patentable.
Claim(s) 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Y. Kim, V. Seshadri, D. Lee, J. Liu and O. Mutlu, "A case for exploiting subarray-level parallelism (SALP) in DRAM," 2012 39th Annual International Symposium on Computer Architecture (ISCA), Portland, OR, USA, 2012, pp. 368-379 (hereafter Kim) and US 20200278923 A1 to Philip Jacob, et al. (hereafter Jacob) in view of US 7,395,398 B2 to Min-kyu Kim (hereafter Min-Kyu Kim).
Regarding Claim 23, Kim discloses the system of claim 1 but fails to disclose the further limitations of Claim 22. Min-kyu Kim, however, discloses a memory system as in Claim 1 wherein
the controller is further configured to adjust a clock frequency of the memory device (Teaching adjusting the clock frequency: Min-kyu Kim, col.6:7-18) to increase a bandwidth associated with the memory addresses (Increasing the bandwidth associated with the address: Min-kyu Kim, col.9:5-8).
Min-kyu Kim teaches shifting the frequency of the clock signal prevents the deterioration in performance due to a slower read operation in the memory (Min-kyu Kim, col.9:8-12). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the performance enhancing variable clock speed of Min-kyu Kim with the cross section access method of Kim, with a reasonable expectation of success. Both inventions are well known in the field of efficient memory array reads and the combination of known inventions with predictable results is obvious and not patentable.
Response to Arguments
Applicant’s arguments filed with respect to the claims have been fully considered but are thought to be fully addressed by the modified and new grounds of rejections above. Applicant’s response is considered to be a bona fide attempt at a response and is being accepted as a complete response.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 10,372,358 B2 to Jan Van Lunteren: Disclosing a memory array with programmable memory partitions, simultaneous access operations, address mapping, and access scheduling.
US 2017/0178702 A1 to James E. Harris, et al.: Disclosing a distributed data storage scheme wherein multiple tiles are simultaneously accessed.
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/CHRISTOPHER LANE REECE/Examiner, Art Unit 2824 /HAN YANG/Primary Examiner, Art Unit 2824
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