DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
As per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
In responding to this Office action, the applicant is requested to include specific references (figures, paragraphs, lines, etc.) to the drawings/specification of the present application and/or the cited prior arts that clearly support any amendments/arguments presented in the response, to facilitate consideration of the amendments/arguments.
Response to Amendment
The amendment filed March 10, 2026 has been entered. Claims 1 and 13-30 remain pending in this application. Claims 2-12 previously cancelled at applicant’s request. The prior office action dated December 10, 2025 incorrectly described Claims 2-12 as withdrawn. Examiner thanks the Applicant for correcting the record. Claims 26 and 28 drawn to non-elected invention have been withdrawn. No claims have been amended. No claims have been added. No new matter has been added.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 19-21, 24-25, 27, and 29-30 rejected under 35 U.S.C. 102(a)(1) based upon a public use or sale or other public availability of the invention. The inventive concept was previously disclosed in non-patent literature Y. Kim, V. Seshadri, D. Lee, J. Liu and O. Mutlu, "A case for exploiting subarray-level parallelism (SALP) in DRAM," 2012 39th Annual International Symposium on Computer Architecture (ISCA), Portland, OR, USA, 2012, pp. 368-379 (hereafter Kim).
Regarding Amended Independent Claim 1, Kim discloses a system, comprising:
a host device (Existence of a host device is inherent in a memory device, which must interface with a minimum of an input and output device);
a memory device (Disclosing a memory device: Kim, §2¶1) comprising:
a controller (Disclosing a controller: Kim, §4.3¶1) configured to:
receive, from the host device, a request for data stored in the memory device (Receiving a READ command from the host device: Kim, §4.3¶1);
activate a memory page of the memory device (Activating a page of memory: Kim, §1¶7),
wherein the memory page is spread across sections of a memory bank of the memory device (Where the page of memory is spread across multiple rows or subarrays: Kim, §1¶7),
wherein each section is configured to be accessible via a memory address (Accessing the memory section via a memory address: Kim, §2.1¶3); and
facilitate access to portions of the data stored across the plurality of sections of the memory bank (Accessing portions of memory stored in separate sections of memory: Kim, §4.3¶2).
Regarding Amended Independent Claim 19, Kim discloses a method, comprising:
at a memory device (Disclosing a memory device: Kim, §2¶1), generating a programmable address map (Generating an address map: Kim, §8¶3)
to spread a memory page across sections of a memory bank of the memory device (Across different sections of a memory bank: Kim, §8¶3);
at the memory device, receiving a plurality of requests for data (Receiving multiple requests for data: Kim, §1¶1);
in response to the plurality of requests (In response to a set of requests: Kim, §3¶2), activating sections of the memory bank not containing the data (Activating sections of memory not containing the data: Kim, §3¶2);
using the programmable address map (Using the address map: Kim, §8¶3),
enabling
access to the data residing in different memory rows (Accessing data in different sections of the memory array: Kim, §3¶2)
within the sections that have been activated (Within the activated rows: Kim, §3¶2).
Regarding Amended Claim 20, Kim discloses the method of claim 19, further comprising
latching the memory page in a page buffer that is shared across the sections of the memory bank (Latching the data cache data in a buffer from multiple sections: Kim, §1¶7).
Regarding New Claim 21, Kim discloses the system of claim 1, wherein
the controller is further configured to selectively activate only a subset of the sections of the memory bank in response to the request (Disclosing selectively activating only a subset of the subarray: Kim, §5.2¶2).
Regarding New Claim 24, Kim discloses the system of claim 1, wherein
the controller is further configured to close the memory page after the portions of the data stored across the sections of the memory bank are accessed (Teaching a ‘closed-row’ system in which a row is closed after reading: Kim, §9.3¶2).
Regarding New Claim 25, Kim discloses the system of claim 1, wherein
the controller is further configured to issue write and read commands (Issuing read and write commands: Kim, §1¶9) to the memory page while the memory page is latched in a buffer shared across the sections of the memory bank (While accessing the sections across a buffer: Kim, §1¶9).
Regarding New Claim 27, Kim discloses the system of claim 1, wherein the controller is further configured to
utilize a programmable address map (Generating an address map: Kim, §8¶3) to enable random access to data stored in different sections and rows of the memory page (Across different sections of a memory bank: Kim, §8¶3).
Regarding New Claim 29, Kim discloses the system of claim 1, wherein the controller is further configured to
enable access to the portions of the data from different rows in the plurality of sections of the memory bank (Enabling access to different rows of data simultaneously: Kim, §4.3¶2).
Regarding New Claim 30, Kim discloses the system of claim 1, wherein the controller is further configured to
issue a reduced activation for access that are spatially local (Disclosing reducing the activation time required for data located on the same row: Kim, §4.1¶1).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 13-15, 17-18, and 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Y. Kim, V. Seshadri, D. Lee, J. Liu and O. Mutlu, "A case for exploiting subarray-level parallelism (SALP) in DRAM," 2012 39th Annual International Symposium on Computer Architecture (ISCA), Portland, OR, USA, 2012, pp. 368-379 (hereafter Kim) in view of US 8,314,807 B2 to Sukalpa Biswas, et al. (hereafter Biswas).
Regarding Claim 13, Kim discloses the system of claim 1, but fails to disclose the further limitations of Claim 13. Biswas, however, discloses a memory system, wherein the controller is further configured to
generate a priority queue including a plurality of requests including the request (Generating a priority queue for the requests: Biswas, col.6:27-32),
wherein the plurality of requests are scheduled (Scheduling requests based on the priority: Biswas, col.6:48-53)
based on a priority associated with each request of the plurality of requests (Ranking requested based on priority: Biswas, Figure 16),
an age of each request of the plurality of requests (Ranking based on age of the request: Biswas, col.7:21-25), or
a combination thereof (Ranking based on a combination of factors: Biswas, Figure 10).
Biswas teaches creating a priority queue allows the memory device to different traffic types in parallel and thus be capable of making better decisions about which memory operations to service prior to others based on the traffic type (Biswas, col.4:53-57). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the priority queue of Biswas with the cross section access method of Kim, with a reasonable expectation of success. Both inventions are well known in the field of memory data operation efficiency and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 14, Biswas discloses the system of claim 13, wherein the controller is configured to
compose the memory page based on the priority queue (Updating the memory page based on the priority queue: Biswas, col.13:61-14:4).
Regarding Amended Independent Claim 15, Kim discloses a memory device, comprising:
a controller (Disclosing a controller: Kim, §4.3¶1) configured to:
identify a memory page (Activating a page of memory: Kim, §1¶7) of the memory device storing the data for a portion of the plurality of requests (Disclosing a memory device: Kim, §2¶1);
issue an activate command to activate the memory page storing the data for the portion of the plurality of requests (Activating a page of memory: Kim, §1¶7),
wherein the memory page is spread across sections of a memory bank of the memory device (Where the page of memory is spread across multiple rows or subarrays: Kim, §1¶7),
wherein each section is accessible via a memory address (Accessing the memory section via a memory address: Kim, §2.1¶3); and
enable access to portions of the data stored across the sections of the memory bank (Accessing portions of memory stored in separate sections of memory: Kim, §4.3¶2).
Kim does not expressly disclose the controller being configured to generate a priority queue. Biswas, however, discloses a controller configure to generate a priority queue for a plurality of requests for data stored in the memory device (Generating a priority queue for the requests: Biswas, col.6:27-32).
Biswas teaches generating a priority queue allows the memory device to different traffic types in parallel and thus be capable of making better decisions about which memory operations to service prior to others based on the traffic type (Biswas, col.4:53-57). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the priority queue of Biswas with the cross section access method of Kim, with a reasonable expectation of success. Both inventions are well known in the field of memory data operation efficiency and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Amended Claim 17, Kim discloses the memory device of claim 15, wherein the controller is further configured to
close the memory page after the portions of the data stored across the sections of the memory bank are accessed (Teaching a ‘closed-row’ system in which a row is closed after reading: Kim, §9.3¶2).
Regarding Amended Claim 18, Kim discloses the memory device of claim 15, wherein the controller is further configured to
enable access to the portions of the data from different rows in the sections of the memory bank (Enabling access to different rows of data simultaneously: Kim, §4.3¶2).
Regarding New Claim 22, Kim discloses the system of claim 1 but fails to disclose the further limitations of Claim 22. Biswas, however, discloses a memory system as in Claim 1, wherein
the controller is further configured to maintain a priority queue for scheduling multiple requests for data stored in the memory device (Maintaining a priority queue for multiple requests for data operations in the memory array: Biswas, col.6:48-53).
Biswas teaches maintaining a priority queue allows the memory device to different traffic types in parallel and thus be capable of making better decisions about which memory operations to service prior to others based on the traffic type (Biswas, col.4:53-57). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the priority queue of Biswas with the cross section access method of Kim, with a reasonable expectation of success. Both inventions are well known in the field of memory data operation efficiency and the combination of known inventions with predictable results is obvious and not patentable.
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Y. Kim, V. Seshadri, D. Lee, J. Liu and O. Mutlu, "A case for exploiting subarray-level parallelism (SALP) in DRAM," 2012 39th Annual International Symposium on Computer Architecture (ISCA), Portland, OR, USA, 2012, pp. 368-379 (hereafter Kim) and US 8,314,807 B2 to Sukalpa Biswas, et al. (hereafter Biswas) in view of US 7,395,398 B2 to Min-kyu Kim (hereafter Min-Kyu Kim).
Regarding Amended Claim 16, Kim discloses the memory device of claim 15 but fails to disclose the further limitations of Claim 16. Min-kyu Kim, however, discloses a memory array as in Claim 15, wherein the controller is further configured to
adjust a test clock frequency of the memory device (Teaching adjusting the clock frequency: Min-kyu Kim, col.6:7-18)
to increase a bandwidth associated with the memory address (Increasing the bandwidth associated with the address: Min-kyu Kim, col.9:5-8).
Min-kyu Kim teaches shifting the frequency of the clock signal prevents the deterioration in performance due to a slower read operation in the memory (Min-kyu Kim, col.9:8-12). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the performance enhancing variable clock speed of Min-kyu Kim with the cross section access method of Kim, with a reasonable expectation of success. Both inventions are well known in the field of efficient memory array reads and the combination of known inventions with predictable results is obvious and not patentable.
Claim(s) 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Y. Kim, V. Seshadri, D. Lee, J. Liu and O. Mutlu, "A case for exploiting subarray-level parallelism (SALP) in DRAM," 2012 39th Annual International Symposium on Computer Architecture (ISCA), Portland, OR, USA, 2012, pp. 368-379 (hereafter Kim) in view of US 7,395,398 B2 to Min-kyu Kim (hereafter Min-Kyu Kim).
Regarding New Claim 23, Kim discloses the system of claim 1 but fails to disclose the further limitations of Claim 22. Min-kyu Kim, however, discloses a memory system as in Claim 1 wherein
the controller is further configured to adjust a clock frequency of the memory device (Teaching adjusting the clock frequency: Min-kyu Kim, col.6:7-18) to increase a bandwidth associated with the memory addresses (Increasing the bandwidth associated with the address: Min-kyu Kim, col.9:5-8).
Min-kyu Kim teaches shifting the frequency of the clock signal prevents the deterioration in performance due to a slower read operation in the memory (Min-kyu Kim, col.9:8-12). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the performance enhancing variable clock speed of Min-kyu Kim with the cross section access method of Kim, with a reasonable expectation of success. Both inventions are well known in the field of efficient memory array reads and the combination of known inventions with predictable results is obvious and not patentable.
Response to Arguments
Applicant's arguments filed March 10, 2026 have been fully considered but they are not persuasive.
Applicant begins his argument by explaining the purpose of the present invention, which is described as a system for providing complex page access in memory devices, such as hybrid-bonded memory (Applicant Arguments/Response: page 2, ¶2). This detailed description provides a clear overview of the intent of the invention. During examination, however, the examiner is required to give all terms their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification (See MPEP § 2111.01). A recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim.
In regards to Claim 1, Applicant traverses the finding of a host device being inherent in a memory device, suggesting the host device is not necessarily present (Applicant Arguments/Response: page 3, ¶1). This is an improperly narrow reading of the response. Both the present invention and the cited prior art Kim are describing memory systems, not a memory array disconnected from all input and output structures (See Claim 1 and Kim, page 368, §1, ¶1). Input and output structures are necessarily present in a memory system and those systems require a memory array to be embedded in a host device ("[I]n order to rely on inherency to establish the existence of a claim limitation in the prior art in an obviousness analysis – the limitation at issue necessarily must be present, or the natural result of the combination of elements explicitly disclosed by the prior art." PAR Pharmaceutical, Inc. v. TWI Pharmaceuticals, Inc., 773 F.3d 1195-96, 112 USPQ2d at 1952.).
Further, the burden of proof lies with the Applicant to rebut a finding of inherency (See MPEP § 2112.V: "[T]he PTO can require an applicant to prove that the prior art products do not necessarily or inherently possess the characteristics of his [or her] claimed product. Whether the rejection is based on ‘inherency’ under 35 U.S.C. 102, on ‘prima facie obviousness’ under 35 U.S.C. 103, jointly or alternatively, the burden of proof is the same." In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433-34 (CCPA 1977) (footnote and citation omitted).). Applicant fails to provide any evidence to meet this burden beyond the stated conclusion. Therefore, this argument is unpersuasive.
Applicant also argues Kim fails to disclose a memory page spread across sections of a memory bank of the memory device with each section accessible via a memory address (Applicant Arguments/Response: page 3, ¶2). Key to this argument is the distinction between ‘rows,’ as cited in the office action, and ‘sections,’ as worded in the claim. Applicant is permitted to be his or her own lexicographer, but that permission is limited to the present application and is an active requirement. To act as their own lexicographer, the applicant must clearly set forth a special definition of a claim term in the specification that differs from the plain and ordinary meaning it would otherwise possess. (CCS Fitness, Inc. v. Brunswick Corp., 288 F.3d 1359, 1366, 62 USPQ2d 1658, 1662 (Fed. Cir. 2002)). But where the specification is ambiguous as to whether the inventor used claim terms inconsistent with their ordinary meaning, the ordinary meaning will apply. (Merck & Co. v. Teva Pharms. USA, Inc., 395 F.3d 1364, 1370, 73 USPQ2d 1641, 1646 (Fed. Cir. 2005)). The word ‘section’ would be understood by a reasonable reader as, “a distinct part of a whole.” A row is a distinct part of a memory bank, as is an individual memory cell. Therefore, the disclosure of a page of memory spread across multiple rows (Kim, §1¶7) is sufficient to anticipate the limitation of a “memory page… spread across sections of a memory bank of the memory device.”
Applicant’s final argument with regards to the anticipation rejection of Claim 1 is the prior art fails to disclose a controller configured to “facilitate access to portions of the data stored across the plurality of sections of the memory bank.” This argument is unpersuasive under the same interpretation as the last. If a memory page stored across multiple rows constitutes data spread across multiple sections, as broadest reasonable interpretation requires the limitation be read, then accessing that page of data (Kim, §4.3¶2) anticipates accessing data stored across the plurality of sections of the memory bank.
Further, this limitation as written does not require the reading of the entire page of data, merely ‘portions’ of it. The portions accessed do not need to be spread across multiple sections, either. As long as the full page of data is spread across multiple sections, or rows, the portions accessed may share the same location. Applicant is attempting to differentiate Claim 1 from the prior art by citing features not present in that art, but the features upon which applicant relies are not recited in the rejected claim(s), either. Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
With regard to Claim 15, Applicant argues the obviousness rejection from the prior office action fails for two reasons. The first is that prior art Kim fails to disclose a page spread across multiple sections. This argument is unpersuasive for the same reasons previously given in regards to claim 1.
Applicant’s second argument with regard to claim 15 is that the motivation to combine prior art is too general and would not suggest combining the priority queue of Biswas with the cross-sectional access method of Kim (Applicant Argument/Response: page 5, ¶1). This argument is unpersuasive. Motivation to combine is not contingent solely on the art being modified but also on the problem the modification seeks to resolve. A person of ordinary skill is not confined to the specific field of the applicant’s endeavor but is presumed to look to all relevant prior art for solutions to the identified problem. Kim was well aware of the prioritization problem extant in complex memory systems (Kim, §9.3¶3), the same type of problem Biswas resolves (Biswas, col.4:52-57). It would have been obvious to one having ordinary skill in the art, prior to the effective filing date of this application, to apply the priority queue of Biswas (a known technique) to improve the cross-sectional access method of Kim (a similar device) in the same way, with a reasonable expectation of success.
With regard to Claim 19, Applicant argues prior art Kim only discloses an address map and not a programmable address map, as required in the claim (Applicant Argument/Response: page 6, ¶1). This argument is unpersuasive. The ordinary meaning of ‘programmable’ would be, ‘able to be programmed, written to, or updated.’ Kim states, “We use line-interleaving to map the physical address space onto the DRAM hierarchy.” (Kim, §8¶3). This discloses an active process of updating an address map, not merely reading a static pre-existing address map, an operation only possible if the address map is programmable.
Finally, Applicant argues it is internally inconsistent that the prior office action, “relies on the same cited portion of Kim (§ 312) [sic] both for ‘activating sections of memory not containing the data’ and for ‘accessing data in different sections of the memory array’ and ‘within the activated rows.’” This argument is also unpersuasive. The properly cited paragraph (Kim, §3¶2) includes an example of a series of steps in the operation of accessing data, including steps of activating sections of memory not containing the data and, separately, accessing data in different sections of the memory array within the activated rows. There is nothing inconsistent about citing the same reference for multiple concepts when those concepts are each described therein.
Although ultimately unpersuasive, Applicant's response is considered to be a bona fide attempt at a response and is being accepted as a complete response.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
• US 10,372,358 B2 to Jan Van Lunteren: Disclosing a memory array with programmable memory partitions, simultaneous access operations, address mapping, and access scheduling.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER LANE REECE whose telephone number is (571)272-0288. The examiner can normally be reached Monday - Friday 7:30am-5pm.
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/CHRISTOPHER LANE REECE/Examiner, Art Unit 2824 /HAN YANG/Primary Examiner, Art Unit 2824
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