Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Group IV in the reply filed on 8/5/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.03(a)).
Claims 4,6,8-10,14,16,19-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to nonelected Species I-III, V-VII claims, there being no allowable generic or linking claim.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
1. Claim(s) 1-3,5,7 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20210210497 A1 (Yang).
Regarding claim 1, Yang shows (Fig. 9C-10) a three-dimensional memory device, comprising:
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a base dielectric layer (32, para 98) disposed on a substrate (14, isolation layer supporting as a substrate, para 99);
a stack structure that includes a plurality of word lines (46, para 105) and a plurality of interlayer dielectric layers (32, para 98) that are alternately stacked on the base dielectric layer;
a bit line (60, para 105) that penetrates the stack structure and extends in a vertical direction perpendicular to a top surface of the substrate; and
a plurality of buried storage patterns (52, ovonic threshold switch material, para 93) interposed between the bit line and the word lines and spaced apart from each other in the vertical direction,
wherein the buried storage patterns surround a lateral surface of the bit line (tubular, para 85), wherein each of the buried storage patterns has a width in a horizontal direction parallel to the top surface of the substrate.
Yang does not show wherein the widths of the buried storage patterns increase with increasing vertical distance from the substrate.
However, the ordinary artisan would have recognized the widths of the buried storage patterns to be a result effective variable that can be changed to match critical bias voltage requirement (para 84). Thus, it would have been obvious to have the widths of the buried storage patterns varied according to the claimed widths, since optimum or workable ranges of such variables are discoverable through routine experimentation. See MPEP 2144.05 II.B.
Regarding claim 2, Yang shows (Fig. 9C-10) wherein the buried storage patterns include at least one of selenium (Se), tellurium (Te), arsenic (As), antimony (Sb), carbon (C), germanium (Ge), silicon (Si), or indium (In) (para 82).
Regarding claim 3, Yang shows (Fig. 9C-10) further comprising a plurality of interlayer patterns (53, spacers, para 105) that are disposed between the buried storage patterns (52) and corresponding word lines (46, para 46).
Regarding claim 5 or claim 7, Yang shows (Fig. 9C-10) further comprising a line pattern (56, para 105) that extends in the vertical direction between the bit line (60) and the stack structure (46, 32) and surrounds the lateral surface of the bit line.
2. Claim(s) 11-13,15,17-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20190035733 A1 (Park) in view of Yang.
Regarding claim 11, Park shows (Fig. 4) a three-dimensional memory device (100), comprising:
a substrate (10, para 44) that includes a cell array region (CAR, para 44) and a contact region (DTR+CTR, para 44) that extends from the cell array region;
a stack structure that includes a plurality of interlayer dielectric layers (32, para 51) and a plurality of word lines (EL, word line or electrode, para 41 and para 46) that are alternately stacked on the substrate, wherein the stack structure includes a plurality of pad portions (EL portion in DTR and CTR) that have a stepwise structure on the contact region;
a pad dielectric layer (portion of 32 in DTR and CTR) that covers the pad portions of the stack structure on the contact region;
a plurality of bit lines (BL, para 37);
an upper dielectric layer (42, para 64) that covers the stack structure; and
a plurality of cell contact plugs (CLP, para 64) that penetrate the upper dielectric layer and the pad dielectric layer (portion of 32 in DTR and CTR) on the contact region (DTR, CTR) and are connected to the word lines (EL, word line or electrode, para 41 and para 46),
wherein the word lines have lengths in a first direction parallel to the top surface of the substrate, wherein the lengths decrease with increasing vertical distance from the top surface of the substrate.
Park does not show the bit lines that penetrate the stack structure on the cell array region and extend in a vertical direction perpendicular to a top surface of the substrate;
a plurality of buried storage patterns interposed between the word lines and each of the bit lines and spaced apart from each other in the vertical direction, wherein the buried storage patterns surround a lateral surface of each of the bit lines;
wherein each of the buried storage patterns has a width in a horizontal direction parallel to the top surface of the substrate,
wherein the widths of the buried storage patterns increase with increasing vertical distance from the substrate.
Yang shows (Fig. 9C-12) the bit lines (60, para 105) that penetrate the stack structure (stack of 46, 32) on the cell array region (100, para 56) and extend in a vertical direction perpendicular to a top surface of the substrate;
a plurality of buried storage patterns (52, ovonic threshold switch material, para 93) interposed between the word lines (46, para 105) and each of the bit lines and spaced apart from each other in the vertical direction, wherein the buried storage patterns surround a lateral surface of each of the bit lines (tubular, para 85);
wherein each of the buried storage patterns has a width in a horizontal direction parallel to the top surface of the substrate.
It would have been obvious to one of ordinary skill in the art, at or before the effective filing date of the invention was made, to modify the invention of Park, including bit lines, with the invention of Yang.
The motivation to do so is that the combination produces vertical stacking of memory arrays with separate storage patterns around the same bit line.
Park in view of Yang does not show wherein the widths of the buried storage patterns increase with increasing vertical distance from the substrate.
However, the ordinary artisan would have recognized the widths of the buried storage patterns to be a result effective variable that can be changed to match critical bias voltage requirement (Yang, para 84). Thus, it would have been obvious to have the widths of the buried storage patterns varied according to the claimed widths, since optimum or workable ranges of such variables are discoverable through routine experimentation. See MPEP 2144.05 II.B.
Regarding claim 12, Park as previously modified by Yang shows wherein the buried storage patterns include at least one of selenium (Se), tellurium (Te), arsenic (As), antimony (Sb), carbon (C), germanium (Ge), silicon (Si), or indium (In) (Yang, para 82).
Regarding claim 13, Park as previously modified by Yang shows further comprising a plurality of interlayer patterns (Yang, 53, spacers, para 105) that are disposed between the buried storage patterns (Yang, 52) and corresponding word lines (Yang, 46, para 46).
Regarding claim 15 or claim 17, Park as previously modified by Yang shows further comprising a plurality of line patterns (Yang, 56 for each bit lines in Fig. 10) that extend in the vertical direction between the stack structure (Yang, 46, 32) and each of the bit lines (Yang, 60) and surround the lateral surface of each of the bit lines.
Regarding claim 18, Park as previously modified by Yang shows wherein the line patterns include carbon (C) [since 56 is made of tunneling dielectric layer (para 93) where tunneling dielectric layer is composed of carbon, (para 86)].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WASIUL HAIDER whose telephone number is (571)272-1554. The examiner can normally be reached M-F 9 a.m. - 6 p.m..
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/WASIUL HAIDER/Primary Examiner, Art Unit 2812
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