DETAILED ACTION
This action is responsive to the following communications: the Application filed January 19, 2024, and Response to election / restriction filed October 24, 2025.
Claims 1-17 are pending. Claims 1-7 are withdrawn from consideration as being drawn to non-elected inventions with traverse. Claims 8 and 14 are independent.
Notice of Pre-AIA or AIA Status
The present application is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on January 19, 2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Election/Restrictions
Applicant's election with traverse of Species 2 (claims 8-14) in the reply filed on 10/24/25 is acknowledged. The traversal is on the ground(s) that: (1) there is no search burden because Figure 4 and Figure 5 shows the same 4T-SRAM that does not have a low voltage storage node connected to the ground voltage as a conventional 6T-SRAM cell does; and (2) Species 1 and Species 2 partially overlap, and therefore are not distinct This is not found persuasive.
(1) A pull-down-less 4T-SRAM is not new, but instead is an old and thus is not a basis to assert any patentable distinction. The distinctions between Figure 4 and Figure 5 (as also expressed in claims 1-7 and claims 8-17) are the purportedly new write circuitry and read circuitry, respectively. Applicant explains in their originally filed Specification, paragraph 17 and 18, that Figure 4 shows “an embodiment of the invention” and Figure 5 shows “another embodiment of the invention, meaning Figures 4 and 5 are different (i.e., distinct) embodiments. As illustrated, and as related to claims 1-7, Figure 4 is directed to the write circuitry for a driverless 4T-SRAM; whereas, as illustrated and as related to claims 8-17, Figure 5 is directed to the read circuitry for a driverless 4T-SRAM. Read circuitry and write circuitry have recognized separate status in the memory art, as evinced by CPC G11C 7/1087, 1096 (write circuitry) and G11C 7/106 (read circuitry).
(2) “Overlap in scope,” as used in election of Species practice, does not mean partial overlap. Instead, the requirement that species “do not overlap in scope” means that one species does not read on the other, and vice versa. See MPEP 806.04(b); see also MPEP 806.04(f).
The requirement is still deemed proper and is therefore made FINAL.
Claims 1-7 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected species (i.e., Fig. 4), there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 10/24/25.
Drawings
The drawings are objected to because:
Figures 2-3B should be designated by a legend such as –Prior Art—because only that which is old is illustrated. See MPEP 608.02(g).
Applicant’s Figures 2-3B are prior art as evinced by Figure 5 in US 6,442,060, which was patented August 27, 2002 (more than one year before instant applicant's earliest effective filing date of the claimed invention).
Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of AIA 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 8-9, 11-14 and 16-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Leung et al. (US 6,442,060).
PNG
media_image1.png
1156
929
media_image1.png
Greyscale
Regarding independent claim 8 and its method independent claim 14, the claimed limitation(s) of memory device having data read latching circuit and discharging device is a well-known technology for a type of memory (e.g., SRAM) for its purpose. For support, of the above asserted facts, see for example, Leung et al. disclose a memory device, comprising:
a SRAM cell (FIG. 6: 500) comprising:
a cross-coupled pair of PMOS transistors (503 and 504) coupled to a supply voltage rail (Vcc) and two storage nodes (N1 and N2); and
two access transistors (501 and 502) responsive to a word line (WL) and coupled to the two storage nodes and a bit line pair (511 (BL) and 512 (BL#)); and
a read circuit comprising:
a latch (601) coupled between the supply voltage rail (Vcc) and a ground voltage rail (GND symbol) and having two output nodes (see 621 output node and 622 output node) that are coupled to the bit line pair respectively (BL and BL#); and
a discharge device (Fig. 6: 631 and 632) responsive to a first control line (EQ) for a predefined duration (see FIG. 7: 701 followed by performing a read operation 702 (see e.g., col. 7 lines 20-21)) and coupled to the two output nodes (see 601 (621 and 622)), the bit line pair (BL and BL#) and the ground voltage rail (GND symbol).
Further, regarding method claim 14, MPEP 2112.02(I) instructs examiners, “Under the principles of inherency, if a prior art device, in its normal and usual operation, would necessarily perform the method claimed, then the method claimed will be considered to be anticipated by the prior art device. When the prior art device is the same as a device described in the specification for carrying out the claimed method, it can be assumed the device will inherently perform the claimed process. In re King, 801 F.2d 1324, 231 USPQ 136 (Fed. Cir. 1986).” Here, the applied prior art product is identical to applicant’s disclosed product, and therefore is assumed, in accordance with MPEP 2112.02(I), to inherently perform the claimed process.
Regarding claim 9, which depends from claim 8, Leung et al. disclose the discharge device comprises: a first reset transistor (FIG. 6: 631) and a second reset transistor (Fig. 6: 632) responsive to the first control line for the predefined duration, wherein the first reset transistor is coupled to one of the two output nodes, one of the bit line pair and the ground voltage rail, and wherein the second reset transistor is coupled to the other output node of the two output nodes, the other bit line of the bit line pair and the ground voltage rail.
Regarding claims 11 and its method claim 16, which depends from claims 8 and 14, respectively, Leung et al. disclose the read circuit further comprises: an accelerating transistor (FIG. 6: 616) responsive to a second control line and coupled between the supply voltage rail and the latch (see FIG. 6 and accompanying disclosure). See also, MPEP 2112.02(I).
Regarding claim 12 and its method claim 17, which depends from claims 8 and 14, respectively, Leung et al. disclose upon activation of the word line, voltages of the two storage nodes are detected by the read circuit to be respectively a supply voltage and a floating voltage, wherein the floating voltage is greater than a ground voltage and less than the supply voltage, and wherein the floating voltage is obtained by detailed balanced leakage currents between a channel diffusion current with a reversed P-drain/N-well junction leakage current for one of the cross-coupled pair of PMOS transistors and a reversed N-drain/P-substrate junction leakage current for one of the two access transistors in connection with one of the two storage nodes having the floating voltage (see FIGS. 6-7 and accompanying disclosure, further the claimed junction leakage current is an inherent characteristic of CMOS transistors). See also, MPEP 2112.01(I), 2112.02(I) and 2114(II).
Regarding claim 13, which depends from claim 8, Leung et al. disclose after the activation of the word line, one of the two storage nodes originally having the floating voltage is refreshed to the ground voltage (see FIGS. 6 and 7: 701 and 702, i.e., refreshed by EQ after turning on VWL in 702).
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 10 and 15 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Leung et al. (US 6,442,060) in view of e.g., Sinangil et al. (US 2022/0359001).
Regarding claim 10 and its method claim 15, Leung et al. teach the limitations of claims 8 and 14, respectively.
Leung et al. do not explicitly disclose the read circuit further comprises: a tri-state buffer responsive to a second control line and having a data input node coupled to one of the two output nodes.
However, tri-state in output circuit in a memory device is a well-known technology for a type of memory for its purpose.
For support, of the above asserted facts, see for example, Sinangil et al. (US 2022/0359001), e.g., FIG. 3: 308 and accompanying disclosure.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize static random access memory used as configuration random access memory in data output with tri-state circuits because these conventional technology are well established in the art of the memory devices.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUNG IL CHO whose telephone number is (571)270-0137. The examiner can normally be reached M-Th, 7:30AM-5PM; Every other F, 7:30AM-4PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander G Sofocleous can be reached on 571-272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SUNG IL CHO/Primary Examiner, Art Unit 2825