DETAILED ACTION
This correspondence is in response to the communications received 01/21/2024. Claims 1-24 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/07/2024 has been considered by the examiner and made of record in the application file.
Applicant’s Claim to Figure Comparison
It is noted that this comparison is merely for the benefit of reviewers of this office action during prosecution, to allow for an understanding of the examiner’s interpretation of the Applicant’s independent claims as compared to disclosed embodiments in Applicant’s Figures. No response or comments are necessary from Applicant.
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Regarding claim 1, a bump structure (1), comprising:
a conductive pad (101) disposed on an active top surface (100a) of a semiconductor die (100, see Fig. 1);
a passivation layer (106) covering a perimeter of the conductive pad, wherein the passivation layer comprises an opening (106r) exposing a central portion of the conductive pad (see Fig. 1);
a first polymer layer (110) disposed on the passivation layer and in the opening, wherein the first polymer layer comprises a via opening (110t) partially exposing the central portion of the conductive pad (see Fig. 1);
a re-distribution layer (RDL) (210) disposed on the first polymer layer and patterned into a bump pad (210p) situated directly above the conductive pad, wherein the via opening is completely filled with the RDL and a RDL via is integrally formed with the bump pad (see Fig. 1);
a second polymer layer (120) disposed on the first polymer layer, wherein the second polymer layer covers a perimeter of the bump pad (see Fig. 1);
an island (120i) of the second polymer layer disposed at a central portion of the bump pad (see Fig. 1);
an under-bump metallization (UBM) layer (220) disposed on the bump pad, wherein the UBM layer covers the island and forms a bulge (220b) thereon (see Fig. 1); and
a bump (250) disposed on the UBM layer (see Fig. 1).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-24 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 10,964,655 B2, published 03/30/2021) in view of Lin et al. (US 10,804,153 B2, published 20/13/2020).
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Regarding claim 1, Figs. 1-6A and 7 of Chen disclose a bump structure (“FIG. 1 illustrates a cross-sectional view of package component 20. In accordance with some embodiments of the present disclosure, package component 20 is a device wafer including active devices and possibly passive devices, which are represented as integrated circuit devices 26. Device wafer 20 may include a plurality of chips 22 therein, with one of chips 22 illustrated”, col. 2, lines 37-43, further as seen in Fig. 7, 20/22 includes a bump “solder regions 62”, col. 7, line 38, therefore 20/22 is a bump structure) comprising:
a conductive pad (“Metal pads 42”, col. 4, line 32) disposed on an active top surface of a semiconductor die (as discussed previously, 22 is a chip which is equivalent to a semiconductor die, further “In accordance with some embodiments of the present disclosure, wafer 20 includes semiconductor substrate 24 and the features formed at a top surface of semiconductor substrate 24 ... Shallow Trench Isolation (STI) regions (not shown) may be formed in semiconductor substrate 24 to isolate the active regions in semiconductor substrate 24. Although not shown, through-vias may be formed to extend into semiconductor substrate 24, wherein the through-vias are used to electrically inter-couple the features on opposite sides of wafer 20”, col. 2 lines 55-67, and col. 3, lines 1-3, thus the top surface of 20/22 is an active surface);
a passivation layer (“patterned passivation layer 44”, col. 4, line 44) covering a perimeter of the conductive pad (as seen in Fig. 1, 44 covers a perimeter of 42), wherein the passivation layer comprises an opening exposing a central portion of the conductive pad (as seen in Fig. 1, 44 comprises “openings 46”, col. 4, line 49, exposing a central portion of 42);
a first polymer layer (“dielectric layer 48 is formed of a polymer such as polyimide, polybenzoxazole (PBO), benzocyclobutene (BCB), or the like … In subsequent discussion, dielectric layer 48 is referred to as polymer layer 48”, col. 4, lines 58-64) disposed on the passivation layer and in the opening (as seen in Fig. 2, 48 is disposed on 44 and in 46), wherein the first polymer layer comprises a via opening (as seen in Fig. 2, 46 becomes a via opening in 48 where “conductive traces 50 includes depositing a blanket metal seed layer, which may be a copper layer, forming a patterned plating mask (not shown) on the blanket metal seed layer, plating conductive traces 50, removing the patterned plating mask, and etching the portions of the blanket metal seed layer previously covered by the patterned plating mask. The remaining portions 50′ of the metal seed layer and the plated material 50″ in combination form conductive traces 50, which include via portions extending into polymer layer 48”, col. 5, lines 42-51, thus as 46 contains via portions of 50, it is a via opening) partially exposing the central portion of the conductive pad (as seen in Fig. 2, 46 exposes the central portion of 62);
a re-distribution layer (RDL) (“Conductive traces 50 are also referred to as Redistribution Lines (RDLs)”, col. 5, lines 38-39) disposed on the first polymer layer (as seen in Fig. 3, 50 is disposed on 48) and patterned into a bump pad (as previously discussed, 50 is patterned and as seen in Fig. 7, the horizontal portion of 50 serves as a bump pad upon which 62 is later formed) situated directly above the conductive pad (as seen in Fig. 3, 50 is situated directly above 42), wherein the via opening is completely filled with the RDL (as seen in Figs. 2 and 3, 46 is completely filled with 50) and a RDL via is integrally formed with the bump pad (as seen in Fig. 3, a via portion of 50 is integrally formed with the bump pad portion of 50);
a second polymer layer (“top polymer layer 52”, col. 5, line 54) disposed on the first polymer layer (as seen in Fig. 5, 52 is disposed on 48), wherein the second polymer layer covers a perimeter of the bump pad (as seen in Fig. 5, 52 covers a perimeter of 50 which therefore includes the bump pad portion of 50);
an island of the second polymer layer disposed at a central portion of the bump pad (Chen does not disclose an island of 52, however a secondary reference will be used to teach this limitation below);
an under-bump metallization (UBM) layer (“Under-Bump Metallurgies (UBMs) 60”, col. 6, lines 51-52) disposed on the bump pad (as seen in Fig. 7, 60 is disposed on the bump pad portion of 50), wherein the UBM layer covers the island and forms a bulge thereon (as Chen does not disclose an island, the secondary reference will also be used to teach this limitation below); and
a bump (“solder regions 62”, col. 7, line 38, as seen in Fig. 7, 62 is formed in the shape of a bump) disposed on the UBM layer (as seen in Fig. 7, 62 is on 60).
Chen fails to disclose “an island of the second polymer layer disposed at a central portion of the bump pad;
an under-bump metallization (UBM) layer disposed on the bump pad, wherein the UBM layer covers the island and forms a bulge thereon”.
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However, in a similar field of endeavor, Figs. 11a-12 of Lin teach an island (“islands 316”, col. 22, line 28, where “Islands 316 of compliant insulating layer 312 provide stress relief to stacked vias”, col. 23, lines 64-65) of the second polymer layer (“Adjacent openings 314 form islands 316 of insulating layer 312 over RDL 310”, col. 22, lines 25-28, where “Insulating layer 312 contains one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, or other material having similar insulating and structural properties”, col. 22, lines 14-16, Chen states “Polymer layer 52 may be formed of a same type of polymer (such as PBO or polyimide) as that of polymer layer 48”, col. 5, lines 65-67, and that “dielectric layer 48 is formed of a polymer such as polyimide, polybenzoxazole (PBO), benzocyclobutene 60 (BCB), or the like. In accordance with some embodiments of the present disclosure, dielectric layer 48 is formed of an inorganic dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, or the like”, col. 4, lines 58-63, thus 316 of Lin can also be formed of a polymer like 52 of Chen) disposed at a central portion of the bump pad (“Conductive layer 310”, col. 22, line 3, 310 of Lin is equivalent to 50 of Chen, as seen in Fig. 12 316 is disposed at a central portion of 310);
an under-bump metallization (UBM) layer (“UBM 318”, col. 22, lines 60-61, 318 of Lin is equivalent to 60 of Chen) disposed on the bump pad (as seen in Fig. 12, 318 is disposed on 310), wherein the UBM layer covers the island and forms a bulge thereon (as seen in Fig. 12, 318 covers 316 and forms a bulge thereon).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “an island of the second polymer layer disposed at a central portion of the bump pad;
an under-bump metallization (UBM) layer disposed on the bump pad, wherein the UBM layer covers the island and forms a bulge thereon” as taught by Lin in the system of Chen for the purpose of reducing internal device stress.
Regarding claim 2, Figs. 1-6A and 7 of Chen in combination with Figs. 11a-12 of Lin disclose the bump structure according to claim 1, Figs. 1-6A and 7 of Chen further disclose wherein the conductive pad comprises an aluminum pad (“Metal pads 42 may be aluminum pads or aluminum-copper pads, and other metallic materials may be used”, col. 4, lines 39-40).
Regarding claim 3, Figs. 1-6A and 7 of Chen in combination with Figs. 11a-12 of Lin disclose the bump structure according to claim 1, Figs. 1-6A and 7 of Chen further disclose wherein the passivation layer comprises a silicon nitride layer (“passivation layer 44 is a composite layer including a silicon oxide layer and a silicon nitride layer over the silicon oxide layer”, col. 4, lines 53-55).
Regarding claim 4, Figs. 1-6A and 7 of Chen in combination with Figs. 11a-12 of Lin disclose the bump structure according to claim 1, Figs. 1-6A and 7 of Chen further disclose wherein the first polymer layer comprises polyimide, PBO, phenolic resins, or epoxy resins (as discussed previously, 48 can be formed of polyimide or PBO).
Regarding claim 5, Figs. 1-6A and 7 of Chen in combination with Figs. 11a-12 of Lin disclose the bump structure according to claim 1, Figs. 1-6A and 7 of Chen further disclose wherein the second polymer layer comprises polyimide, PBO, phenolic resins, or epoxy resins (as discussed previously, 52 can be formed of the same material as 48 which includes polyimide or PBO).
Regarding claim 6, Figs. 1-6A and 7 of Chen in combination with Figs. 11a-12 of Lin disclose the bump structure according to claim 1, Figs. 1-6A and 7 of Chen further disclose wherein the RDL comprises copper (“the formation of conductive traces 50 includes depositing a blanket metal seed layer, which may be a copper layer”, col. 5, lines 42-44).
Regarding claim 7, Figs. 1-6A and 7 of Chen in combination with Figs. 11a-12 of Lin disclose the bump structure according to claim 1, Figs. 1-6A and 7 of Chen further disclose wherein the RDL via has a width that is smaller than a width of the conductive pad (as seen in Fig. 7, the via portion of 50 has a width that is smaller than a width of 42).
Regarding claim 8, Figs. 1-6A and 7 of Chen in combination with Figs. 11a-12 of Lin disclose the bump structure according to claim 1, Figs. 11a-12 of Lin further disclose wherein the island of the second polymer layer is disposed directly above the RDL via and the conductive pad (as seen in Fig. 12, 316 is disposed directly above the via portion of 310 and “conductive layer 132”, col. 21, line 52, where the via portion of 310 of Lin is equivalent to the via portion of 50 of Chen and 132 of Lin is equivalent to 42 of Chen).
Regarding claim 9, Figs. 1-6A and 7 of Chen in combination with Figs. 11a-12 of Lin disclose the bump structure according to claim 1, Figs. 11a-12 of Lin further disclose wherein the island of the second polymer layer has a width that is greater than a width of the RDL via (as seen in Fig. 12, the widest portion of 316 has a width that is greater than a width of the narrowest portion of the via portion of 310 where the via portion of 310 of Lin is equivalent to the via portion of 50 of Chen).
Regarding claim 10, Figs. 1-6A and 7 of Chen in combination with Figs. 11a-12 of Lin disclose the bump structure according to claim 1, Figs. 11a-12 of Lin further disclose wherein the island of the second polymer layer has a width that is smaller than a width of the conductive pad (as seen in Fig. 12, 316 has a width that is smaller than a width of “conductive layer 132”, col. 21, line 52, where 132 of Lin is equivalent to 42 of Chen).
Regarding claim 11, Figs. 1-6A and 7 of Chen in combination with Figs. 11a-12 of Lin disclose the bump structure according to claim 1, Figs. 11a-12 of Lin further disclose (“UBM 318 can be a multiple metal stack with adhesion layer, barrier layer, and seed or wetting layer”, col. 22, lines 63-64, where 318 of Lin is equivalent to 60 of Chen).
Regarding claim 12, Figs. 1-6A and 7 of Chen in combination with Figs. 11a-12 of Lin disclose the bump structure according to claim 1, Figs. 11a-12 of Lin further disclose wherein the bump comprises Sn, Al, Ni, Au, Ag, Pb, Bi, Cu, solder, or any combinations thereof (“The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof”, col. 23, lines 26-27).
Regarding claim 13, Figs. 1-6A, 7, and 24 of Chen disclose a method for forming a bump structure (“FIG. 1 illustrates a cross-sectional view of package component 20. In accordance with some embodiments of the present disclosure, package component 20 is a device wafer including active devices and possibly passive devices, which are represented as integrated circuit devices 26. Device wafer 20 may include a plurality of chips 22 therein, with one of chips 22 illustrated”, col. 2, lines 37-43, further as seen in Fig. 7, 20/22 includes a bump “solder regions 62”, col. 7, line 38, therefore 20/22 is a bump structure, further, “The corresponding processes are also reflected schematically in the process flow 200 as shown in FIG. 24”, col. 2, lines 34-36), comprising:
forming a conductive pad (“Metal pads 42 are formed”, col. 4, line 32) on an active top surface of a semiconductor die (as discussed previously, 22 is a chip which is equivalent to a semiconductor die, further “In accordance with some embodiments of the present disclosure, wafer 20 includes semiconductor substrate 24 and the features formed at a top surface of semiconductor substrate 24 ... Shallow Trench Isolation (STI) regions (not shown) may be formed in semiconductor substrate 24 to isolate the active regions in semiconductor substrate 24. Although not shown, through-vias may be formed to extend into semiconductor substrate 24, wherein the through-vias are used to electrically inter-couple the features on opposite sides of wafer 20”, col. 2 lines 55-67, and col. 3, lines 1-3, thus the top surface of 20/22 is an active surface);
forming a passivation layer (“A patterned passivation layer 44 is formed over interconnect structure 32”, col. 4, lines 44-45) covering a perimeter of the conductive pad (as seen in Fig. 1, 44 covers a perimeter of 42), wherein the passivation layer comprises an opening exposing a central portion of the conductive pad (as seen in Fig. 1, 44 comprises “openings 46”, col. 4, line 49, exposing a central portion of 42);
forming a first polymer layer (“dielectric layer 48 is formed of a polymer such as polyimide, polybenzoxazole (PBO), benzocyclobutene (BCB), or the like … In subsequent discussion, dielectric layer 48 is referred to as polymer layer 48”, col. 4, lines 58-64) on the passivation layer and in the opening (as seen in Fig. 2, 48 is disposed on 44 in 46), wherein the first polymer layer comprises a via opening (as seen in Fig. 2, 46 becomes a via opening in 48 where “conductive traces 50 includes depositing a blanket metal seed layer, which may be a copper layer, forming a patterned plating mask (not shown) on the blanket metal seed layer, plating conductive traces 50, removing the patterned plating mask, and etching the portions of the blanket metal seed layer previously covered by the patterned plating mask. The remaining portions 50′ of the metal seed layer and the plated material 50″ in combination form conductive traces 50, which include via portions extending into polymer layer 48”, col. 5, lines 42-51, thus as 46 contains via portions of 50, it is a via opening) partially exposing the central portion of the conductive pad (as seen in Fig. 2, 46 exposes the central portion of 62);
forming a re-distribution layer (RDL) (“Fig. 3 illustrates the formation of conductive traces 50. Conductive traces 50 are also referred to as Redistribution Lines (RDLs)”, col. 5, lines 37-38) on the first polymer layer (as seen in Fig. 3, 50 is disposed on 48) and patterned into a bump pad (as previously discussed, 50 is patterned and as seen in Fig. 7, the horizontal portion of 50 serves as a bump pad upon which 62 is later formed) situated directly above the conductive pad (as seen in Fig. 3, 50 is situated directly above 42), wherein the via opening is completely filled with the RDL (as seen in Figs. 2 and 3, 46 is completely filled with 50) and a RDL via is integrally formed with the bump pad (as seen in Fig. 3, a via portion of 50 is integrally formed with the bump pad portion of 50);
forming a second polymer layer (“FTG. 4A illustrates the formation of top polymer layer 52”, col. 5, line 54) on the first polymer layer (as seen in Fig. 5, 52 is on 48), wherein the second polymer layer covers a perimeter of the bump pad (as seen in Fig. 5, 52 covers a perimeter of 50 which therefore includes the bump pad portion of 50);
forming an island of the second polymer layer at a central portion of the bump pad (Chen does not disclose an island of 52, however a secondary reference will be used to teach this limitation below);
forming an under-bump metallization (UBM) layer (“FIG. 6A illustrates the formation of Under-Bump Metallurgies (UBMs) 60”, col. 6, lines 51-52) on the bump pad (as seen in Fig. 7, 60 is disposed on the bump pad portion of 50), wherein the UBM layer covers the island and forms a bulge thereon (as Chen does not disclose an island, the secondary reference will also be used to teach this limitation below); and
forming a bump (“FIG. 7 illustrates the formation of solder regions 62”, col. 7, line 38) on the UBM layer (as seen in Fig. 7, 62 is on 60).
Chen fails to disclose “forming an island of the second polymer layer at a central portion of the bump pad;
forming an under-bump metallization (UBM) layer on the bump pad, wherein the UBM layer covers the island and forms a bulge thereon”.
However, in a similar field of endeavor, Figs. 11a-12 of Lin teach forming an island (“Adjacent openings 314 form islands 316 of insulating layer 312 over RDL 310”, col. 22, lines 27-28, where “Islands 316 of compliant insulating layer 312 provide stress relief to stacked vias”, col. 23, lines 64-65) of the second polymer layer (“Insulating layer 312 contains one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, or other material having similar insulating and structural properties”, col. 22, lines 14-16, Chen states “Polymer layer 52 may be formed of a same type of polymer (such as PBO or polyimide) as that of polymer layer 48”, col. 5, lines 65-67, and that “dielectric layer 48 is formed of a polymer such as polyimide, polybenzoxazole (PBO), benzocyclobutene 60 (BCB), or the like. In accordance with some embodiments of the present disclosure, dielectric layer 48 is formed of an inorganic dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, or the like”, col. 4, lines 58-63, thus 316 of Lin can also be formed of a polymer like 52 of Chen) at a central portion of the bump pad (“Conductive layer 310”, col. 22, line 3, 310 of Lin is equivalent to 50 of Chen, as seen in Fig. 12 316 is disposed at a central portion of 310);
forming an under-bump metallization (UBM) layer pad (“Corrugated UBM 318 is formed in vias 314 and directly contacts RDL 310”, col. 22, lines 62-63) on the bump pad (as seen in Fig. 12, 318 is disposed on 310), wherein the UBM layer covers the island and forms a bulge thereon (as seen in Fig. 12, 318 covers 316 and forms a bulge thereon).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “forming an island of the second polymer layer at a central portion of the bump pad;
forming an under-bump metallization (UBM) layer on the bump pad, wherein the UBM layer covers the island and forms a bulge thereon” as taught by Lin in the system of Chen for the purpose of reducing internal device stress.
Regarding claim 14, Figs. 1-6A, 7, and 24 of Chen in combination with Figs. 11a-12 of Lin disclose the method according to claim 13, Figs. 1-6A, 7, and 24 of Chen further disclose wherein the conductive pad comprises an aluminum pad (“Metal pads 42 may be aluminum pads or aluminum-copper pads, and other metallic materials may be used”, col. 4, lines 39-40).
Regarding claim 15, Figs. 1-6A, 7, and 24 of Chen in combination with Figs. 11a-12 of Lin disclose the method according to claim 13, Figs. 1-6A, 7, and 24 of Chen further disclose wherein the passivation layer comprises a silicon nitride layer (“passivation layer 44 is a composite layer including a silicon oxide layer and a silicon nitride layer over the silicon oxide layer”, col. 4, lines 53-55).
Regarding claim 16, Figs. 1-6A, 7, and 24 of Chen in combination with Figs. 11a-12 of Lin disclose the method according to claim 13, Figs. 1-6A, 7, and 24 of Chen further disclose wherein the first polymer layer comprises polyimide, PBO, phenolic resins, or epoxy resins (as discussed previously, 48 can be formed of polyimide or PBO).
Regarding claim 17, Figs. 1-6A, 7, and 24 of Chen in combination with Figs. 11a-12 of Lin disclose the method according to claim 13, Figs. 1-6A, 7, and 24 of Chen further disclose wherein the second polymer layer comprises polyimide, PBO, phenolic resins, or epoxy resins (as discussed previously, 52 can be formed of the same material as 48 which includes polyimide or PBO).
Regarding claim 18, Figs. 1-6A, 7, and 24 of Chen in combination with Figs. 11a-12 of Lin disclose the method according to claim 13, Figs. 1-6A, 7, and 24 of Chen further disclose wherein the RDL comprises copper (“the formation of conductive traces 50 includes depositing a blanket metal seed layer, which may be a copper layer”, col. 5, lines 42-44).
Regarding claim 19, Figs. 1-6A, 7, and 24 of Chen in combination with Figs. 11a-12 of Lin disclose the method according to claim 13, Figs. 1-6A, 7, and 24 of Chen further disclose wherein the RDL via has a width that is smaller than a width of the conductive pad (as seen in Fig. 7, the via portion of 50 has a width that is smaller than a width of 42).
Regarding claim 20, Figs. 1-6A, 7, and 24 of Chen in combination with Figs. 11a-12 of Lin disclose the method according to claim 13, Figs. 11a-12 of Lin further disclose wherein the island of the second polymer layer is disposed directly above the RDL via and the conductive pad (as seen in Fig. 12, 316 is disposed directly above the via portion of 310 and “conductive layer 132”, col. 21, line 52, where the via portion of 310 of Lin is equivalent to the via portion of 50 of Chen and 132 of Lin is equivalent to 42 of Chen).
Regarding claim 21, Figs. 1-6A, 7, and 24 of Chen in combination with Figs. 11a-12 of Lin disclose the method according to claim 13, Figs. 11a-12 of Lin further disclose wherein the island of the second polymer layer has a width that is greater than a width of the RDL via (as seen in Fig. 12, the widest portion of 316 has a width that is greater than a width of the narrowest portion of the via portion of 310 where the via portion of 310 of Lin is equivalent to the via portion of 50 of Chen).
Regarding claim 22, Figs. 1-6A, 7, and 24 of Chen in combination with Figs. 11a-12 of Lin disclose the method according to claim 13, Figs. 11a-12 of Lin further disclose wherein the island of the second polymer layer has a width that is smaller than a width of the conductive pad (as seen in Fig. 12, 316 has a width that is smaller than a width of “conductive layer 132”, col. 21, line 52, where 132 of Lin is equivalent to 42 of Chen).
Regarding claim 23, Figs. 1-6A, 7, and 24 of Chen in combination with Figs. 11a-12 of Lin disclose the method according to claim 13, Figs. 11a-12 of Lin further disclose (“UBM 318 can be a multiple metal stack with adhesion layer, barrier layer, and seed or wetting layer”, col. 22, lines 63-64, where 318 of Lin is equivalent to 60 of Chen).
Regarding claim 24, Figs. 1-6A, 7, and 24 of Chen in combination with Figs. 11a-12 of Lin disclose the method according to claim 13, Figs. 11a-12 of Lin further disclose wherein the bump comprises Sn, Al, Ni, Au, Ag, Pb, Bi, Cu, solder, or any combinations thereof (“The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof”, col. 23, lines 26-27).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BENJAMIN M KUPP whose telephone number is (571)272-5608. The examiner can normally be reached Monday - Friday, 7:00 am - 4:00 pm PT.
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/BENJAMIN MICHAEL KUPP/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
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