Prosecution Insights
Last updated: October 01, 2026
Application No. 18/418,419

SEMICONDUCTOR PACKAGE STRUCTURE, METHOD OF FORMING THE SAME AND SEMICONDUCTOR PACKAGE ASSEMBLY HAVING THE SAME

Non-Final OA §102
Filed
Jan 22, 2024
Priority
Feb 14, 2023 — provisional 63/484,760
Examiner
HO, ANTHONY
Art Unit
2817
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
MediaTek Inc.
OA Round
1 (Non-Final)
91%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
94%
With Interview

Examiner Intelligence

Grants 91% — above average
91%
Career Allowance Rate
1057 granted / 1163 resolved
+22.9% vs TC avg
Minimal +3% lift
Without
With
+2.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
18 currently pending
Career history
1178
Total Applications
across all art units

Statute-Specific Performance

§101
2.5%
-37.5% vs TC avg
§103
35.8%
-4.2% vs TC avg
§102
37.1%
-2.9% vs TC avg
§112
16.3%
-23.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1163 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Claims 13-29 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected invention, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on May 19, 2026. Applicant's election with traverse of Group I, claims 1-12, in the reply filed on May 19, 2026 is acknowledged. The traversal is on the ground(s) that the claims are drawn to closely related aspects of a single inventive concept and share common technical features. This is not found persuasive because the Requirement for Restriction/Election mailed March 19, 2026 shows how each of the inventions are independent or distinct. The requirement is still deemed proper and is therefore made FINAL. Information Disclosure Statement The information disclosure statement (IDS) submitted on June 23, 2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-4, 6-8, and 10-12 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Arvin et al (US Pub 2017/0162436). In re claim 1, Arvin et al discloses a semiconductor package structure (i.e. see at least Figure 7, paragraphs 0024, 0033-0034), comprising: a first component (i.e. 100); a bonding structure on the first component, the bonding structure comprising: a copper base (i.e. 150) disposed on the first component; and copper protruding portions (i.e. 170) disposed on the copper base; a second component (i.e. 200) connected to the first component; and a copper connector (i.e. 210 or 220) on the second component, wherein the second component is connected to the first component by bonding the copper protruding portions to the copper connector, and the copper protruding portions are in contact with the copper connector (i.e. see at least Figures 6 and 7; paragraphs 0031-0032). In re claim 2, Arvin et al discloses wherein the first component is a die, a chip or a system-on-chip (SOC) (i.e. see at least paragraphs 0003 and 0024). In re claim 3, Arvin et al discloses wherein the second component is at least a package substrate or an interposer substrate, and the copper connector is a copper pad (i.e. see at least Figures 7 and 9; paragraph 0024). In re claim 4, Arvin et al discloses wherein the copper protruding portions and the copper connector form a fused layer (i.e. 230) having copper nano- pillars (i.e. see at least Figure 7; paragraph 0032). In re claim 6, Arvin et al discloses wherein an average diameter of the copper protruding portions is within a range of about 20 nm to about 200 nm (i.e. see at least paragraph 0028). In re claim 7, Arvin et al discloses wherein the bonding structure on the first component (i.e. 100) is referred to as a first bonding structure and comprises a first copper base (i.e. 150) and first copper protruding portions (i.e. 170), and the copper connector on the second component (i.e. 200) is a second bonding structure, wherein the second bonding structure comprises: a second copper base (i.e. 210) disposed on the second component; and second copper protruding portions (i.e. 220) disposed on the second copper base (i.e. see at least Figure 6). In re claim 8, Arvin et al discloses wherein the first copper protruding portions are staggered with respect to the second copper protruding portions and in direct contact with the second copper protruding portions when the first bonding structure is bonded to the second bonding structure (i.e. see at least Figures 6 and 7). In re claim 10, Arvin et al discloses wherein the second component is at least a package substrate (i.e. see at least Figure 7). In re claim 11, Arvin et al discloses wherein the first component is a die, and the bonding structure is formed on a backside of the die, wherein the copper base is in direct contact with the backside of the die (i.e. see at least Figures 6 and 7). In re claim 12, Arvin et al discloses wherein the second component is a heat spreader or an interposer substrate, and the first bonding structure on the die is bonded to the second bonding structure on the second component through direct contact between the first copper protruding portions and the second copper protruding portions (i.e. see at least Figures 6 and 7). Allowable Subject Matter Claims 5 and 9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTHONY HO whose telephone number is (571)270-1432. The examiner can normally be reached 9AM - 5PM, Monday-Friday. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached at 571-272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ANTHONY HO/Primary Examiner, Art Unit 2817
Read full office action

Prosecution Timeline

Jan 22, 2024
Application Filed
Sep 01, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
91%
Grant Probability
94%
With Interview (+2.6%)
2y 3m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1163 resolved cases by this examiner. Grant probability derived from career allowance rate.

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