DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1, 2, 7-9, and 14-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Farbiz et al. US 2019/0073440 A1 (“Farbiz”).
As to claim 1, Farbiz discloses a semiconductor device comprising at least a first cell and a second cell (Paragraphs 5-7 – e.g., cells of a floorplan), each of the first and second cells comprising:
a first well of a first conductivity type (Figure 3 or Paragraphs 7 or 42 – e.g., a P-well or an N-well);
a second well in the first well, wherein the second well has a second conductivity type opposite the first conductivity type (Figure 3 or Paragraphs 7 or 42 – e.g., a N+ or P+ region within the P-well or N-well); and
a discharge pin connected to the second well (Paragraphs 68-72 – e.g., ESD transistors/protection, used with the materials and dopants of the cells/wells); wherein
the semiconductor device further comprises a discharge path connected between the discharge pins of the first and second cells, such that the second wells of the first and second cells are on a same electric potential (Paragraphs 68-72 – e.g., ESD transistors/protection connected to at least a ground potential, see below).
Farbiz teaches cells and ESD protection elements, but does not explicitly show cells with ESDs configured with a same potential. However, it would have been obvious to one having ordinary skill in the art at the time the invention was made to arrange cells with ESD protection connected to a common ground because doing so would allow cells within a power domain to be protected from electrical surges/shorts.
As to claim 2, Farbiz discloses the device of claim 1. Farbiz further discloses wherein the first well is a deep N-well, and the second well is an isolated P-well region arranged within the deep N-well (Figure 3 or Paragraphs 7 or 42 – e.g., a P+ region within a N-well region).
As to claim 7, Farbiz discloses the device of claim 1. Farbiz further discloses wherein the first cell further comprises at least a transistor arranged in the second well (Figure 3 – e.g., transistor gate stripes, Paragraph 8 – e.g., ESD transistors between transistor gate stripes).
Claims 8, 9, 14, and 15 recite elements similar to claims 1, 2, and 7, and are rejected for the same reasons.
As to claim 16, Farbiz discloses the device of claim 15. Farbiz further discloses wherein the first cell and the second cell are each a standard cell and/or a tap-less cell with deep N-well (Paragraphs 5-7 – e.g., cells of a floorplan, Figure 3 or Paragraphs 7 or 42 – e.g., a N-well 180).
Allowable Subject Matter
Claims 3-6, 10-13, and 17-20 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art does not teach or suggest a device or fabrication method having the combination of elements/steps of the claims including, among other elements, the bias configuration or routing/layout details of the claims, in combination with the well, pin, and conductivity elements of the claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRYCE M AISAKA whose telephone number is (571)270-5808. The examiner can normally be reached M-F: 6:30AM-5:00PM PT.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached at (571)272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/BRYCE M AISAKA/Primary Examiner, Art Unit 2851
Prosecution Insights