Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Prior Art of Record
The applicant's attention is directed to additional pertinent prior art cited in the accompanying PTO-892 Notice of References Cited, which, however, may not be currently applied as a basis for the following rejections. While these references were considered during the examination of this application and are deemed relevant to the claimed subject matter, they are not presently being applied as a basis for rejection in this Office action. The pertinence of these documents, however, may be revisited, and they may be applied in subsequent Office actions, particularly in light of any amendments or further clarification of the claimed invention.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nishimura et al. (US 20080150157 A1) in view of Asada (US 6239496 B1).
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CLAIM 1. Nishimura teaches a semiconductor package, comprising:
a package substrate 41 having substrate pads 47-1/2;
a first semiconductor chip 42 arranged on an upper surface of the package substrate 41, the first semiconductor chip having a first side surface (46-side) and a second side (43-side) surface each extending in a first direction parallel to the upper surface of the package substrate and facing each other, the first semiconductor chip having first chip pads 46 that are disposed on a first surface thereof and arranged along the first side surface;
a stress relieving adhesive layer 45 disposed on the first semiconductor chip and covering the first semiconductor chip from the first surface of the first semiconductor chip to the second side surface of the first semiconductor chip and exposing the first chip pads 46 (Note: The phrase "stress relieving" is a functional, result-oriented description that fails to provide a clear, explicit structural distinction from other adhesive layers in the claimed location. Furthermore, paragraph [0176] of Nishimura teaches that the third adhesive 133 may be made of the same material as the first 43 or second 45 adhesives, or, alternatively, a different material for purposes of "easing of stress or resistance to moisture." Consequently, "stress relieving" is not a limiting structural feature, as any of the adhesives may possess this property.);
a second semiconductor chip 44 disposed on the stress relieving adhesive layer 45 on the first semiconductor chip by an adhesive film 45/7/101-1/101-2 and having second chip pads, wherein the second semiconductor chip is offset-aligned with the first semiconductor chip in a second direction perpendicular to the first direction to expose the first chip pad (Figs. 5-18, 24); and
a molding member 52 covering the first semiconductor chip and the second semiconductor chip on the package substrate (Figs. 5-18, 24);and
wherein the second chip pads are spaced apart from the substrate pads (Figs. 5-18, 24).
Nisshimura is merely silent upon “wherein the stress relieving adhesive layer is spaced apart from the second chip pads, in a plan view”. While Nishimura shows an adhesive layer, it is largely silent on upon “wherein the stress relieving adhesive layer is spaced apart from the second chip pads, in a plan view”. Instead depicts the adhesive as an integral material that overlaps the second chip pad.
Nishimura discloses coating a first chip with a stress-relieving adhesive on both its sidewall and top surface. Whether this layer is formed as an integral mass or spaced apart is a direct result of standard manufacturing choices. Both integrated and separated formations are well-known options in the art that effectively achieve the same functional results, including device isolation, structural protection, and stress relief.
Asada discloses an analogous semiconductor device structure that addresses any minor variations found in Nishimura. Asada explicitly teaches a material having adhesive/stress relieving properties located on the top and side surfaces of a first chip while remaining distinctly separated from the adjacent chip pad. This separation technique facilitates proper bonding of the second bond pads either during or after the die-stacking process is complete, similar to what is shown in figure 25 of Nishimura. The structure of Nissimura fig. 25, may simply be modified to allow for the adhesive/stress relieving material 45 simply also extend to cover the sidewall of the first chip as shown in fig. 8b of Asada.
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It would have been obvious to a person of ordinary skill in the art at the time of the invention to modify the device structure and manufacturing process of Nishimura. A skilled artisan would readily apply the adhesive material to be separated from the second chip pads as taught by Asada, and then provide further underfill around the second chip pad connection if needed. This action represents a simple substitution of one known technique for another to obtain predictable results.
Following the standards set in KSR International Co. v. Teleflex Inc., modifying a primary reference using a known alternative from a secondary reference to achieve predictable benefits is prima facie obvious. Because the separable and integral adhesive configurations are interchangeable options yielding identical protective and stress-relieving properties, the claimed spacing limitation lacks patentable weight over this combination.
CLAIM 2. Nishimura in view of Asada teach a semiconductor package of claim 1, wherein the stress relieving adhesive layer includes a same material as the adhesive film (Nishimura Fig. 10 & ¶175).
CLAIM 3. Nishimura in view of Asada teach a semiconductor package of claim 2, wherein the stress relieving adhesive layer includes a die attach film (101-1 and 101-2 - Nishimura Fig. 10; Note: The surface protection films 101-1 and 101-2 can be considered die attach films (DAF) structurally because they are applied as a pre-formed layer on the semiconductor wafer during processing to provide structural support, protection, and bonding capability between stacked chips).
CLAIM 4. Nishimura in view of Asada teach a semiconductor package of claim 1, wherein the stress relieving adhesive layer includes a same material as the molding member (Nishimura Fig. 10 & ¶408 – “using the sealing resin 52 as the adhesive” – Sealing resin is a suitable material for adhesive.).
CLAIM 5. Nishimura in view of Asada teach a semiconductor package of claim 1, wherein: the stress relieving adhesive layer 45 includes a first adhesive portion that covers the first surface of the first semiconductor chip and exposes the first chip pads; and a second adhesive portion that covers the second side surface of the first semiconductor chip (Nishimura Fig. 10).
CLAIM 6. Nishimura in view of Asada teach a semiconductor package of claim 5, wherein the second semiconductor chip is offset-aligned with the first semiconductor chip in the second direction on the first adhesive portion to expose a periphery portion of the first adhesive portion of the stress relieving adhesive layer (Nishimura Fig. 10).
CLAIM 7. Nishimura in view of Asada teach a semiconductor package of claim 1, however may be silent upon wherein: the stress relieving adhesive layer has a thickness in a range of about 10 μm to about 30 μm; and the adhesive film has a thickness in a range of about 10 μm to about 40 μm.
Nishimura specifically teaches an adhesive film thickness of 5–20 microns in paragraph 136. While Nishimura may not explicitly label the “stress-relieving adhesive layer” with the recited exact range, the figures and overall device scaling render this thickness at least obvious to the disclosed structure. A PHOSITA would find it obvious to apply the explicitly disclosed 5–20 micron range to the stress-relieving layer to achieve optimal performance, as film thickness is a result-effective variable. Optimizing this range constitutes routine experimentation within the scope of the prior art and produces no unexpected results. Therefore, determining this optimal thickness is not inventive. See MPEP 2144.05.
Given the teaching of the references, it would have been obvious to determine the optimum thickness, temperature as well as condition of delivery of the layers involved. See In re Aller, Lacey and Hall (10 USPQ 233-237) “It is not inventive to discover optimum or workable ranges by routine experimentation.” Note that the specification contains no disclosure of either the critical nature of the claimed ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the Applicant must show that the chosen dimensions are critical. In re Woodruff, 919 f.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Any differences in the claimed invention and the prior art may be expected to result in some differences in properties. The issue is whether the properties differ to such an extent that the difference is really unexpected. In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Applicants have the burden of explaining the data in any declaration they proffer as evidence of non-obviousness. Ex parte Ishizaka, 24 USPQ2d 1621, 1624 (Bd. Pat. App. & Inter. 1992).
An Affidavit or declaration under 37 CFR 1.132 must compare the claimed subject matter with the closest prior art to be effective to rebut a prima facie case of obviousness. In re Burckel, 592 F.2d 1175, 201 USPQ 67 (CCPA 1979).
CLAIM 8. Nishimura in view of Asada teach a semiconductor package of claim 1, wherein: the first semiconductor chip has a third side surface and a fourth side surface that each extend in the second direction, and the first semiconductor chip further has additional first chip pads that are arranged along the third side surface; the stress relieving adhesive layer is disposed on the first semiconductor chip and covers the first surface of the first semiconductor chip to the fourth side surface of the first semiconductor chip, the stress relieving adhesive layer exposing the additional first chip pads; and the second semiconductor chip is offset-aligned with the first semiconductor chip in the first direction to expose the additional first chip pads (Nishimura Fig. 10 & 18).
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CLAIM 9. Nishimura in view of Asada teach a semiconductor package of claim 1, further comprising: at least one spacer chip 181 disposed on the package substrate, wherein the first semiconductor chip is arranged on the at least one spacer chip (Nishimura fig. 25 & ¶291).
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CLAIM 10. Nishimura in view of Asada teach a semiconductor package of claim 1, the further limitation of comprising: at least one third semiconductor chip stacked on the second semiconductor chip by an adhesive film would be a obvious variation of duplication of parts in view of Fig. 27.
While the specific adhesive arrangement with three stacked chips may not be depicted in a single figure, Fig. 27 of Nishimura establishes that such stacking is a known configuration. Modifying the stacked arrangement of Fig. 10 to include a third chip via known adhesive techniques is a mere matter of design optimization, falling within the scope of a POSITA. Such a modification yields predictable, expected results, rendering the limitation obvious under § 103.
CLAIM 11. Nishimura in view of Asada teach a semiconductor package, comprising:
a package substrate 41 having substrate pads;
a first semiconductor chip 42 disposed on the package substrate 41, The first semiconductor chip including first chip pads;
a second semiconductor chip 44 disposed on the first semiconductor chip by an adhesive film 45, and having second chip pad, wherein the second semiconductor chip is offset-aligned with the first semiconductor chip in a horizontal direction (Fig. 10);
a stress relieving adhesive layer 45 disposed on the first semiconductor chip and covering an upper surface of the first semiconductor chip (Note: The phrase "stress relieving" is a functional, result-oriented description that fails to provide a clear, explicit structural distinction from other adhesive layers in the claimed location. Furthermore, paragraph [0176] of Nishimura teaches that the third adhesive 133 may be made of the same material as the first 43 or second 45 adhesives, or, alternatively, a different material for purposes of "easing of stress or resistance to moisture." Consequently, "stress relieving" is not a limiting structural feature, as any of the adhesives may possess this property.),the stress relieving adhesive layer 45 extending vertically downward from the upper surface to cover a side surface of the first semiconductor chip 42 under an overhang region of the second semiconductor chip (Fig. 10); and a molding member 52 covering the first semiconductor chip 41 and the second semiconductor chip 44 on the package substate 41 (Fig. 10).
wherein the second chip pads are spaced apart from the substrate pads in a plan view (Figs. 5-18, 24).
Nisshimura is merely silent upon “wherein the stress relieving adhesive layer is spaced apart from the second chip pads, in a plan view”. While Nishimura shows an adhesive layer, it is largely silent on upon “wherein the stress relieving adhesive layer is spaced apart from the second chip pads, in a plan view”. Instead depicts the adhesive as an integral material that overlaps the second chip pad.
Nishimura discloses coating a first chip with a stress-relieving adhesive on both its sidewall and top surface. Whether this layer is formed as an integral mass or spaced apart is a direct result of standard manufacturing choices. Both integrated and separated formations are well-known options in the art that effectively achieve the same functional results, including device isolation, structural protection, and stress relief.
Asada discloses an analogous semiconductor device structure that addresses any minor variations found in Nishimura. Asada explicitly teaches a material having adhesive/stress relieving properties located on the top and side surfaces of a first chip while remaining distinctly separated from the adjacent chip pad. This separation technique facilitates proper bonding of the second bond pads either during or after the die-stacking process is complete, similar to what is shown in figure 25 of Nishimura. The structure of Nissimura fig. 25, may simply be modified to allow for the adhesive/stress relieving material 45 simply also extend to cover the sidewall of the first chip as shown in fig. 8b of Asada.
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It would have been obvious to a person of ordinary skill in the art at the time of the invention to modify the device structure and manufacturing process of Nishimura. A skilled artisan would readily apply the adhesive material to be separated from the second chip pads as taught by Asada, and then provide further underfill around the second chip pad connection if needed. This action represents a simple substitution of one known technique for another to obtain predictable results.
Following the standards set in KSR International Co. v. Teleflex Inc., modifying a primary reference using a known alternative from a secondary reference to achieve predictable benefits is prima facie obvious. Because the separable and integral adhesive configurations are interchangeable options yielding identical protective and stress-relieving properties, the claimed spacing limitation lacks patentable weight over this combination.
CLAIM 12. Nishimura in view of Asada teach a semiconductor package of claim 11, wherein the stress relieving adhesive layer includes a same material as the adhesive film (Nishimura Fig. 10 & ¶175).
CLAIM 13. Nishimura in view of Asada teach a semiconductor package of claim 12, wherein the stress relieving adhesive layer includes a die attach film (101-1 and 101-2 - Nishimura Fig. 10; Note: The surface protection films 101-1 and 101-2 can be considered die attach films (DAF) structurally because they are applied as a pre-formed layer on the semiconductor wafer during processing to provide structural support, protection, and bonding capability between stacked chips).
CLAIM 14. Nishimura in view of Asada teach a semiconductor package of claim 11, wherein the stress relieving adhesive layer includes a same material as the molding member (Nishimura Fig. 10 & ¶408 – “using the sealing resin 52 as the adhesive” – Sealing resin is a suitable material for adhesive.).
CLAIM 15. Nishimura in view of Asada teach a semiconductor package of claim 11, wherein: the stress relieving adhesive layer includes a first adhesive portion that covers the upper surface of the first semiconductor chip and exposes the first chip pads; and a second adhesive portion that covers the side surface of the first semiconductor chip (Fig. 10).
CLAIM 16. Nishimura in view of Asada teach a semiconductor package of claim 11, wherein the stress relieving adhesive layer is attached on an entirety of an upper surface of the first semiconductor chip and lateral side surfaces of the first semiconductor chip including the side surface except for portions of conductive connection members connected to the first chip pads (Fig. 10).
CLAIM 17. Nishimura teaches a semiconductor package of claim 11, however may be silent upon wherein: the stress relieving adhesive layer has a thickness in a range of about 10 μm to about 30 μm; and the adhesive film has a thickness in a range of about 10 μm to about 40 μm.
Nishimura specifically teaches an adhesive film thickness of 5–20 microns in paragraph 136. While Nishimura may not explicitly label the “stress-relieving adhesive layer” with the recited exact range, the figures and overall device scaling render this thickness at least obvious to the disclosed structure. A PHOSITA would find it obvious to apply the explicitly disclosed 5–20 micron range to the stress-relieving layer to achieve optimal performance, as film thickness is a result-effective variable. Optimizing this range constitutes routine experimentation within the scope of the prior art and produces no unexpected results. Therefore, determining this optimal thickness is not inventive. See MPEP 2144.05.
Given the teaching of the references, it would have been obvious to determine the optimum thickness, temperature as well as condition of delivery of the layers involved. See In re Aller, Lacey and Hall (10 USPQ 233-237) “It is not inventive to discover optimum or workable ranges by routine experimentation.” Note that the specification contains no disclosure of either the critical nature of the claimed ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the Applicant must show that the chosen dimensions are critical. In re Woodruff, 919 f.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Any differences in the claimed invention and the prior art may be expected to result in some differences in properties. The issue is whether the properties differ to such an extent that the difference is really unexpected. In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Applicants have the burden of explaining the data in any declaration they proffer as evidence of non-obviousness. Ex parte Ishizaka, 24 USPQ2d 1621, 1624 (Bd. Pat. App. & Inter. 1992).
An Affidavit or declaration under 37 CFR 1.132 must compare the claimed subject matter with the closest prior art to be effective to rebut a prima facie case of obviousness. In re Burckel, 592 F.2d 1175, 201 USPQ 67 (CCPA 1979).
CLAIM 18. Nishimura in view of Asada teach a semiconductor package of claim 11, further comprising: at least one spacer chip 181 disposed on the package substrate, wherein the first semiconductor chip is arranged on the at least one spacer chip (Nishimura fig. 25 & ¶291).
CLAIM 19. Nishimura in view of Asada teach a semiconductor package of claim 11, the further limitation of comprising: at least one third semiconductor chip stacked on the second semiconductor chip by an adhesive film would be a obvious variation of duplication of parts in view of Fig. 27.
While the specific adhesive arrangement with three stacked chips may not be depicted in a single figure, Fig. 27 of Nishimura establishes that such stacking is a known configuration. Modifying the stacked arrangement of Fig. 10 to include a third chip via known adhesive techniques is a mere matter of design optimization, falling within the scope of a POSITA. Such a modification yields predictable, expected results, rendering the limitation obvious under § 103.
CLAIM 20. Nishimura teaches a semiconductor package (Fig. 10),
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comprising:
a package substrate 41 having substrate pads;
a first semiconductor chip 42 arranged on the package substrate 41, the first semiconductor chip 42 having first chip pads46 that are disposed on a first surface thereof and arranged along a first side surface of the first semiconductor chip 41;
a stress relieving adhesive layer 45 covering the first surface of the first semiconductor chip except for the first chip pads and extending vertically downward to cover a second side surface facing the first side surface of the first semiconductor chip (Fig. 10 – Note:);
a second semiconductor chip 44 disposed on the stress relieving adhesive layer 45 on the first semiconductor chip 42 by an adhesive film 45/101-1/101-2, and having second chip pads, wherein the second semiconductor chip 44 is offset-aligned with the first semiconductor chip in a horizontal direction from the first side surface to the second side surface such that the first chip pads 146 are exposed by the second semiconductor chip 44 (fig. 10); and
a molding member 52 covering the first semiconductor chip 42 and the second semiconductor chip 44 on the package substrate 41 (Fig. 10)
wherein the second chip pads are spaced apart from the substrate pads in a plan view (Figs. 5-18, 24).
Nisshimura is merely silent upon “wherein the stress relieving adhesive layer is spaced apart from the second chip pads, in a plan view”. While Nishimura shows an adhesive layer, it is largely silent on upon “wherein the stress relieving adhesive layer is spaced apart from the second chip pads, in a plan view”. Instead depicts the adhesive as an integral material that overlaps the second chip pad.
Nishimura discloses coating a first chip with a stress-relieving adhesive on both its sidewall and top surface. Whether this layer is formed as an integral mass or spaced apart is a direct result of standard manufacturing choices. Both integrated and separated formations are well-known options in the art that effectively achieve the same functional results, including device isolation, structural protection, and stress relief.
Asada discloses an analogous semiconductor device structure that addresses any minor variations found in Nishimura. Asada explicitly teaches a material having adhesive/stress relieving properties located on the top and side surfaces of a first chip while remaining distinctly separated from the adjacent chip pad. This separation technique facilitates proper bonding of the second bond pads either during or after the die-stacking process is complete, similar to what is shown in figure 25 of Nishimura. The structure of Nissimura fig. 25, may simply be modified to allow for the adhesive/stress relieving material 45 simply also extend to cover the sidewall of the first chip as shown in fig. 8b of Asada.
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It would have been obvious to a person of ordinary skill in the art at the time of the invention to modify the device structure and manufacturing process of Nishimura. A skilled artisan would readily apply the adhesive material to be separated from the second chip pads as taught by Asada, and then provide further underfill around the second chip pad connection if needed. This action represents a simple substitution of one known technique for another to obtain predictable results.
Following the standards set in KSR International Co. v. Teleflex Inc., modifying a primary reference using a known alternative from a secondary reference to achieve predictable benefits is prima facie obvious. Because the separable and integral adhesive configurations are interchangeable options yielding identical protective and stress-relieving properties, the claimed spacing limitation lacks patentable weight over this combination.
Nishimura however may be further silent upon wherein: the stress relieving adhesive layer has a thickness in a range of about 10 μm to about 30 μm; and the adhesive film has a thickness in a range of about 10 μm to about 40 μm.
Nishimura specifically teaches an adhesive film thickness of 5–20 microns in paragraph 136. While Nishimura may not explicitly label the “stress-relieving adhesive layer” with the recited exact range, the figures and overall device scaling render this thickness at least obvious to the disclosed structure. A PHOSITA would find it obvious to apply the explicitly disclosed 5–20 micron range to the stress-relieving layer to achieve optimal performance, as film thickness is a result-effective variable. Optimizing this range constitutes routine experimentation within the scope of the prior art and produces no unexpected results. Therefore, determining this optimal thickness is not inventive. See MPEP 2144.05.
Given the teaching of the references, it would have been obvious to determine the optimum thickness, temperature as well as condition of delivery of the layers involved. See In re Aller, Lacey and Hall (10 USPQ 233-237) “It is not inventive to discover optimum or workable ranges by routine experimentation.” Note that the specification contains no disclosure of either the critical nature of the claimed ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the Applicant must show that the chosen dimensions are critical. In re Woodruff, 919 f.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Any differences in the claimed invention and the prior art may be expected to result in some differences in properties. The issue is whether the properties differ to such an extent that the difference is really unexpected. In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Applicants have the burden of explaining the data in any declaration they proffer as evidence of non-obviousness. Ex parte Ishizaka, 24 USPQ2d 1621, 1624 (Bd. Pat. App. & Inter. 1992).
An Affidavit or declaration under 37 CFR 1.132 must compare the claimed subject matter with the closest prior art to be effective to rebut a prima facie case of obviousness. In re Burckel, 592 F.2d 1175, 201 USPQ 67 (CCPA 1979).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JARRETT J STARK whose telephone number is (571)272-6005. The examiner can normally be reached 8-4 M-F.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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JARRETT J. STARK
Primary Examiner
Art Unit 2822
8/26/2026
/JARRETT J STARK/Primary Examiner, Art Unit 2898
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