DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19 and 20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 8, 8, 10, 11, 12, 13, 14, 15, 16, 17, 18 and 19, respectively, of U.S. Patent No. 11,018,157 B2 (of record). Although the claims at issue are not identical, they are not patentably distinct from each other because the current claims are essentially broader in scope than the corresponding claims of US Patent No. 11,018,157 B2. In other words, all pertinent limitations in the current claims are disclosed; accordingly, the corresponding claims of US Patent No. 11,018,157 B2 anticipates the invention in the current claims (see chart hereinafter).
Current application (18/419,014)
U.S. Patent No. 11,018,157 B2
9. An apparatus, comprising: a first fin field effect transistor (finFET) with a first gate terminal, a first source/drain terminal connected to a first reference metal line through a first via, and a second source/drain terminal; a second finFET with a second gate terminal, a third source/drain terminal connected to a second reference metal line through a second via, and a fourth source/drain terminal; a local interconnect structure routed at a same interconnect level as the first and second reference lines and connected to the first and second gate terminals through one or more third vias; a first interconnect structure routed above the local interconnect structure and connected to the third source/drain terminal through the second via; and a second interconnect structure routed above the local interconnect structure and at a same interconnect level as the first interconnect structure.
10. The apparatus of claim 9, further comprising: a third interconnect structure routed above the first and second interconnect structures and connected to the first interconnect structure through the one or more third vias.
8. An apparatus, comprising: a first fin field effect transistor (finFET) with a first gate terminal, a first source/drain terminal connected to a first reference metal line through a first via, and a second source/drain terminal; a second finFET with a second gate terminal, a third source/drain terminal connected to a second reference metal line through a second via, and a fourth source/drain terminal; a local interconnect structure connected to the first and second gate terminals through one or more third vias and routed at a same interconnect level as the first and second reference lines; a first interconnect structure connected to the second source/drain terminal through the fourth via and the first reference metal line and routed above the local interconnect structure; a second interconnect structure connected to the third source/drain terminal through the second via and the second reference metal line and routed above the local interconnect structure;
and
a third interconnect structure routed above the local interconnect structure and at a same interconnect level as the first and second interconnect structures.
11. The apparatus of claim 9, wherein the local interconnect structure comprises cobalt, copper, or ruthenium.
10. The apparatus of claim 8, wherein the local interconnect structure comprises cobalt, copper, or ruthenium.
12. The apparatus of claim 9, wherein the local interconnect structure has a longer length dimension than the second interconnect structure.
11. The apparatus of claim 8, wherein the local interconnect structure has a longer length dimension than the third interconnect structure.
13. The apparatus of claim 9, wherein the local interconnect structure is routed over the first and second gate terminals and the second interconnect structure is routed over the first gate terminal or the second gate terminal.
12. The apparatus of claim 11, wherein the local interconnect structure is routed over the first and second gate terminals and the third interconnect structure is routed over the first gate terminal or the second gate terminal.
14. A device, comprising: a first transistor with a first gate terminal, a first source/drain terminal connected to a first reference metal line, and a second source/drain terminal; a second transistor with a second gate terminal, a third source/drain terminal connected to a second reference metal line, and a fourth source/drain terminal; a local interconnect structure connected to the first and second gate terminals; a first interconnect structure connected to the third source/drain terminal and the second reference metal line; and a second interconnect structure routed above the local interconnect structure and at a same interconnect level as the first interconnect structure, wherein: the local interconnect structure, the first reference metal line, and the second reference metal line are routed at a first level, and the first interconnect structure and the second interconnect structure are routed at a second level.
13. A device, comprising: a first transistor with a first gate terminal, a first source/drain terminal connected to a first reference metal line through a first via, and a second source/drain terminal; a second transistor with a second gate terminal, a third source/drain terminal connected to a second reference metal line through a second via, and a fourth source/drain terminal; a local interconnect structure connected to the first and second gate terminals through one or more third vias; a first interconnect structure connected to the second source/drain terminal through the fourth via and the first reference metal line; a second interconnect structure connected to the third source/drain terminal through the second via and the second reference metal line; and a third interconnect structure routed above the local interconnect structure and at a same interconnect level as the first and second interconnect structures, wherein the local interconnect structure, the first reference line, and the second reference line are routed at a first level, wherein the first interconnect structure, the second interconnect structure, and the third interconnect structure are routed at a second level.
15. The device of claim 14, wherein the second level is above the first level.
14. The device of claim 13, wherein the second level is above the first level.
16. The device of claim 14, further comprising a third interconnect structure connected to the first interconnect structure and routed at the second level.
15. The device of claim 13, further comprising a fourth interconnect structure connected to the first and second interconnect structures through one or more third vias and routed at the second level.
17. The device of claim 14, wherein the local interconnect structure comprises cobalt, copper, or ruthenium.
16. The device of claim 13, wherein the local interconnect structure comprises cobalt, copper, or ruthenium.
18. The device of claim 14, wherein the local interconnect structure has a longer length dimension than that of the second interconnect structure.
17. The device of claim 13, wherein the local interconnect structure has a longer length dimension than that of the third interconnect structure.
19. The device of claim 14, wherein the local interconnect structure is routed over the first and second gate terminals and the second interconnect structure is routed over the first gate terminal or the second gate terminal.
18. The device of claim 13, wherein the local interconnect structure is routed over the first and second gate terminals and the third interconnect structure is routed over the first gate terminal or the second gate terminal.
20. The device of claim 14, wherein at least one of the first transistor and the second transistor comprises a multi-gate transistor structure.
19. The device of claim 13, wherein at least one of the first transistor and the second transistor comprises a multi-gate transistor structure.
Allowable Subject Matter
Claims 1-8 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Claims 1-8 are allowed primarily because the prior art of record cannot anticipate or render obvious the following limitations, in combination as recited in independent claim 1: a local interconnect structure electrically connected to the gate terminal of the transistor and to another gate terminal of another transistor, wherein the local interconnect structure is routed at a same interconnect level as and is electrically isolated from the reference metal line.
Remarks
Applicant remarks have been carefully reviewed and considered, and the amendment to claims 1-8 overcomes the prior rejections under 35 U.S.C. 112(b), 35 U.S.C. 102(a)(1) and 35 U.S.C. 103.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LEX H MALSAWMA whose telephone number is (571)272-1903. The examiner can normally be reached M-F (4-12 Hours, between 5:30AM-10PM).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at 571-272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/LEX H MALSAWMA/Primary Examiner, Art Unit 2892
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