DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 11/06/2025 has been entered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-8 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "the another gate terminal" in line 5. There is insufficient antecedent basis for this limitation in the claim; and claims 2-8 depend from indefinite claim 1.
For the purpose of examination, “the another gate terminal” is interpreted to be “to another gate terminal”.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 4, 7 and 8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Rashed et al. (US 2013/0146986 A1; hereinafter, “Rashed”, prior art of record).
Regarding claims 1, 4, 7 and 8:
re claim 1(as interpreted), Rashed discloses (in Figs. 1, 5, 6 and 7) an apparatus, comprising:
a transistor 24a (Fig. 6 and [0036]), on a substrate 22 (Fig. 6 and [0036]), comprising a gate terminal 30a [0037], a first source/drain terminal 28a (Fig. 5 and [0034], i.e., although not shown in Figs. 6-7, a first source/drain terminal is required for a functional transistor) coupled to a reference metal line 34/CA (Figs. 1, 5 and [0035] ) separated from the substrate 22, and a second source/drain terminal 26a (Fig. 5 and [0034]);
a local interconnect structure 34/36a/36b (Figs. 6, 7 and [0026]) electrically connected to the gate terminal 30a (Fig. 7 and [0037-0038]) of the transistor 30a and to another gate terminal 30c (Fig. 7 and [0037-0038]) of another transistor 24c (Fig. 7 and [0037-0038]), wherein the local interconnect structure 34/36a/36b (Figs. 6, 7) is routed at a same interconnect level as the reference metal line 34/CA (Figs. 1, 7, i.e., the reference metal 34 shown in Fig. 2 would be associated with transistor 24b in Figs. 6-7 because a source/drain of the transistor 24b must be accessed by upper metallization, and in [0038], Rashed discloses the local interconnect is electrically isolated from the gate 30b of transistor 24b); and
an interconnect structure 33 (Figs. 1, 3 and [0024]) routed above the local interconnect structure 36/CA (Figs. 1 and 3, wherein interconnect metal 33 is located at various locations in order to acquire a complete, function device);
re claim 4, the apparatus of claim 1, wherein the local interconnect structure 34/36a/36b (Figs. 6, 7) is routed over the gate terminal 30a and the other gate terminal 30c, wherein the interconnect structure 33 is routed over the gate terminal 30a or the other gate terminal 30b (Figs. 1, 3 and [0024, 0025, 0030]);
re claim 7, Rashed discloses a plurality of other interconnect structures 33 (Fig. 3 and [0024]) routed above the local interconnect structure 36 (Fig. 1) and coupled to second source/drain terminals (i.e., all wiring in the apparatus are considered to be coupled to power supply voltage and ground in order for the apparatus to be functional; accordingly, because all the source/drain terminals are coupled to power, ground and the interconnect structures 33, this claim is disclosed by Rashed); and
re claim 8, the apparatus of claim 1, wherein the local interconnect structure 36 (Fig. 1) is longer than the interconnect structure 33 (in the vertical direction, as viewed in Fig. 1).
Therefore, Rashed anticipates claims 1, 4, 7 and 8.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 2, 3, 5 and 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rashed.
Regarding claim 2:
Rashed anticipates claims 1 and discloses (in [0004]) the trench silicide layer 37 (Figs. 1, 3 and [0028]) electrically connects one of the source/drain of a first transistor to one of the source/drain of a second transistor. Rashed also discloses/shows another reference metal line 48/CA (Fig. 5 and [0035]) connected to a source/drain terminal of a transistor separated from the other transistor 24b (Fig. 5 and [0034], Note in Fig. 5, the other transistor “24b” is mislabeled as “24a”). Furthermore, Rashed discloses a plurality of other interconnect structures 33 (Fig. 3 and [0024, 0025 and 0030]) connected to various source/drain regions 28 (Fig. 1 and [0004]).
In sum, Rashid discloses the apparatus of claim 1, wherein the other transistor 24b (Fig. 5 with notation above) comprises a third source/drain terminal 26b (Fig. 5 and [0045]) Fig. 5 and [0045]), and wherein the apparatus further comprises another interconnect structure 33 (i.e., one of structures “33” in Fig. 3 and [0024]) Fig. 1 and [0029]).
Rashed does not explicitly show a third source/drain terminal 26b (Fig. 5 and [0045]) coupled to an other reference metal line and an other interconnect structure 33 coupled to the fourth source/drain terminal 28b. However, in an embodiment (shown in Fig. 2), Rashed discloses the trench silicide layers 37 (of transistors 24a, 24b that are separated by a gap 32) are coupled to each other (i.e., the source/drain of one transistor is coupled to the source/drain of another transistor); and in Figs. 1, 3 and [0004], an other interconnect structure 33 is connected to a source/drain of the first transistor and to a source/drain of the second transistor.
Therefore, although Rashed does not explicitly show third source/drain 26b (Fig. 5) couple to an other reference metal line 48/CA (Fig. 5) and an other interconnect structure 33 (Figs. 1 and 3) coupled to the fourth source/drain 26b, it would have been obvious to one of ordinary skill in the art to couple the elements as currently claimed because Rashed discloses such connections would be made (although not explicitly shown) in order to acquire a logic device such as scan-D flip-flops and multiplexers [0002, 0027].
Regarding claims 3, 5 and 6:
re claim 3, Rashed renders obvious the apparatus of claim 2, and further discloses wherein the local interconnect structure 36 (Figs. 1, 3 and [0025]) is coupled to the gate terminal 30a (Fig. 5 and [0034]) and the other gate terminal 30b (Fig. 5 and [0034]) comprises copper; and
re claims 5 and 6, all wiring in the apparatus of claim 2 are considered to be coupled to power supply voltage and ground in order for the apparatus to be functional; therefore, the other reference metal line and the reference metal line are coupled to both supply voltage and ground.
Therefore, claims 3, 5 and 6 are rendered obvious by Rashed.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19 and 20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 8, 8, 10, 11, 12, 13, 14, 15, 16, 17, 18 and 19, respectively, of U.S. Patent No. 11,018,157 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because the current claims are essentially broader in scope than the corresponding claims of US Patent No. 11,018,157 B2. In other words, all pertinent limitations in the current claims are disclosed; accordingly, the corresponding claims of US Patent No. 11,018,157 B2 anticipates the invention in the current claims.
Remarks
Applicant remarks have been carefully reviewed and considered. The amendment to claims 1-8 overcome the prior rejection based on an embodiment in Rashed; however, the claims are currently rejected based on a different embodiment disclosed by Rashed. Applicant’s remarks with respect to the nonstatutory double patenting rejection have been noted.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LEX H MALSAWMA whose telephone number is (571)272-1903. The examiner can normally be reached M-F (4-12 Hours, between 5:30AM-10PM).
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/LEX H MALSAWMA/Primary Examiner, Art Unit 2892