Prosecution Insights
Last updated: July 17, 2026
Application No. 18/419,033

TWINNED MICROMACHINED ULTRASONIC TRANSDUCER

Non-Final OA §102§103
Filed
Jan 22, 2024
Priority
Jan 25, 2023 — DE 102023200596.4
Examiner
PALANISWAMY, KRISHNA JAYANTHI
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Infineon Technologies AG
OA Round
1 (Non-Final)
74%
Grant Probability
Favorable
1-2
OA Rounds
7m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 74% — above average
74%
Career Allowance Rate
14 granted / 19 resolved
+5.7% vs TC avg
Strong +33% interview lift
Without
With
+33.3%
Interview Lift
resolved cases with interview
Typical timeline
3y 1m
Avg Prosecution
20 currently pending
Career history
47
Total Applications
across all art units

Statute-Specific Performance

§103
90.9%
+50.9% vs TC avg
§102
3.0%
-37.0% vs TC avg
§112
6.1%
-33.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 19 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement The information disclosure statement (IDS) submitted on 01/22/2024, is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Election/Restrictions Applicant’s election without traverse of Group I, and Claims 1-18 in the reply filed on 04/23/2026 is acknowledged. Claims 20 and 22 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 04/23/2026. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1, 12, 18 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Tsai et al. (US20210078857A1; hereinafter Tsai). PNG media_image1.png 889 513 media_image1.png Greyscale Tsai: FIG. 2H Regarding Claim 1, Tsai discloses an ultrasonic transducer (hybrid micromachined ultrasonic transducer (MUT) device 10, FIG. 1A, [0014]), comprising: a set of transducer elements (array of MUT units, FIG. 1A, [0015]) including: a capacitive transducer element (cMUT unit 102C, FIG. 1A, [0012, 0015]); and a piezoelectric transducer element (pMUT unit 102P, FIG. 1A, [0012, 0015]); wherein the capacitive transducer element (cMUT unit 102C) and the piezoelectric transducer element (pMUT unit 102P) are provided laterally separated in a same semiconductor die (the MUT device 20 includes the cMUT units 102C and 104C alternately disposed with the pMUT units 102P and 104P, [0054]), FIG. 2H reproduced above, [0021]. Regarding Claim 12, Tsai discloses the ultrasonic transducer of claim 1, wherein the piezoelectric transducer element (pMUT 102P) comprises a piezoelectric layer (piezoelectric layer 102PM, [0029]) made from at least one of AlN, AlScN, or PZT, (aluminum nitride and lead zirconate-titanate (PZT), [0028]). Regarding Claim 18, Tsai discloses the ultrasonic transducer of claim 1, wherein the semiconductor die (MUT device 10 comprising MEMS substrate 201 bonded to device substrate 231) comprises an array of sets of transducer elements (the MUT device 10 includes an array of MUT units) including the set of transducer elements (pMUT units 102P and 104P and cMUT units 102C and 104C), FIG. 1A, [0015]. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 2, 11, 13, 14, and 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over Tsai in view of Adachi et al. (US20100201222A1; hereinafter Adachi). Regarding Claim 2, Tsai discloses the ultrasonic transducer of claim 1. Tsai discloses: wherein the capacitive transducer element (102C) comprises a bottom capacitive transducer element electrode (102CB) and a top capacitive transducer element electrode (102CT), FIG. 1A, [0015]. wherein the piezoelectric transducer element (102P) comprises a bottom piezoelectric transducer element electrode (102PB) and a top piezoelectric transducer element electrode (102PT), FIG. 1A, [0015]. Tsai does not disclose “wherein the top capacitive transducer element electrode is provided in a same layer as the bottom piezoelectric transducer element electrode.” In a similar art, Adachi discloses micromachined ultrasound transducer [0004]. Adachi discloses: wherein the top capacitive transducer element electrode is provided in a same layer as the bottom piezoelectric transducer element electrode (the cMUT 32 and the pMUT 33 have a common ground electrode 35), FIG. 3, [0103]. Adachi FIG. 3, [0104] discloses the cMUT 32 includes a bottom electrode 34 and the common ground electrode 35. The common electrode 35 faces the bottom electrode 34 across the cavity and functions as the top capacitive transducer element electrode. Adachi FIG. 3, [0105] discloses the pMUT 33 includes the upper electrode 36, the piezoelectric film 46, and the common ground electrode 35. Since the piezo electric film 46 is disposed between the upper electrode 36 and the common electrode 35, the common electrode 35 functions as the bottom piezoelectric transducer element electrode. Adachi [0103] discloses the cMUT32 and pMUT33 have a common ground electrode 35. Adachi [0104], [0105], [0106] discloses the common ground electrode 35 of the cMUT32 and pMUT33 correspond to the common ground electrode 8 shown in Fig. 1. The common ground electrode 8 functions as the top electrode of cMUT32 and also the bottom electrode of pMUT33. Thus, the top electrode of the cMUT32 and the bottom electrode of the pMUT33 are provided in the same layer (common ground electrode layer 8) shown in FIG. 1. Adachi discloses that an ultrasonic transducer as taught increases the reception sensitivity [0120]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Tsai’s device in order to increase the reception sensitivity as disclosed by Adachi [0120]. Regarding Claim 11, The combination of Tsai and Adachi discloses the ultrasonic transducer of claim 2. Tsai discloses: wherein the top piezoelectric transducer element electrode (102PT) is made from a metal (metallic materials, e.g., gold, silver, copper, tungsten, aluminum, titanium, tantalum, and the like, [0018]). Regarding Claim 13, Tsai discloses the ultrasonic transducer of claim 1. Tsai does not explicitly disclose “wherein at least one of the capacitive transducer element and the piezoelectric transducer element comprises a frequency tuning layer.” Adachi discloses: wherein at least one of the capacitive transducer element and the piezoelectric transducer element (pMUT33) comprises a frequency tuning layer (insulating film 82), FIG. 7, [0153], [0162], [0163]. Adachi [0153] discloses the insulation film 82 is formed on the bottom electrode 7, and the cavity 6 is enclosed by membrane 5, supporting membrane 4, and the insulating film 82. Adachi [0163] discloses the high order vibrations which can cause frequency changing phenomenon are damped and only the charges generated by the fundamental vibrations remain as feedback signals. Insulating film 82 forms a part of the cavity structure and functions as the frequency tuning layer. Adachi discloses that an ultrasonic transducer as taught improves vibration stability and efficiency [0163]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Tsai’s device in order to improve vibration stability and efficiency as disclosed by Adachi [0163]. Regarding Claim 14, The combination of Tsai and Adachi discloses the ultrasonic transducer of claim 13. Tsai does not disclose “wherein the frequency tuning layer is made from at least one of SiO2, SiN, or SiOxN.” Adachi discloses: wherein the frequency tuning layer (insulation film 82) is made from at least one of SiO2, SiN, or SiOxN [0160]. Adachi [0160] discloses the insulating film 82 is formed of materials such as SrTiO3, barium titanate BaTiO3, .. or the like. Adachi [0090] also discloses an insulating film 11 comprising SiO2 formed on the substrate 3. It would be obvious to use SiO2, SiN, or SiOxN as a choice of insulating material for the insulating film 82. Adachi discloses that an ultrasonic transducer as taught improves vibration stability and efficiency [0163]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify the device in order to improve vibration stability and efficiency as disclosed by Adachi [0163]. Regarding Claim 15, The combination of Tsai and Adachi discloses the ultrasonic transducer of claim 2. Tsai discloses: wherein the semiconductor die (MUT device 10) comprises an active semiconductor component (semiconductor devices 234 may be active devices, such as field effect transistors (FET), that include metal-oxide-semiconductor (MOS) FET and junction FET devices), [0039]. Regarding Claim 16, The combination of Tsai and Adachi discloses the ultrasonic transducer of claim 15. Tsai discloses: wherein an interlayer connector (RDL 242 including conductive liens 246 and vias 248) electrically connects the active semiconductor component (234) to at least one of: the bottom capacitive transducer element electrode (102CB), [0040], [0042]. the top capacitive transducer element electrode, the bottom piezoelectric transducer element electrode, the top piezoelectric transducer element electrode. Regarding Claim 17, The combination of Tsai and Adachi discloses the ultrasonic transducer of claim 16. Adachi discloses: wherein the semiconductor die (substrate 3 of the MUT element 31) comprises an ASIC, wherein the ASIC comprises the active semiconductor component (FETs 38 and 43), [0121]. Adachi discloses that an ultrasonic transducer as taught can be compact [0121]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify the device in order to provide a compact device as disclosed by Adachi [0121]. Claims 3 – 5 are rejected under 35 U.S.C. 103 as being unpatentable over Tsai in view of Wakabayashi et al. (US20090058228A1; hereinafter Wakabayashi). Regarding Claim 3, Tsai discloses the ultrasonic transducer of claim 1. Tsai [0048] discloses the cavities 102CV, 104CV, 102PV, and 104PV are formed between bonded substrate structures 201 and 231, where the bonding may be performed in a vacuum or highly vacuum environment such that the cavities are substantially vacuum cavities. Tsai does not explicitly disclose “wherein at least one of the capacitive transducer element or the piezoelectric transducer element comprises a hermetically sealed cavity.” In a similar art, Wakabayashi discloses a capacitive ultrasonic transducer [0003]. Wakabayashi discloses: wherein at least one of the capacitive transducer element (capacitive transducer cell 33 [0062]) or the piezoelectric transducer element comprises a hermetically sealed cavity (the cavity 107 is a hermetically-sealed air gap layer), FIG. 5, [0073]. Wakabayashi discloses that an ultrasonic transducer as taught including a hermetically sealed cavity enables a stable pressure condition in the cavity [0073]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Tsai’s device in order maintain a stable pressure condition in the cavity as disclosed by Wakabayashi [0073]. Regarding Claim 4, The combination of Tsai and Wakabayashi discloses the ultrasonic transducer of claim 3. Tsai does not disclose “wherein a pressure in the hermetically sealed cavity is approximately 1013 mbar.” Wakabayashi discloses: wherein a pressure in the hermetically sealed cavity (107) is approximately 1013 mbar (atmospheric pressure, [0073]). Wakabayashi [0073] discloses the cavity 107 as a hermetically-sealed air gap layer in an atmospheric pressure. Since the atmospheric value is 1013 mbar, the hermetically sealed cavity pressure is approximately 1013 mbar. Wakabayashi discloses that an ultrasonic transducer as taught including a hermetically sealed cavity enables a stable pressure condition in the cavity [0073]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify the device in order maintain a stable pressure condition in the cavity as disclosed by Wakabayashi [0073]. Regarding Claim 5, The combination of Tsai and Wakabayashi discloses the ultrasonic transducer of claim 3. Tsai discloses the cavities 102PV, 104PV, 102CV and 104CV have a barometric pressure between about 1E-5 and about 1E-4 mtorr, [0048]. Pressure range of 1E-5 to 1E-4 mtorr is equal to 1.33X10-8 to 1.33X10-7 mbar, which is below 10 mbar. Wakabayashi discloses the cavity 107 is hermetically-sealed air gap layer in an atmospheric pressure, a pressurized, or a depressurized state, [0073]. The combination of Tsai and Wakabayashi discloses: wherein a pressure in the hermetically sealed cavity (Wakabayashi: cavity 107, [0073]) is below 10 mbar (Tsai: pressure of about 1E-5 and about 1E-4 mtorr, [0048]). Wakabayashi discloses that an ultrasonic transducer as taught including a hermetically sealed cavity enables a stable pressure condition in the cavity [0073]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify the device in order maintain a stable pressure in the cavity as disclosed by Wakabayashi [0073]. Claims 6, 9, and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Tsai in view of Adachi, further in view of Dehe et al. (US20150001647A1; hereinafter Dehe647). Regarding Claim 6, The combination of Tsai and Adachi discloses the ultrasonic transducer of claim 2. The combination of Tsai and Adachi does not explicitly disclose “wherein the bottom capacitive transducer element electrode is made from a doped semiconductor material.” In a similar art, Dehe647 discloses a MEMS sound transducer [0009]. Dehe647 discloses: wherein the bottom capacitive transducer element electrode (224) is made from a doped semiconductor material (layer 2024 for forming electrode 224 may be doped polysilicon), FIG. 20D, [0068]. Dehe647 discloses that an ultrasonic transducer as taught can improve signal-to-noise ratio and improve the performance of the device [0002]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Tsai and Adachi’s device in order to improve signal-to-noise ratio and improve the performance of the device as disclosed by Dehe647 [0002]. Regarding Claim 9, The combination of Tsai and Adachi discloses the ultrasonic transducer of claim 2. The combination of Tsai and Adachi does not explicitly disclose “wherein the top capacitive transducer element electrode and the bottom piezoelectric transducer element electrode are made from a doped semiconductor material or a metal.” Dehe647 [0068] discloses layers 2022 and 2024 which form the electrodes 222 and 224 of the transducer may be of doped polysilicon or comprise doped polysilicon. The combination of Tsai and Dehe647 discloses: wherein the top capacitive transducer element electrode (Tsai: 102CT) and the bottom piezoelectric transducer element electrode (Tsai: 102PB) are made from a doped semiconductor material or a metal (Dehe647: doped polysilicon, [0068]). Dehe647 discloses that an ultrasonic transducer as taught can improve signal-to-noise ratio and improve the performance of the device [0002]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Tsai and Adachi’s device in order to improve signal-to-noise ratio and improve the performance of the device as disclosed by Dehe647 [0002]. Regarding Claim 10, The combination of Tsai, Adachi, and Dehe647 discloses the ultrasonic transducer of claim 9. The combination of Tsai and Adachi does not disclose “wherein the top capacitive transducer element electrode and the bottom piezoelectric transducer element electrode are made from doped polysilicon.” Dehe647 [0068] discloses layers 2022 and 2024 which form the electrodes 222 and 224 of the transducer may be of doped polysilicon or comprise doped polysilicon. The combination of Tsai, Adachi, and Dehe647 discloses: wherein the top capacitive transducer element electrode (Tsai: 102CT) and the bottom piezoelectric transducer element electrode (Tsai: 102PB) are made from doped polysilicon (Dehe647: doped polysilicon, [0068]). Dehe647 discloses that an ultrasonic transducer as taught can improve signal-to-noise ratio and improve the performance of the device [0002]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify the device in order to improve signal-to-noise ratio and improve the performance of the device as disclosed by Dehe647 [0002]. Claims 7 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Tsai in view of Adachi, further in view of Dehe647, still further in view of Dehe (US20150245118A1; hereinafter Dehe118). Regarding Claim 7, The combination of Tsai, Adachi, and Dehe647 discloses the ultrasonic transducer of claim 6. The combination of Tsai, Adachi, and Dehe647 does not disclose “wherein the bottom capacitive transducer element electrode is made from an implanted semiconductor layer.” In a similar art, Dehe118 discloses a transducer [0028]. Dehe118 discloses: wherein the bottom capacitive transducer element electrode (12) is made from an implanted semiconductor layer (highly implanted polysilicon layer 124), FIG. 5, [0045]. Dehe118 [0045] discloses the polysilicon layer 124 also serves as an electrode of a capacitor formed by the first stator 12 and the membrane 14 and is made of highly implanted polysilicon 124, thus the bottom capacitive transducer element electrode (12) is made of implanted semiconductor layer. Dehe118 discloses that a transducer as taught including electrode made of implanted semiconductor layer improves electrical conductivity of the device [0045]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Tsai, Adachi, Dehe647’s device in order to improve electrical conductivity as disclosed by Dehe118 [0045]. Regarding Claim 8, The combination of Tsai, Adachi, and Dehe647 discloses the ultrasonic transducer of claim 6. The combination of Tsai, Adachi, and Dehe647 does not disclose “wherein a dopant of the doped semiconductor material comprises at least one of Ar or P.” Dehe118 discloses: wherein a dopant of the doped semiconductor material (124) comprises at least one of Ar or P, (phosphor doping, [0047]), FIG. 5, [0045]. Dehe118 [0045] discloses the polysilicon layer 124 also serves as an electrode of a capacitor formed by the first stator 12 and the membrane 14, and [0047] discloses the phosphor doping of the silicon layer 124, thus the dopant of the doped semiconductor material comprises Phosphorus P. Dehe118 discloses that a transducer as taught including phosphorus dopant improves electrical conductivity of the semiconductor layer [0047]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Tsai, Adachi, Dehe647’s device in order to improve electrical conductivity as disclosed by Dehe118 [0047]. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Krishna J Palaniswamy whose telephone number is (571)272-6239. The examiner can normally be reached Monday - Friday 8:30AM - 5PM EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brent Fairbanks can be reached at 408-918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Krishna J. Palaniswamy/Examiner, Art Unit 2899 /Brent A. Fairbanks/Supervisory Patent Examiner, Art Unit 2899
Read full office action

Prosecution Timeline

Jan 22, 2024
Application Filed
Jan 22, 2024
Response after Non-Final Action
Jun 04, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 3 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
74%
Grant Probability
99%
With Interview (+33.3%)
3y 1m (~7m remaining)
Median Time to Grant
Low
PTA Risk
Based on 19 resolved cases by this examiner. Grant probability derived from career allowance rate.

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