Prosecution Insights
Last updated: October 02, 2026
Application No. 18/419,190

SIDEWALL STRUCTURES FOR MEMORY CELLS IN VERTICAL STRUCTURES

Non-Final OA §103
Filed
Jan 22, 2024
Priority
May 27, 2021 — divisional of 11/903,333
Examiner
NIX, NORA TAYLOR
Art Unit
2891
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Micron Technology Inc.
OA Round
1 (Non-Final)
90%
Grant Probability
Favorable
1-2
OA Rounds
4m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 90% — above average
90%
Career Allowance Rate
79 granted / 88 resolved
+21.8% vs TC avg
Moderate +9% lift
Without
With
+9.4%
Interview Lift
resolved cases with interview
Typical timeline
3y 1m
Avg Prosecution
21 currently pending
Career history
105
Total Applications
across all art units

Statute-Specific Performance

§103
60.7%
+20.7% vs TC avg
§102
26.9%
-13.1% vs TC avg
§112
12.1%
-27.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 88 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Claims 3-6 and 13-17 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected species, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 07/10/2026. Response to Arguments Applicant's arguments filed 07/10/2026 have been fully considered but they are not persuasive. Applicant argues the examiner has drawn the species lines too finely and unreasonably since FIG. 14 depicts the overarching method recited in independent claim 2; FIG. 9, associated with Species D, depicts a storage element formed by the method illustrated in FIG. 14; and FIGS. 10-13, associated with Species E-H, each depict alternative implementations of sub-steps for performing various steps of the FIG. 14 method. Applicant argues since FIGS. 10-13 are four alternative implementations of sub-steps within the method depicted in FIG. 14, Species D-H share a common method, a common field of search, and substantially overlapping art. However, FIGS. 9-13, associated with Species D-H, each depict distinct structures formed via the method illustrated in FIG. 14. Although FIG. 14 shows a method which is shared among all species, alternative implementations of sub-steps for forming the structures of FIGS. 9-13 exist (see Applicant arguments filed 07/10/2026). These distinct structures and alternative sub-steps necessarily require different fields of search and prior art. Thus, the restriction among species stands. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claims 2, 7, and 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Kobayashi (US 20210083184 A1; hereinafter Kobayashi) in view of Happ et al. (US 20070097739 A1; hereinafter Happ). Regarding claim 2, FIGS. 1-12 of Kobayashi teach a method, comprising: forming a substrate (11 ¶ [0055]) defining a plane (xy-plane) in a first direction (x direction) and a second direction (y direction), and extending in a third direction (z direction) orthogonal to the plane (xy-plane); forming a stack of layers (21, 65, 88, 47) on the substrate (11 ¶ [0090]), the stack of layers (21, 65, 88, 47) comprising one or more conductive materials (21, 47 ¶ [0090]) and one or more dielectric materials (65, 88 ¶ [0090]); etching the stack of layers (21, 65, 88, 47) to form a plurality of cavities (e.g. S ¶ [0096], see FIGS. 7-9); depositing a chalcogenide material (55/51) into a cavity of the plurality of cavities (S ¶ [0067]) to form a self-selecting storage element (61, 51, 43, 81, i.e. MC, see FIG. 2) that is in contact with a first conductive material (WL) and at least two dielectric materials (instances of 38) and that comprises a bulk region (52-53, 58) comprising the chalcogenide material having a first composition (¶ [0067],[0070]) and a sidewall region (59 ¶ [0070]); and depositing a second conductive material (22/BL, see FIGS. 7-9) that contacts the sidewall region of the chalcogenide material (59), a portion of the sidewall region (59) extending between the first conductive material (WL) and the second conductive material (BL) in the first direction parallel to the plane defined by the substrate (x direction). The examiner notes the term “contacts” has been interpreted under broadest reasonable interpretation (BRI, MPEP § 2111.01) as meaning “directly contacts”, “indirectly contacts”, “electrically contacts”, or “physically contacts”. Kobayashi does not explicitly teach the sidewall region comprising the chalcogenide material having a second composition that is different than the first composition. FIG. 10 of Happ teaches a phase-change memory device comprising a chalcogenide material (134) including a bulk region (128) comprising the chalcogenide material having a first composition (“second phase-change material composition”) and a sidewall region (124) comprising the chalcogenide material having a second composition that is different than the first composition (“first phase-change material composition” ¶ [0026]). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method taught by Kobayashi with the sidewall region taught by Happ for the purpose of achieving the desired size for the active region (¶ [0028],[0046],[0055], e.g. a thickness of the chalcogenide material), reducing a reset current of the phase-change memory cell, and improvement of multi-bit data storage control (¶ [0064]). Regarding claim 7, Kobayashi as modified teaches the method of claim 2, wherein: the second conductive material (22/BL) is deposited prior to the chalcogenide material (55/51), the first conductive material (WL) forming a first side of the cavity (side of S closest to WL) and the second conductive material (22/BL) forming a second side of the cavity (side of S closest to BL, see FIGS. 9-10), and the self-selecting storage element (MC) is in contact with the second conductive material (BL) based at least in part on depositing the chalcogenide material into the cavity (S). Regarding claim 10, Kobayashi as modified teaches the method of claim 2, and Kobayashi further teaches wherein a performance of the bulk region (52-53, 58) is based at least in part on a thickness of the sidewall region (59 ¶ [0072],[0084],[0102]). Regarding claim 11, Kobayashi as modified teaches the method of claim 2, and FIGS. 7-9 of Kobayashi further teach wherein etching the stack of layers to form the plurality of cavities (etching processes shown in FIGS. 7-9) comprises: etching one or more layers of the stack of layers (21, 65, 88, 47) that comprise the one or more conductive materials (21, 22) to form the plurality of cavities (S) in the one or more layers comprising the one or more conductive materials (21, 65, 88, 47 ¶ [0094]-[0096]). Allowable Subject Matter Claims 18-21 are allowed. The following is an examiner’s statement of reasons for allowance: Claim 18 recites a method, comprising: forming a substrate defining a plane in a first direction and a second direction; forming a stack of layers on the substrate; forming a first electrode and a second electrode in a layer of the stack of layers, wherein a cavity is located between the first electrode and the second electrode; forming, after forming the first electrode and the second electrode, a chalcogenide material within the cavity, wherein the chalcogenide material contacts the first electrode, the second electrode, and at least one dielectric material; and depositing, after forming the chalcogenide material within the cavity, a second dielectric material within the cavity, wherein: the chalcogenide material comprises a bulk region having a first composition and a sidewall region having a second composition that is different than the first composition based at least in part on forming the chalcogenide material within the cavity, depositing the second dielectric material within the cavity, or both, and a portion of the sidewall region extends between the first electrode and the second electrode in the first direction parallel to the plane defined by the substrate and is positioned between the bulk region and the second dielectric material. FIGS. 1-12 of Kobayashi teach a method, comprising: forming a substrate (11 ¶ [0055]) defining a plane (xy-plane) in a first direction (x direction) and a second direction (y direction); forming a stack of layers (21, 65, 88, 47, 22) on the substrate (11 ¶ [0090]); forming a first electrode (21) and a second electrode (22) in a layer of the stack of layers (21, 65, 88, 47, 22), wherein a cavity (S) is located between the first electrode (21/WL) and the second electrode (22/BL ¶ [0096], see FIG. 9); forming, after forming the first electrode (21/WL) and the second electrode (22/BL), a chalcogenide material (55/51) within the cavity (S ¶ [0067]), wherein the chalcogenide material (55/51) contacts the first electrode (21/WL), the second electrode (22/BL), and at least one dielectric material (39, see FIG. 10); and depositing, after forming the chalcogenide material (55/51) within the cavity (S), a second dielectric material (38) within the cavity (S ¶ [0100], see FIGS. 11-12), wherein: the chalcogenide material (55/51) comprises a bulk region (52-53, 58) having a first composition (¶ [0067],[0070]) and a sidewall region (59 ¶ [0070]), a portion of the sidewall region (59) extends between the first electrode (WL) and the second electrode (BL) in the first direction parallel to the plane defined by the substrate (e.g. x direction, see FIG. 2). FIG. 10 of Happ teaches a phase-change memory device comprising a chalcogenide material (134) including a bulk region (128) comprising the chalcogenide material having a first composition (“second phase-change material composition”) and a sidewall region (124) comprising the chalcogenide material having a second composition that is different than the first composition (“first phase-change material composition” ¶ [0026]). However, the prior art fails to teach or reasonably suggest “a portion of the sidewall region is positioned between the bulk region and the second dielectric material” together with all the limitations of claim 18 as claimed. Claims 19-21 are allowable insofar as they depend upon and require all the limitations of claim 18. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Claims 8-9 and 12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Claim 8 recites the method of claim 7, further comprising: processing first portions of the chalcogenide material after depositing the chalcogenide material into the cavity, wherein the portion of the sidewall region extends from the first conductive material to the second conductive material based at least in part on processing the first portions of the chalcogenide material. Kobayashi in view of Happ teaches the method of claim 7, and Kobayashi further teaches further comprising: processing first portions of the chalcogenide material (55 including 52-53, 58, e.g. removing portions of 55 other than 52-23, 58) after depositing the chalcogenide material into the cavity (S, see FIGS. 9-12). However, the prior art fails to teach or reasonably suggest “wherein the portion of the sidewall region extends from the first conductive material to the second conductive material based at least in part on processing the first portions of the chalcogenide material” together with all the limitations of claims 2 and 7-8 as claimed. Claim 9 recites the method of claim 2, wherein a conductive path extends between the first conductive material and the second conductive material in a direction that is parallel to the plane. Kobayashi in view of Happ teaches the method of claim 2. However, the prior art fails to teach or reasonably suggest “wherein a conductive path extends between the first conductive material and the second conductive material in a direction that is parallel to the plane” together with all the limitations of claims 2 and 9 as claimed. Claim 12 recites the method of claim 11, further comprising: depositing the first conductive material into the plurality of cavities formed in the one or more layers comprising the one or more conductive materials. Kobayashi in view of Happ teaches the method of claim 11. However, the prior art fails to teach or reasonably suggest “depositing the first conductive material into the plurality of cavities formed in the one or more layers comprising the one or more conductive materials” together with all the limitations of claims 2 and 11-12 as claimed. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Nora T Nix whose telephone number is (571)270-1972. The examiner can normally be reached Monday - Friday 9:00 am - 5:00 pm ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571) 272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Nora T. Nix/Assistant Examiner, Art Unit 2891 /MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891
Read full office action

Prosecution Timeline

Jan 22, 2024
Application Filed
Sep 14, 2026
Non-Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
90%
Grant Probability
99%
With Interview (+9.4%)
3y 1m (~4m remaining)
Median Time to Grant
Low
PTA Risk
Based on 88 resolved cases by this examiner. Grant probability derived from career allowance rate.

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