DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-6 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over SHI et al. (US PGpub: 2023/0018253 A1 or US 2020/0227395 A1), herein after SHI, in view of SHI.
Regarding claim 1, SHI teaches a light-emitting diode structure, including:
a substrate (1110, FIG. 1, 2, 3A, The LED chip (110L1-110L3) is a flip-chip LED, and includes a light-transmissible substrate 1110 (which may be omitted according to practical requirements), a first-type semiconductor layer 1111 that is connected to the light-transmissible substrate 1110 in Paragraph [0050]) ,
a semiconductor light-emitting structure (a light-emitting structure includes layer 1112, 1111) located on the substrate, and the semiconductor light-emitting structure including a light-emitting surface (1323) and a plurality of side walls (S24 has two side surfaces as in FIG. 8. LED chips (110L1-110L3) as well has multiple sidewalls), and the light-emitting surface having a surface roughening area (180 as seen in FIG.3. coarse layer 180 that is disposed on the first surface (S21) of each of the LED chips (110L1-110L3) for inducing light scattering to reduce glare of the display panel);
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and
an electrode (1121 and 1122) located on the light-emitting surface (S24, FIG. 8 and 13) ,
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wherein the surface roughening area is located between the electrode and the plurality of side walls (since 180 is located on S24, 180 should be located between 1120 and side surface S24), and
SHI does not explicitly teach the light-emitting surface has a first flat part (1323 has extended part) formed between the surface roughening area (180) and the plurality of side walls.
However, SHI discloses light-emitting surface has a first flat part (1323 has extended part) formed between the surface roughening area (180) and the plurality of side walls (LED chips surface 110L2 and 110L3 in below FIG. 16).
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Hence, it would have been obvious to one of ordinary skill in the art before the effective fling date of the claimed invention to use SHI’s display device to modify with teaching from SHI such that the device improves the stability of the TFT and increase the lighting efficiency of the LED device
Regarding claim 3, SHI teaches the light-emitting diode structure of claim 1, wherein the surface roughening area is not higher than the first flat part (this claim is little unclear. Higher in what? In simple terms, the surface roughening area 180 can be interpreted to be not higher is not higher than the first flat part
Regarding claim 4, SHI teaches the light-emitting diode structure of claim 1, wherein the light-emitting surface (1112 and 1111) has a second flat part (multiple flat parts) formed between the surface roughening area and the electrode (1122).
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Regarding claim 5, SHI teaches the light-emitting diode structure of claim 4, wherein the surface roughening area is not higher than the second flat part (this claim is little unclear. Higher in what? In simple terms, the surface roughening area 180 can be interpreted to be not higher is not higher than the second flat part as well).
Regarding claim 6, SHI teaches the light-emitting diode structure of claim 4, wherein the electrode (1121 and 1122) includes a pad part and at least one extension part, one end of each of the extension part connects to the pad part, and the second flat part is located at a peripheral of the pad part and that of each of the extension part (In FIG. 8 , 1121 has a flat part and flat part and second side part which all are connected and connected to peripheral part) .
Regarding claim 10, SHI teaches the light-emitting diode structure of claim 1, wherein each of the plurality of side walls is perpendicular to a flat surface of the light-emitting surface (Top surface is perpendicular to side walls).
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Claims 2, 7-9 and 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over SHI et al. (US PGpub: 2023/0018253 A1 or US 2020/0227395 A1), herein after SHI, in view of SHI and in further view of TAKEUCHI et al. (FP: TW201044632A as in IDS)
Regarding claim 2, SHI teaches the light-emitting diode (in view of TAKEUCHI) structure of claim 1, wherein a width of the first flat part is not less than 1 micrometer (the film thickness of the p-type cladding layer 7c is preferably maintained in the range of 200 to 2000 nm, and the film thickness of the n-type cladding layer 7a is preferably maintained in the range of 200 to 2000 nm. Further, the thickness of the entire light-emitting layer 7 is preferably in the range of 500 to 1,500 nm. By maintaining the thickness of each of the light-emitting layer 7 and each of the layers constituting the light-emitting layer 7 in the above range, the light-emitting layer 7 having excellent crystallinity and excellent luminous efficiency can be obtained. The n-type semiconductor layer 8 is provided on the light-emitting layer 7 and has an n-type characteristic of doping Si, Te or Sn quantitatively, for example, composed of (Al0.5Ga0.5)0.5In0.5P doped with Si. N-type contact layer. As a raw material for doping Si, for example, dioxane (Si 2 H 6 ) or the like can be used. The thickness of the n-type semiconductor layer 8 is preferably maintained in the range of 100 to 8000 nm, more preferably in the range of 500 to 3000 nm. When the thickness of the n-type semiconductor layer 8 is within this range, it becomes a film having good crystallinity, and the light-emitting efficiency of the light-emitting layer 7 is improved, and the light-emitting characteristics of the light-emitting diode A are improved). The height or width can be manipulated to fit the need, any flat part can be considered changeable to fit he device functionality.
Regarding claim 7, SHI teaches the light-emitting diode (in view of TAKEUCHI)structure of claim 4, further including a transparent conductive layer,( Next, as shown in FIG. 3B, the bonding layer 4 is further formed on each of the compound semiconductor layers 11. Specifically, first, a light-transmitting thin film layer 4a made of ITO or the like is formed to cover the p-type ohmic electrode 5 formed on the p-type semiconductor layer 6 of the compound semiconductor layer 11. Then, a bonding layer 4b made of Ag or the like, a barrier layer 4c made of Mo or the like, an Au layer 4d, and a metal bonding layer 4e made of an AuSn material or the like are sequentially laminated thereon to form a bonding layer 4. . As a method of forming the respective layers constituting the bonding layer 4, the previously known method can be employed without any limitation.) wherein the transparent conductive layer covers the at least one part of the electrode, the second flat part and the surface roughening area (ITO will cover the surface roughening area in you insert ITO) such that light-emitting diode which is capable of preventing damage such as cracks in the compound semiconductor layer, improves yield, and has excellent heat dissipation properties of the substrate. Thereby, a light-emitting diode which is applied with high current and excellent in luminous efficiency can be manufactured with high manufacturing efficiency.
Regarding claim 8, SHI teaches the light-emitting diode (in view of TAKEUCHI) structure of claim 1, further including a transparent conductive layer (light-transmitting thin film layer 4a made of ITO), wherein the transparent conductive layer at least covers the surface roughening area (ITO will cover the surface roughening area in you insert ITO) such that light-emitting diode which is capable of preventing damage such as cracks in the compound semiconductor layer, improves yield, and has excellent heat dissipation properties of the substrate. Thereby, a light-emitting diode which is applied with high current and excellent in luminous efficiency can be manufactured with high manufacturing efficiency.
Regarding claim 9, SHI teaches (in view of TAKEUCHI) the light-emitting diode structure of claim 7, wherein the transparent conductive layer includes indium tin oxide, indium zinc oxide or indium gallium zinc oxide (light-transmitting thin film layer 4a made of ITO) such that light-emitting diode which is capable of preventing damage such as cracks in the compound semiconductor layer, improves yield, and has excellent heat dissipation properties of the substrate. Thereby, a light-emitting diode which is applied with high current and excellent in luminous efficiency can be manufactured with high manufacturing efficiency.
Regarding claim 11, SHI teaches (in view of TAKEUCHI) the light-emitting diode structure of claim 1, wherein the substrate is selected from a group consisted of silicon substrate, aluminum nitride substrate, sapphire substrate, copper tungsten substrate and molybdenum substrate (The method for producing a light-emitting diode according to the above [18] or [19] wherein the substrate forming process is formed of molybdenum or tungsten or an alloy material thereof. [21] The method for producing a light-emitting diode according to any one of the above aspects, wherein the substrate forming process is formed by a material containing at least one or more elements selected from the group consisting of gold, silver, copper or aluminum. Unit in TAKEUCHI) such that light-emitting diode which is capable of preventing damage such as cracks in the compound semiconductor layer, improves yield, and has excellent heat dissipation properties of the substrate. Thereby, a light-emitting diode which is applied with high current and excellent in luminous efficiency can be manufactured with high manufacturing efficiency.
Regarding claim 12, SHI teaches (in view of TAKEUCHI) the light-emitting diode structure of claim 1, further including a buffer layer formed between the substrate and the semiconductor light-emitting structure, and the buffer layer (4b) is made of a material selected from a group consisted of silicon dioxide, aluminum oxide, gold, indium, tin, platinum, zinc, titanium, indium tin oxide, indium zinc oxide, indium oxide Made of gallium zinc and zinc oxide (The reflective layer 4b is a reflective film made of a metal material having high reflection characteristics from light emitted from the compound semiconductor layer 11 by, for example, Ag, Au, Pt, Al, or Cu, and is reflected toward the compound semiconductor layer 11 side from the compound semiconductor. The layer 11 is emitted and transmitted through the light-transmitting film layer 4a toward the heat-dissipating substrate 1 side. Further, the material of the reflective layer 4b depends on the light-emitting wavelength of the compound semiconductor layer 11 (light-emitting layer 7), and the above materials may be used alone or the above materials may be used as an alloy material.) such that light-emitting diode which is capable of preventing damage such as cracks in the compound semiconductor layer, improves yield, and has excellent heat dissipation properties of the substrate. Thereby, a light-emitting diode which is applied with high current and excellent in luminous efficiency can be manufactured with high manufacturing efficiency.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See form PTO-892.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHEIKH MARUF whose telephone number is (571)270-1903. The examiner can normally be reached M-F, 8am-6pm EDT.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached at 571-270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHEIKH MARUF/Primary Examiner, Art Unit 2897
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