Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 5/8/2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s).
Claims 1-2, 4, 6, 8-9, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Lin (US 20180138116 A1, hereinafter Lin ‘116) in view of Watanabe (US 20090321912 A1) and Lin (US 10790164 B1).
Regarding claim 1, Lin ‘116 discloses a method for manufacturing a semiconductor package (Fig. 2A), comprising:
disposing sub-semiconductor packages (113; [0017]: “a stack of multiple dies”) and main semiconductor chips (111; [0017]: “a logic die such as a system-on-chip (SoC) die”) on a package substrate (150M) to form a semiconductor structure (one of the multiple structures 200 shown),
wherein each of the sub-semiconductor packages and the main semiconductor chips is disposed on the package substrate in a vertical direction (See annotated figure for direction designation), and each of the sub-semiconductor packages comprises a base chip and an inner mold layer on the base chip, and is spaced apart from each of the main semiconductor chips in a horizontal direction (See annotated figure for direction designation);
disposing the semiconductor structure in a first mold;
disposing, in a second mold, a mold film comprising a first mold film and a second mold film;
coupling the first mold and the second mold to each other to form a cavity between the first mold and the second mold, and disposing the sub-semiconductor packages and the main semiconductor chips in the cavity; and
heat treating the mold film to form a mold layer (133/135) to cover the semiconductor structure and to fill the cavity,
the mold layer comprising a first mold layer (133) contacting the package substrate (directly contacting) and a second mold layer (135) entirely spaced apart from the package substrate (no portion of layer 135 reaches substrate 150M),
the first mold layer covering a first surface (See annotated figure) of the semiconductor structure (directly covering) and a first portion of a side surface (See annotated figure) of the semiconductor structure,
the second mold layer covering (horizontally covering at the edges) a second surface of the semiconductor structure (See annotated figure) and a second portion of the side surface of the semiconductor structure (See annotated figure),
the first surface facing the package substrate (directly facing), and the second surface being disposed opposite to the first surface in the vertical direction,
wherein an upper surface of the first mold layer is in contact with an under surface of the second mold layer, and
wherein the inner mold layer is in contact with both the first mold layer and the second mold layer.
Illustrated below is a marked and annotated figure of Fig. 2A of Lin ‘116.
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Lin ‘116 teaches the mold layer but fails to teach the method of forming it. Thus, Lin ‘116 fails to teach “disposing the semiconductor structure in a first mold;
disposing, in a second mold, a mold film comprising a first mold film and a second mold film;
coupling the first mold and the second mold to each other to form a cavity between the first mold and the second mold, and disposing the sub-semiconductor packages and the main semiconductor chips in the cavity; and
heat treating the mold film to form a mold layer to cover the semiconductor structure and to fill the cavity, […]
wherein an upper surface of the first mold layer is in contact with an under surface of the second mold layer”.
Watanabe discloses a method (the package structural embodiment of Fig. 10: more specifically, selecting a stacked plurality of chips disclosed in [0103]: “multiple semiconductor chips”; and selecting the connection species disclosed in [0107]: “flip chip”), comprising:
disposing the semiconductor structure (the resultant package of Fig. 10) in a first mold (selecting the method of Figs. 8A-8C: the first mold is 26);
disposing, in a second mold (27), a mold film (the collection of the initial 11 and 12) comprising a first mold film (the initial 11) and a second mold film (the initial 12);
coupling the first mold and the second mold to each other to form a cavity (the cavity is encircled in annotated Fig. 8B) between the first mold and the second mold (the method step of Fig. 8C), and disposing the sub-semiconductor packages and the main semiconductor chips in the cavity (proceeding from the method step of Fig. 8B to Fig. 8C shows “disposing” in the cavity); and
heat treating the mold film ([0041]: “thermosetting resin” requiring a heat treatment) to form a mold layer (Fig. 10: the resultant 10) to cover the semiconductor structure (completely fill) and to fill the cavity (completely fill),
the mold layer comprising a first mold layer (the resultant 11) contacting the package substrate (directly physically contacting substrate 13) and a second mold layer (the resultant 12) entirely spaced apart from the package substrate (entirely spaced apart by intervening 11),
the first mold layer covering a first surface of the semiconductor structure (at least indirectly covering) and a first portion of a side surface of the semiconductor structure ([0107]: “In the case of the uppermost semiconductor chip being used for flip chip connection, the first resin is filled up to a bottom surface 7b' of the uppermost semiconductor chip”. Therefore the 11/12 interface is shifted to be coplanar with 7b'. Thus, layer 11 is directly covering the side surface: See dashed reference line in annotated Fig. 10 for first portion designation, in view of this species modification),
the second mold layer covering a second surface of the semiconductor structure (7a', directly covering) and a second portion of the side surface of the semiconductor structure (7a', similar to the reasoning for layer 11, layer 12 is directly covering the side surface: See dashed reference line in annotated Fig. 10 for second portion designation),
the first surface facing the package substrate (directly facing towards), and the second surface being disposed opposite to the first surface in the vertical direction (7a' is opposite the first surface in the vertical direction),
wherein an upper surface of the first mold layer is in contact (direct contact is shown in Fig. 10) with an under surface of the second mold layer
Modifying the method of Lin ‘116 by forming the mold layer in the way disclosed by Watanabe would arrive at the claimed mold layer method. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because in each situation a mold layer is formed on an intermediately formed package to arrive at an encapsulated package (Lin ‘116: Fig. 2A; Watanabe: Fig. 10). Watanabe provides a teaching to motivate one of ordinary skill in the art before the effective filing date to incorporate the mold layer formation method in that it would improve thermal expansion characteristics of the package, thereby reducing warpage ([0050]: “a balance of thermal expansion coefficients is improved, and warpage of the semiconductor device 1 can be prevented”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed mold layer formation method because it would reduce package warping. MPEP 2143 (I)(G).
Illustrated below are marked and annotated figures of Figs. 8A-8C and Fig. 10 of Watanabe.
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Lin ‘116 in view of Watanabe teaches the sub-semiconductor packages of the method but only teaches these packages with a generic configuration (Lin ‘116: Fig. 2A: 113; [0017]: “a stack of multiple dies”). Thus, Lin ‘116 in view of Watanabe fails to teach “each of the sub-semiconductor packages comprises a base chip and an inner mold layer on the base chip, and is spaced apart from each of the main semiconductor chips in a horizontal direction; […]
wherein the inner mold layer is in contact with both the first mold layer and the second mold layer”.
Lin discloses a method with sub-semiconductor packages, wherein:
each of the sub-semiconductor packages (Fig. 8B: 130) comprises a base chip (131) and an inner mold layer (140) on the base chip (directly on), and is spaced apart from each of the main semiconductor chips (120) in a horizontal direction; […]
wherein the inner mold layer is in contact with (at least indirect contact) both the first mold layer and the second mold layer (mold layers 150/160 are relied upon here to establish analogousness of the packages, and to show general spatial arrangements of these packages, but these mold layers are not being incorporated here in the combination of references).
Modifying the sub-semiconductor packages of the method disclosed by Lin ‘116 in view of Watanabe, by incorporating the specific configuration of Lin, would arrive at the claimed sub-semiconductor package configuration and mold layer configurations: because the mold layers of Lin ‘116 in view of Watanabe would be in contact at least indirectly with each other. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because in each situation the methods include sub-semiconductor packages comprising stacked chips performing similar functions (Lin ‘116: [0017]: “memory dies…a stack of multiple dies”; Lin: col. 9, ln. 61-col. 10, ln. 3: “stacked die package…memory dies”). A person of ordinary skill in the art before the effective filing date could have combined the teachings of Lin ‘116 with the method and sub-semiconductor package configuration of Lin in the way claimed, because each sub-semiconductor package (of Lin ‘116 or Lin) includes stacks of chips performing the same function. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed method and sub-semiconductor package configuration because it is a combination of package configurations according to known methods, with a reasonable expectation of success. MPEP 2143 (I)(A).
Regarding claim 2, Lin ‘116 in view of Watanabe and Lin discloses the method of claim 1 (Watanabe: Fig. 8B), wherein the second mold film is directly disposed on the second mold (there are no intervening films between 12 and 27), the first mold film is directly disposed on the second mold film (there are no intervening films between 11 and 12), one surface of the first mold film contacts the second mold film (directly physically contacts), and the one surface of the first mold film and another surface of the first mold film opposite to the one surface are spaced apart from the second mold (spaced apart from the portion directly physically interfacing with 12).
Regarding claim 4, Lin ‘116 in view of Watanabe and Lin discloses the method of claim 1 (Watanabe: Fig. 8C), wherein: the forming the semiconductor structure comprises forming first spaces between respective sub-semiconductor packages and the package substrate (the first spaces are a resultant dimension produced by the flip chip electrical connectors of the selected embodiment), and forming second spaces between respective main semiconductor chips and the package substrate (the second spaces are a resultant dimension produced by the flip chip electrical connectors of the selected embodiment); and the forming the mold layer comprises filling the first spaces and the second spaces with the first mold layer ([0107]: “the first resin is filled up to a bottom surface 7b' of the uppermost semiconductor chip” would result in 11 surrounding the flip chip electrical connectors of the selected embodiment).
Regarding claim 6, Lin ‘116 in view of Watanabe and Lin discloses the method of claim 1 (Watanabe: Fig. 8C), wherein a thickness of the first mold film (a plurality of thicknesses must exist when including at least: a vertical thickness of the film adjacent the sub-semiconductor packages/main semiconductor chips; as well as the portion of the film sandwiched between the sub-semiconductor packages/main semiconductor chips and the package substrate, which is a resultant dimension produced by the flip chip electrical connectors of the selected embodiment), differs from a thickness of the second mold film (since a plurality of thicknesses exist, at least one must differ from a thickness of the second mold film).
Regarding claim 8, Lin ‘116 in view of Watanabe and Lin discloses the method of claim 1 (Watanabe: Fig. 8B), wherein: the first mold film comprises a first base film ([0043]: “a first resin”) and a first filler ([0042]: “filler”); and the second mold film comprises a second base film ([0043]: “a second resin”) and a second filler ([0042]: “filler”).
Regarding claim 9, Lin ‘116 in view of Watanabe and Lin discloses the method of claim 8 (Watanabe: Fig. 8B), however fails to teach specific dimensional characteristics of the first and second fillers, and therefore fails to teach “wherein an average size of the first filler is smaller than an average size of the second filler”.
Lin discloses first and second mold layers (Fig. 8F: 150 and 16 respectively) respectively including first and second fillers (152 and 162 respectively), wherein the first and second filler configurations are deliberately chosen to be different
wherein an average size of the first filler is smaller than an average size of the second filler (col. 10, lines 51-61: “the average diameter of each of the fillers 152 of the underfill layer 150 is shorter than the average first length L.sub.1 of each of the first fillers 162 of the package layer 160”).
Watanabe and Lin separately disclose each element claimed. One of ordinary skill in the art before the effective filing date could have combined the method of Lin ‘116 in view of Watanabe and Lin with the filler configuration of Lin as claimed and in combination each filler configuration merely performs the same function as it does separately (i.e. to have different resultant coefficients of thermal expansion for the first and second mold layers). One of ordinary skill in the art before the effective filing date would have had predictable results because both Watanabe and Lin teach methods with deliberately varied filler configurations to produce first and second mold layers having differing coefficients of thermal expansion (Watanabe: [0041] “two types of resins having different thermal expansion coefficients”; in combination with [0042]: “different thermal expansion coefficients can be obtained by, for example, the content of a filler being changed”; Lin: col. 10, lines 51-61: “the coefficient of thermal expansion (CTE) of each of the fillers 162 of the package layer 160 is greater than the CTE of each of the fillers 152 of the underfill layer 150”).. Therefore, the claim would have been obvious to one of ordinary skill in the art before the effective filing date because it appears to be a mere combination of prior art element configurations according to known functional configurations yielding a predictable mold layer. One of ordinary skill in the art before the effective filing date would have been motivated to do so to produce a mold layer having a plurality of coefficients of thermal expansion. MPEP 2143 (I)(A).
Illustrated below is a marked and annotated figure of Fig. 8F of Lin.
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Regarding claim 13, Lin ‘116 in view of Watanabe and Lin discloses the method of claim 1 (Watanabe: Fig. 8C), wherein an under surface of the first mold layer (See annotated figure) contacts an upper surface of the package substrate (See annotated figure, directly physically contacts), an upper surface of the first mold layer contacts an under surface of the second mold layer (See annotated figure, directly physically contacts), the under surface of the second mold layer is parallel to the upper surface of the package substrate (illustrated as parallel), and the upper surface of the first mold layer and the under surface of the second mold layer are flat (illustrated as flat).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Lin ‘116, Watanabe, and Lin as applied to claim 1 above, and further in view of Yanagawa (US 20140124936 A1).
Regarding claim 3, Lin ‘116 in view of Watanabe and Lin discloses the method of claim 1 (Watanabe: Fig. 8C), wherein the forming the mold layer comprises pressing the semiconductor structure against the mold film (the collection of 13 and 7 are directly pressing into 11 and 12), however is silent with respect to specific force ranges used for pressing. Accordingly, Watanabe fails to teach the specific pressing configuration “wherein the forming the mold layer comprises pressing the semiconductor structure against the mold film at about 1 to 20 MPa”.
Yanagawa discloses a method in the same field of endeavor wherein a first and second mold are pressed together ([0049]: “male and female molds”) using a known pressing configuration ([0049]: “thereby completing molding”); the pressing configuration includes:
pressing the semiconductor structure ([0049]: “semiconductor module”) against the mold film at about 1 to 20 MPa ([0049]: “clamping pressure…14.7 MPa”).
Lin ‘116 in view of Watanabe, Lin, and Yanagawa separately disclose each element claimed. One of ordinary skill in the art before the effective filing date could have combined the method of Lin ‘116 in view of Watanabe and Lin with the pressing configuration of Yanagawa as claimed, and in combination each pressing configuration merely performs the same function as it does separately (i.e. to produce the resultant effect of a mold film). One of ordinary skill in the art before the effective filing date would have had predictable results because both Watanabe and Yanagawa teach methods with first and second molds used with pressing a semiconductor structure against a mold film (Watanabe Fig. 8C illustrates the first and second mold are pressed together with at least a force sufficient to produce the resultant effect of the mold film completely conforming to the semiconductor structure. Yanagawa teaches the first and second mold are pressed together in [0049]: “male and female molds” with at least a force sufficient to produce the resultant effect of a mold film described in [0049]: “thereby completing molding”).
Therefore, the claim would have been obvious to one of ordinary skill in the art before the effective filing date because it appears to be a mere combination of prior art element configurations according to known functional configurations yielding a predictable mold film. One would have been motivated to do so to produce a semiconductor structure enclosed by a mold film. MPEP 2143 (I)(A).
Claims 5 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Lin ‘116 , Watanabe, and Lin as applied to claim 1 above, and further in view of Meyer (US 20090108440 A1).
Regarding claim 5, Lin ‘116 in view of Watanabe and Lin discloses the method of claim 1 (Watanabe: Fig. 8C), however fails to teach specific dimensional ranges for a thickness of the mold film, and therefore fails to teach “a thickness of the mold film is about 250 to 350 µm”.
Meyer discloses a method in the same field of endeavor with a mold film (Fig. 1: the collection of 102 with 103) including a first mold film (102) and a second mold film (103), and further teaches a thicknesses of the mold film includes at least a thickness of the first mold film ([0026]: “thickness of the first material…chosen in a range”),
wherein the thickness of the mold film is about 250 to 350 µm ([0026]: selecting 100% from “between 20 to 200% of the thickness of the semiconductor chips” and selecting 300 µm from “have a thickness of 100 µm to 300 µm or more”; these selected thickness are squarely within the claimed range);
Selecting the known mold film thickness configuration of Meyer for the mold film of Lin ‘116 in view of Watanabe and Lin would arrive at the claimed mold film thickness configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success to formulate the claimed thickness configuration because it is routine optimization within a prior art condition. Any differences in the claimed invention and the prior art may be expected to result in some differences in properties. The issue is whether the properties differ to such an extent that the difference is really unexpected. In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). Applicants have the burden of explaining the data in any declaration they proffer as evidence of non-obviousness. Ex parte Ishizaka, 24 USPQ2d 1621, 1624 (Bd. Pat. App. & Inter. 1992). An Affidavit or declaration under 37 CFR 1.132 must compare the claimed subject matter with the closest prior art to be effective to rebut a prima facie case of obviousness. In re Burckel, 592 F.2d 1175, 201 USPQ 67 (CCPA 1979). MPEP 716.02.
Therefore, it would have been obvious to one of ordinary skill in the art of manufacturing a semiconductor package before the effective filing date to determine the workable or optimal value for the thickness of the mold film through routine experimentation and optimization to obtain optimal or desired device performance because the claimed thickness is a result-effective variable and there is no evidence indicating that it is critical or produces any unexpected results and it has been held that it is not inventive to discover the optimum or workable ranges of a result-effective variable within given prior art conditions by routine experimentation. Moreover, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669,149 USPQ 47 (CCPA 1966). MPEP 2144.04 (IV)(A).
Illustrated below is Fig. 1 of Meyer.
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Regarding claim 7, Lin ‘116 in view of Watanabe and Lin discloses the method of claim 1 (Watanabe: Fig. 8C), however fails to teach specific dimensional ranges for thicknesses of the first and second mold films, and therefore fails to teach “wherein a thickness of the first mold film is smaller than a thickness of the second mold film”.
Meyer discloses a method in the same field of endeavor with a mold film (Fig. 1: the collection of 102 with 103) including a first mold film (102) and a second mold film (103), and further teaches a thicknesses of the first mold film ([0026]: “thickness of the first material…chosen in a range”),
wherein a thickness of the first mold film ([0026]: selecting 20% for 102 from “between 20 to 200% of the thickness of the semiconductor chips”) is smaller than a thickness of the second mold film (103 is covering the remainder of the chip, i.e., 80%. Thus, 20% is smaller than 80%);
Selecting the known first and second mold film thickness configuration of Meyer for the first and second mold film of Lin ‘116 in view of Watanabe and Lin would arrive at the claimed thickness configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success to formulate the claimed thickness configuration because it is routine optimization within a prior art condition. Any differences in the claimed invention and the prior art may be expected to result in some differences in properties. The issue is whether the properties differ to such an extent that the difference is really unexpected. In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). Applicants have the burden of explaining the data in any declaration they proffer as evidence of non-obviousness. Ex parte Ishizaka, 24 USPQ2d 1621, 1624 (Bd. Pat. App. & Inter. 1992). An Affidavit or declaration under 37 CFR 1.132 must compare the claimed subject matter with the closest prior art to be effective to rebut a prima facie case of obviousness. In re Burckel, 592 F.2d 1175, 201 USPQ 67 (CCPA 1979). MPEP 716.02.
Therefore, it would have been obvious to one of ordinary skill in the art of manufacturing a semiconductor package before the effective filing date to determine the workable or optimal value for the thicknesses of the first and second mold films through routine experimentation and optimization to obtain optimal or desired device performance because the claimed thicknesses are a result-effective variable and there is no evidence indicating that they are critical or produces any unexpected results and it has been held that it is not inventive to discover the optimum or workable ranges of a result-effective variable within given prior art conditions by routine experimentation. Moreover, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669,149 USPQ 47 (CCPA 1966). MPEP 2144.04 (IV)(A).
Claims 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Lin ‘116 in view of Watanabe and Lin as applied to claims 8 and 1 above, and further in view of Takasugi (JP H10199936 A).
Regarding claim 10, Lin ‘116 in view of Watanabe and Lin discloses the method of claim 8 (Watanabe: Fig. 8B), however fails to teach specific ranges for particular physical properties of the first and second base films, i.e., “wherein a viscosity of the first base film differs from a viscosity of the second base film”.
Takasugi discloses a method with first and second base films in the same field of endeavor (Fig. 1: films 6 and 7 respectively), wherein the first base film surrounds electrical connectors (5) and the second base film completely encapsulated the remainder of a package (remainder of 4). Takasugi further teaches:
a viscosity of the first base film differs from a viscosity of the second base film (pg. 8 to pg. 9 of translation: “low viscosity and fluidity is preferable” and “high viscosity” respectively).
Modifying the viscosities of the first and second base films of Lin ‘116 in view of Watanabe and Lin, by incorporating the viscosity teachings of Takasugi would arrive at the claimed viscosity configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success because in each situation, the first base film has utility surrounding electrical connectors (Watanabe: [0107]: “the first resin is filled up to a bottom surface 7b' of the uppermost semiconductor chip” would result in film 11 surrounding the flip chip electrical connectors of the selected embodiment; Takasugi: Fig. 1: layer 6 on connectors 5) and discloses the second base film has utility encapsulating the remainder of the package (Watanabe: [0104]: “the second resin 12 is formed over the first resin 11 and the uppermost semiconductor chip”; Takasugi: Fig. 7: layer 7 on package 4). Takasugi provides a teaching to motivate one of ordinary skill in the art before the effective filing date to modify the viscosity configuration of Lin ‘116 in view of Watanabe and Lin in that it would prevent air bubbles among the electrical connectors while still enabling a strong package (pg. 8 last paragraph to pg. 9 first paragraph of translation: “to prevent air bubbles”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed viscosity configuration because it would prevent air bubbles while maintaining package strength. MPEP 2143 (I)(G).
Regarding claim 11, Lin ‘116 in view of Watanabe and Lin discloses the method of claim 8 with first and second base films (Watanabe: Fig. 8B), however fails to teach specific ranges for particular physical properties of the first and second base films, i.e., “wherein a viscosity of the first base film is lower than a viscosity of the second base film”.
Takasugi discloses a method with first and second base films in the same field of endeavor (Fig. 1: 6 and 7 respectively), wherein the first base film surrounds electrical connectors (5) and the second base film completely encapsulated the remainder of a package (remainder of 4). Takasugi further teaches:
a viscosity of the first base film is lower than a viscosity of the second base film (pg. 8 to pg. 9 of translation: “low viscosity and fluidity is preferable” and “high viscosity” respectively).
Modifying the viscosities of the first and second base films of Lin ‘116 in view of Watanabe and Lin, by incorporating the viscosity teachings of Takasugi would arrive at the claimed viscosity configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success because in each situation, the first base film has utility surrounding electrical connectors (Watanabe: [0107]: “the first resin is filled up to a bottom surface 7b' of the uppermost semiconductor chip” would result in film 11 surrounding the flip chip electrical connectors of the selected embodiment; Takasugi: Fig. 1: layer 6 on connectors 5) and discloses the second base film has utility encapsulating the remainder of the package (Watanabe: [0104]: “the second resin 12 is formed over the first resin 11 and the uppermost semiconductor chip”; Takasugi: Fig. 7: layer 7 on package 4). Takasugi provides a teaching to motivate one of ordinary skill in the art before the effective filing date to modify the viscosity configuration of Lin ‘116 in view of Watanabe and Lin in that it would prevent air bubbles among the electrical connectors while still enabling a strong package (pg. 8 last paragraph to pg. 9 first paragraph of translation: “to prevent air bubbles”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed viscosity configuration because it would prevent air bubbles while maintaining package strength. MPEP 2143 (I)(G).
Claims 12, 15, and 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Lin ‘116 in view of Watanabe, Lin, and Yanagawa.
Regarding independent claim 12, Lin ‘116 discloses a method for manufacturing a semiconductor package (Fig. 2A), comprising:
disposing sub-semiconductor packages (113; [0017]: “a stack of multiple dies”) and main semiconductor chips (111; [0017]: “a logic die such as a system-on-chip (SoC) die”) on a package substrate (150M) to form a semiconductor structure (one of the multiple structures 200 shown), and forming a space (See annotated figure) between the package substrate and each of the sub-semiconductor packages and the main semiconductor chips,
wherein each of the sub-semiconductor packages and the main semiconductor chips is disposed on the package substrate in a vertical direction (See annotated figure for direction designation), and each of the sub-semiconductor packages comprises a base chip and an inner mold layer on the base chip, and is spaced apart from each of the main semiconductor chips in a horizontal direction (See annotated figure for direction designation);
disposing the semiconductor structure in a first mold;
disposing, in a second mold, a mold film comprising a first mold film and a second mold film;
coupling the first mold and the second mold to each other to form a cavity between the first mold and the second mold, and disposing the semiconductor structure in the cavity; and
pressing the semiconductor structure against the mold film at about 1 to 20 MPa, and heating the mold film to 100 to 200°C to form a mold layer (133/135) to cover the semiconductor structure and to fill the cavity,
the mold layer comprising a first mold layer (133) contacting the package substrate (directly contacting) while filling the space (completely filling) and a second mold layer (135) entirely spaced apart from the package substrate (no portion of layer 135 reaches substrate 150M),
the first mold layer covering a first surface (See annotated figure) of the semiconductor structure (directly covering) and a first portion of a side surface (See annotated figure) of the semiconductor structure,
the second mold layer covering (horizontally covering at the edges) a second surface of the semiconductor structure (See annotated figure) and a second portion of the side surface of the semiconductor structure (See annotated figure),
the first surface facing the package substrate (directly facing), and the second surface being disposed opposite to the first surface in the vertical direction,
wherein an upper surface of the first mold layer is in contact with an under surface of the second mold layer, and
wherein the inner mold layer is in contact with both the first mold layer and the second mold layer.
Lin ‘116 teaches the mold layer but fails to teach the method of forming it. Thus, Lin ‘116 fails to teach “disposing the semiconductor structure in a first mold;
disposing, in a second mold, a mold film comprising a first mold film and a second mold film;
coupling the first mold and the second mold to each other to form a cavity between the first mold and the second mold, and disposing the semiconductor structure in the cavity;
pressing the semiconductor structure against the mold film at about 1 to 20 MPa, and heating the mold film to 100 to 200°C to form a mold layer to cover the semiconductor structure and to fill the cavity, […]
wherein an upper surface of the first mold layer is in contact with an under surface of the second mold layer”.
Watanabe discloses a method (the package structural embodiment of Fig. 10: more specifically, selecting a stacked plurality of chips disclosed in [0103]: “multiple semiconductor chips”; and selecting the connection species disclosed in [0107]: “flip chip”), comprising:
disposing the semiconductor structure (the resultant package of Fig. 10) in a first mold (selecting the method of Figs. 8A-8C: the first mold is 26);
disposing, in a second mold (27), a mold film (the collection of the initial 11 and 12) comprising a first mold film (the initial 11) and a second mold film (the initial 12);
coupling the first mold and the second mold to each other to form a cavity (the cavity is encircled in annotated Fig. 8B) between the first mold and the second mold (the method step of Fig. 8C), and disposing the semiconductor structure in the cavity (proceeding from the method step of Fig. 8B to Fig. 8C shows “disposing” in the cavity); and
pressing the semiconductor structure against the mold film (the collection of 13 and 7 are directly pressing into 11 and 12) at about 1 to 20 MPa, and heating the mold film to 100 to 200°C ([0071]: “the second resin 12 is cured at a given temperature, such as approximately 180° C”; [0096]: “the first resin 11 is cured at a given temperature, for example, 180°C”) to form a mold layer (Fig. 10: the resultant 10) to cover the semiconductor structure (completely fill) and to fill the cavity (completely fill),
the mold layer comprising a first mold layer (the resultant 11) contacting the package substrate (directly physically contacting substrate 13) while filling the space (completely filling) and a second mold layer (the resultant 12) entirely spaced apart from the package substrate (entirely spaced apart by intervening 11),
the first mold layer covering a first surface of the semiconductor structure (at least indirectly covering) and a first portion of a side surface of the semiconductor structure ([0107]: “In the case of the uppermost semiconductor chip being used for flip chip connection, the first resin is filled up to a bottom surface 7b' of the uppermost semiconductor chip”. Therefore the 11/12 interface is shifted to be coplanar with 7b'. Thus, layer 11 is directly covering the side surface: See dashed reference line in annotated Fig. 10 for first portion designation, in view of this species modification),
the second mold layer covering a second surface of the semiconductor structure (7a', directly covering) and a second portion of the side surface of the semiconductor structure (7a', similar to the reasoning for layer 11, layer 12 is directly covering the side surface: See dashed reference line in annotated Fig. 10 for second portion designation),
the first surface facing the package substrate (directly facing towards), and the second surface being disposed opposite to the first surface in the vertical direction (7a' is opposite the first surface in the vertical direction),
wherein an upper surface of the first mold layer is in contact with an under surface of the second mold layer (direct contact is shown in Fig. 10).
Modifying the method of Lin ‘116 by forming the mold layer in the way disclosed by Watanabe would arrive at the claimed mold layer method. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because in each situation a mold layer is formed on an intermediately formed package to arrive at an encapsulated package (Lin ‘116: Fig. 2A; Watanabe: Fig. 10). Watanabe provides a teaching to motivate one of ordinary skill in the art before the effective filing date to incorporate the mold layer formation method in that it would improve thermal expansion characteristics of the package, thereby reducing warpage ([0050]: “a balance of thermal expansion coefficients is improved, and warpage of the semiconductor device 1 can be prevented”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed mold layer formation method because it would reduce package warping. MPEP 2143 (I)(G).
Lin ‘116 in view of Watanabe teaches the sub-semiconductor packages of the method but only teaches these packages with a generic configuration (Lin ‘116: Fig. 2A: 113; [0017]: “a stack of multiple dies”). Thus, Lin ‘116 in view of Watanabe fails to teach “each of the sub-semiconductor packages comprises a base chip and an inner mold layer on the base chip, and is spaced apart from each of the main semiconductor chips in a horizontal direction; […]
wherein the inner mold layer is in contact with both the first mold layer and the second mold layer”.
Lin discloses a method with sub-semiconductor packages, wherein:
each of the sub-semiconductor packages (Fig. 8B: 130) comprises a base chip (131) and an inner mold layer (140) on the base chip (directly on), and is spaced apart from each of the main semiconductor chips (120) in a horizontal direction; […]
wherein the inner mold layer is in contact with (at least indirect contact) both the first mold layer and the second mold layer (mold layers 150/160 are relied upon here to establish analogousness of the packages, and to show general spatial arrangements of these packages, but these mold layers are not being incorporated here in the combination of references).
Modifying the sub-semiconductor packages of the method disclosed by Lin ‘116 in view of Watanabe, by incorporating the specific configuration of Lin, would arrive at the claimed sub-semiconductor package configuration and mold layer configurations: because the mold layers of Lin ‘116 in view of Watanabe would be in contact at least indirectly with each other. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because in each situation the methods include sub-semiconductor packages comprising stacked chips performing similar functions (Lin ‘116: [0017]: “memory dies…a stack of multiple dies”; Lin: col. 9, ln. 61-col. 10, ln. 3: “stacked die package…memory dies”). A person of ordinary skill in the art before the effective filing date could have combined the teachings of Lin ‘116 with the method and sub-semiconductor package configuration of Lin in the way claimed, because each sub-semiconductor package (of Lin ‘116 or Lin) includes stacks of chips performing the same function. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed method and sub-semiconductor package configuration because it is a combination of package configurations according to known methods, with a reasonable expectation of success. MPEP 2143 (I)(A).
Lin ‘116 in view of Watanabe and Lin discloses pressing the semiconductor structure against the mold film (Watanabe: Fig. 8C: the collection of 13 and 7 are directly pressing into 11 and 12), however is silent with respect to specific force ranges used for pressing. Accordingly, Watanabe fails to teach the specific pressing configuration “pressing the semiconductor structure against the mold film at about 1 to 20 MPa”.
Yanagawa discloses a method in the same field of endeavor wherein a first and second mold are pressed together ([0049]: “male and female molds”) using a known pressing configuration ([0049]: “thereby completing molding”); the pressing configuration includes:
pressing the semiconductor structure ([0049]: “semiconductor module”) against the mold film at about 1 to 20 MPa ([0049]: “clamping pressure…14.7 MPa”).
Lin ‘116/Watanabe/Lin and Yanagawa separately disclose each element claimed. One of ordinary skill in the art before the effective filing date could have combined the method of Lin ‘116 in view of Watanabe and Lin with the pressing configuration of Yanagawa as claimed, and in combination each pressing configuration merely performs the same function as it does separately (i.e. to produce the resultant effect of a mold film). One of ordinary skill in the art before the effective filing date would have had predictable results because both Watanabe and Yanagawa teach methods with first and second molds used with pressing a semiconductor structure against a mold film (Watanabe Fig. 8C illustrates the first and second mold are pressed together with at least a force sufficient to produce the resultant effect of the mold film completely conforming to the semiconductor structure. Yanagawa teaches the first and second mold are pressed together in [0049]: “male and female molds” with at least a force sufficient to produce the resultant effect of a mold film described in [0049]: “thereby completing molding”).
Therefore, the claim would have been obvious to one of ordinary skill in the art before the effective filing date because it appears to be a mere combination of prior art element configurations according to known functional configurations yielding a predictable mold film. One would have been motivated to do so to produce a semiconductor structure enclosed by a mold film. MPEP 2143 (I)(A).
Regarding claim 15, Lin ‘116 in view of Watanabe, Lin, and Yanagawa discloses the method according to claim 12 (Watanabe: Fig. 8C), wherein a thickness of the first mold film (a plurality of thicknesses must exist when including at least: a vertical thickness of the film adjacent the sub-semiconductor packages/main semiconductor chips; as well as the portion of the film sandwiched between the sub-semiconductor packages/main semiconductor chips and the package substrate, which is a resultant dimension produced by the flip chip electrical connectors of the selected embodiment) differs from a thickness of the second mold film (since a plurality of thicknesses exist, at least one must differ from a thickness of the second mold film).
Regarding claim 17, Lin ‘116 in view of Watanabe, Lin, and Yanagawa discloses the method of claim 12 (Watanabe: Fig. 8B), wherein: the first mold film comprises a first base film ([0043]: “a first resin”) and a first filler ([0042]: “filler”); and the second mold film comprises a second base film ([0043]: “a second resin”) and a second filler ([0042]: “filler”).
Regarding claim 18, Lin ‘116 in view of Watanabe, Lin, and Yanagawa discloses the method of claim 17 (Lin: Fig. 8F), however fails to teach specific dimensional characteristics of the first and second fillers, and therefore fails to teach “wherein an average size of the first filler is smaller than an average size of the second filler”.
Lin discloses first and second mold layers (Fig. 8F: 150 and 16 respectively) respectively including first and second fillers (152 and 162 respectively), wherein the first and second filler configurations are deliberately chosen to be different
wherein an average size of the first filler is smaller than an average size of the second filler (col. 10, lines 51-61: “the average diameter of each of the fillers 152 of the underfill layer 150 is shorter than the average first length L.sub.1 of each of the first fillers 162 of the package layer 160”).
Watanabe and Lin separately disclose each element claimed. One of ordinary skill in the art before the effective filing date could have combined the method of Lin ‘116 in view of Watanabe, Lin, and Yanagawa with the filler configuration of Lin as claimed and in combination each filler configuration merely performs the same function as it does separately (i.e. to have different resultant coefficients of thermal expansion for the first and second mold layers). One of ordinary skill in the art before the effective filing date would have had predictable results because both Watanabe and Lin teach methods with deliberately varied filler configurations to produce first and second mold layers having differing coefficients of thermal expansion (Watanabe: [0041] “two types of resins having different thermal expansion coefficients”; in combination with [0042]: “different thermal expansion coefficients can be obtained by, for example, the content of a filler being changed”; Lin: col. 10, lines 51-61: “the coefficient of thermal expansion (CTE) of each of the fillers 162 of the package layer 160 is greater than the CTE of each of the fillers 152 of the underfill layer 150”).. Therefore, the claim would have been obvious to one of ordinary skill in the art before the effective filing date because it appears to be a mere combination of prior art element configurations according to known functional configurations yielding a predictable mold layer. One of ordinary skill in the art before the effective filing date would have been motivated to do so to produce a mold layer having a plurality of coefficients of thermal expansion. MPEP 2143 (I)(A).
Claims 14 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Lin ‘116 in view of Watanabe, Lin, and Yanagawa as applied to claim 12 above, and further in view of Meyer.
Regarding claim 14, Lin ‘116 in view of Watanabe, Lin, and Yanagawa discloses the method according to claim 12 (Watanabe: Fig. 8C), however fails to teach specific dimensional ranges for a thickness of the mold film, and therefore fails to teach “a thickness of the mold film is about 250 to 350 µm”.
Meyer discloses a method in the same field of endeavor with a mold film (Fig. 1: the collection of 102 with 103) including a first mold film (102) and a second mold film (103), and further teaches a thicknesses of the mold film includes at least a thickness of the first mold film ([0026]: “thickness of the first material…chosen in a range”),
wherein the thickness of the mold film is about 250 to 350 µm ([0026]: selecting 100% from “between 20 to 200% of the thickness of the semiconductor chips” and selecting 300 µm from “have a thickness of 100 µm to 300 µm or more”; these selected thickness are squarely within the claimed range);
Selecting the known mold film thickness configuration of Meyer for the mold film of Lin ‘116 in view of Watanabe, Lin, and Yanagawa would arrive at the claimed mold film thickness configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success to formulate the claimed thickness configuration because it is routine optimization within a prior art condition. Any differences in the claimed invention and the prior art may be expected to result in some differences in properties. The issue is whether the properties differ to such an extent that the difference is really unexpected. In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). Applicants have the burden of explaining the data in any declaration they proffer as evidence of non-obviousness. Ex parte Ishizaka, 24 USPQ2d 1621, 1624 (Bd. Pat. App. & Inter. 1992). An Affidavit or declaration under 37 CFR 1.132 must compare the claimed subject matter with the closest prior art to be effective to rebut a prima facie case of obviousness. In re Burckel, 592 F.2d 1175, 201 USPQ 67 (CCPA 1979). MPEP 716.02.
Therefore, it would have been obvious to one of ordinary skill in the art of manufacturing a semiconductor package before the effective filing date to determine the workable or optimal value for the thickness of the mold film through routine experimentation and optimization to obtain optimal or desired device performance because the claimed thickness is a result-effective variable and there is no evidence indicating that it is critical or produces any unexpected results and it has been held that it is not inventive to discover the optimum or workable ranges of a result-effective variable within given prior art conditions by routine experimentation. Moreover, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669,149 USPQ 47 (CCPA 1966). MPEP 2144.04 (IV)(A).
Regarding claim 16, Lin ‘116 in view of Watanabe, Lin, and Yanagawa discloses the method of claim 12 (Watanabe: Fig. 8C), however fails to teach specific dimensional ranges for thicknesses of the first and second mold films, and therefore fails to teach “wherein a thickness of the first mold film is smaller than a thickness of the second mold film”.
Meyer discloses a method in the same field of endeavor with a mold film (Fig. 1: the collection of 102 with 103) including a first mold film (102) and a second mold film (103), and further teaches a thicknesses of the first mold film ([0026]: “thickness of the first material…chosen in a range”),
wherein a thickness of the first mold film ([0026]: selecting 20% for 102 from “between 20 to 200% of the thickness of the semiconductor chips”) is smaller than a thickness of the second mold film (103 is covering the remainder of the chip, i.e., 80%. Thus, 20% is smaller than 80%);
Selecting the known first and second mold film thickness configuration of Meyer for the first and second mold film of Lin ‘116 in view of Watanabe, Lin, and Yanagawa would arrive at the claimed thickness configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success to formulate the claimed thickness configuration because it is routine optimization within a prior art condition. Any differences in the claimed invention and the prior art may be expected to result in some differences in properties. The issue is whether the properties differ to such an extent that the difference is really unexpected. In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). Applicants have the burden of explaining the data in any declaration they proffer as evidence of non-obviousness. Ex parte Ishizaka, 24 USPQ2d 1621, 1624 (Bd. Pat. App. & Inter. 1992). An Affidavit or declaration under 37 CFR 1.132 must compare the claimed subject matter with the closest prior art to be effective to rebut a prima facie case of obviousness. In re Burckel, 592 F.2d 1175, 201 USPQ 67 (CCPA 1979). MPEP 716.02.
Therefore, it would have been obvious to one of ordinary skill in the art of manufacturing a semiconductor package before the effective filing date to determine the workable or optimal value for the thicknesses of the first and second mold films through routine experimentation and optimization to obtain optimal or desired device performance because the claimed thicknesses are a result-effective variable and there is no evidence indicating that they are critical or produces any unexpected results and it has been held that it is not inventive to discover the optimum or workable ranges of a result-effective variable within given prior art conditions by routine experimentation. Moreover, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669,149 USPQ 47 (CCPA 1966). MPEP 2144.04 (IV)(A).
Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lin ‘116, Watanabe, Lin, and Yanagawa as applied to claims 17 and 12 above, and further in view of Takasugi.
Regarding claim 19, Lin ‘116 in view of Watanabe, Lin, and Yanagawa discloses the method of claim 17 (Watanabe: Fig. 8B), however fails to teach specific ranges for particular physical properties of the first and second base films, i.e., “wherein a viscosity of the first base film differs from a viscosity of the second base film”.
Takasugi discloses a method with first and second base films in the same field of endeavor (Fig. 1: films 6 and 7 respectively), wherein the first base film surrounds electrical connectors (5) and the second base film completely encapsulated the remainder of a package (remainder of 4). Takasugi further teaches:
a viscosity of the first base film differs from a viscosity of the second base film (pg. 8 to pg. 9 of translation: “low viscosity and fluidity is preferable” and “high viscosity” respectively).
Modifying the viscosities of the first and second base films of Lin ‘116 in view of Watanabe, Lin, and Yanagawa, by incorporating the viscosity teachings of Takasugi would arrive at the claimed viscosity configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success because in each situation, the first base film has utility surrounding electrical connectors (Watanabe: [0107]: “the first resin is filled up to a bottom surface 7b' of the uppermost semiconductor chip” would result in film 11 surrounding the flip chip electrical connectors of the selected embodiment; Takasugi: Fig. 1: layer 6 on connectors 5) and discloses the second base film has utility encapsulating the remainder of the package (Watanabe: [0104]: “the second resin 12 is formed over the first resin 11 and the uppermost semiconductor chip”; Takasugi: Fig. 7: layer 7 on package 4). Takasugi provides a teaching to motivate one of ordinary skill in the art before the effective filing date to modify the viscosity configuration of Lin ‘116 in view of Watanabe, Lin, and Yanagawa in that it would prevent air bubbles among the electrical connectors while still enabling a strong package (pg. 8 last paragraph to pg. 9 first paragraph of translation: “to prevent air bubbles”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed viscosity configuration because it would prevent air bubbles while maintaining package strength. MPEP 2143 (I)(G).
Regarding claim 20, Lin ‘116 in view of Watanabe, Lin, and Yanagawa discloses the method of claim 17 with first and second base films (Watanabe: Fig. 8B), however fails to teach specific ranges for particular physical properties of the first and second base films, i.e., “wherein a viscosity of the first base film is lower than a viscosity of the second base film”.
Takasugi discloses a method with first and second base films in the same field of endeavor (Fig. 1: 6 and 7 respectively), wherein the first base film surrounds electrical connectors (5) and the second base film completely encapsulated the remainder of a package (remainder of 4). Takasugi further teaches:
a viscosity of the first base film is lower than a viscosity of the second base film (pg. 8 to pg. 9 of translation: “low viscosity and fluidity is preferable” and “high viscosity” respectively).
Modifying the viscosities of the first and second base films of Lin ‘116 in view of Watanabe, Lin, and Yanagawa, by incorporating the viscosity teachings of Takasugi would arrive at the claimed viscosity configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success because in each situation, the first base film has utility surrounding electrical connectors (Watanabe: [0107]: “the first resin is filled up to a bottom surface 7b' of the uppermost semiconductor chip” would result in film 11 surrounding the flip chip electrical connectors of the selected embodiment; Takasugi: Fig. 1: layer 6 on connectors 5) and discloses the second base film has utility encapsulating the remainder of the package (Watanabe: [0104]: “the second resin 12 is formed over the first resin 11 and the uppermost semiconductor chip”; Takasugi: Fig. 7: layer 7 on package 4). Takasugi provides a teaching to motivate one of ordinary skill in the art before the effective filing date to modify the viscosity configuration of Lin ‘116 in view of Watanabe, Lin, and Yanagawa in that it would prevent air bubbles among the electrical connectors while still enabling a strong package (pg. 8 last paragraph to pg. 9 first paragraph of translation: “to prevent air bubbles”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed viscosity configuration because it would prevent air bubbles while maintaining package strength. MPEP 2143 (I)(G).
Response to Arguments
Applicant's arguments filed 5/8/2026 have been fully considered but they are not persuasive.
Applicant argues:
Applicant argues with respect to amended claim 1 that “claim 1 distinguishes over the proposed combination of Lin, Watanabe, and Lin '164, and is in condition for allowance. Independent claim 12 recites features similar but not identical to independent claim 1. Accordingly, Applicant respectfully requests that the rejection be withdrawn with respect to all pending claims”. Remarks at pg. 10.
Examiner’s reply:
The examiner understands Applicants remarks regarding the contended distinctions between the claimed invention and the prior art. However, the examiner finds the claim as written reasonably encompassing mold layer contact configurations beyond that which has been disclosed. For example, the claim as written does not require contact in any particular direction, and more importantly, the claim reasonably includes direct or indirect contact. Accordingly, since the presence of all three mold layers has been rendered obvious in the instant Office action, there must necessarily be at least indirect contact among them. MPEP 2111.
Conclusion
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/WILLIAM H ANDERSON/ Examiner, Art Unit 2817
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