CTNF 18/419,436 CTNF 101649 Detailed Action Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15-aia AIA Claim(s) 1-4 and 23 is/are rejected under 35 U.S.C. 102 (a)(1) and (a)(2) as being anticipated by Cho et al. (Pub. No. US 20200381505 A1), hereinafter referred to as Cho . Regarding claim 1, Cho teaches a display apparatus comprising: a substrate including a display area, and a peripheral area outside the display area (Figs. 1 & 2, display device 10, display area DA, peripheral area PA, substrate 100; ¶5 & 82); a plurality of data lines crossing the display area (Fig. 2 data lines DL; ¶90-91); a plurality of spider lines in the peripheral area, each of the plurality of spider lines being electrically connected to a corresponding data line from among the plurality of data lines (Fig. 3, connection lines 200, first connection line 210, second connection line 220, third connection line 230; ¶93-94); and a plurality of protective circuits, each of the plurality of protective circuits being electrically connected to a corresponding spider line from among the plurality of spider lines (Figs. 23 and 25, first connection line 210, second connection line 22, third connection line 230, electrostatic discharge (ESD) protection circuit; ¶164, 169, 180-181). PNG media_image1.png 1015 716 media_image1.png Greyscale PNG media_image2.png 945 740 media_image2.png Greyscale PNG media_image3.png 619 413 media_image3.png Greyscale Regarding claim 2, Cho further teaches the plurality of data lines correspond one-to-one to the plurality of spider lines (Fig. 3 & 4, connection lines 200, first connection line 210, second connection line 220, third connection line 230, data lines DL; ¶92-94). Regarding claim 3, Cho further teaches the plurality of spider lines correspond one-to-one to the plurality of protective circuits (Figs. 5A, 5B, Fig. 23, Fig. 25, electrostatic discharge (ESD) protection circuit, bridge 250, connection lines 200, first connection line 210, second connection line 220, third connection line 230; ¶100,164,169). Regarding claim 4, Cho further teaches the plurality of protective circuits are located between the plurality of spider lines (Figs. 5A, 5B, Fig. 23, Fig. 25, electrostatic discharge (ESD) protection circuit, bridge 250, sections 212; ¶100,164,169). Regarding claim 23, Cho teaches a display apparatus comprising: a substrate including a display area, and a peripheral area outside the display area (Figs. 1 & 2, display device 10, display area DA, peripheral area PA, substrate 100, ¶12, ¶82); a plurality of pads located along one edge of the substrate in the peripheral area (Figs. 2 & 3, pad area PADA, plurality of pads PAD; ¶12,¶20-21); and a plurality of protective circuits in the peripheral area between the display area and the plurality of pads (Figs. 3 & 25, electrostatic discharge (ESD) protection circuit, portions B, E, and D in the peripheral area PA; ¶98 & ¶169) . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim (s) 5 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cho as applied to claim 1 above, and in view of Moon et al. (Pub. No. US 20210098550 A1), hereinafter referred to as Moon . Regarding claim 5, Cho teaches the display apparatus of claim 1, further comprising a plurality of power lines crossing the display area (Figs. 2 & 7, power supply voltage line 172; ¶90,105-120) and a power supply line being electrically connected to the plurality of power lines (¶97). However, Cho does not explicitly teach a power supply line in the peripheral area over the plurality of spider lines. Moon teaches a power supply line in the peripheral area over the plurality of spider lines (Fig. 2, Fan-out portion 150, first power supply line 160; ¶68). Cho and Moon are analogous art as they are in the same field of endeavor of display devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Cho to incorporate the teachings of Moon to have the power supply line in the peripheral area be over the plurality of spider lines. For the purpose of reducing the size of the peripheral area. Regarding claim 14, Cho further teaches a common electrode covering the display area and a common voltage line electrically connected to the common electrode (Figs. 17 & 22, opposite electrode 430, second power supply voltage ELVSS; ¶120,147,153,161). However, Cho does not explicitly teach the common voltage line being in the peripheral area over the plurality of spider lines. Moon teaches a power supply line in the peripheral area over the plurality of spider lines (Fig. 2, Fan-out portion 150, first power supply line 160; ¶68). Cho and Moon are analogous art as they are in the same field of endeavor of display devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Cho to incorporate the teachings of Moon to have the common voltage line in the peripheral area be over the plurality of spider lines. For the purpose of reducing the size and unused space of the peripheral area . 07-22-aia AIA Claim (s) 6 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cho in view of Moon as applied to claim s 5 and 14 above, and further in view of Lee et al. (Pub. No. US 20220157915 A1), hereinafter referred to as Lee . Regarding claim 6, Cho in view of Moon does not explicitly teach a protective transistor of each of the plurality of protective circuits being electrically connected to the power supply line. Lee teaches a protective transistor of each of the plurality of protective circuits being electrically connected to the power supply line (Lee: Fig. 6, electrostatic protection circuit PC, first and second power lines ELVDL and ELVSL, first transistor PT1, second transistor PT2; ¶116 – 125). Cho, Moon, and Lee are all analogous art as they are all in the same field of endeavor of display devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Cho in view of Moon to incorporate the teaching of Lee to have a protective transistor of each of the plurality of protective circuits being electrically connected to the power supply line. For the purpose of preventing electrostatic discharge related to the power supply line from damaging the display device. Regarding claim 15, Cho in view of Moon does not explicitly teach a protective transistor of each of the plurality of protective circuits being electrically connected to the common voltage line. Lee teaches a protective transistor of each of the plurality of protective circuits being electrically connected to the common voltage line (Lee: Fig. 6, electrostatic protection circuit PC, first and second power lines ELVDL and ELVSL, first transistor PT1, second transistor PT2; ¶116 – 125). Cho, Moon, and Lee are all analogous art as they are all in the same field of endeavor of display devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Cho in view of Moon to incorporate the teaching of Lee to have a protective transistor of each of the plurality of protective circuits being electrically connected to the common voltage line. For the purpose of preventing electrostatic discharge related to the common voltage line from damaging the display device . 07-22-aia AIA Claim (s) 7-10 and 16-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cho in view of Moon and Lee as applied to claim s 6 and 15 above, and further in view of Kwak (US Patent No. 8,665,191) . Regarding Claim 7, Cho teaches the protective circuit being electrically connected to the corresponding spider line through a bridge line (Figs. 5A, 5B, 6A, & 6B, section 212, bridge 250; ¶100-103). However, Cho does not explicitly teach one end of a protective semiconductor layer of each of the plurality of protective circuits being electrically connected to the power supply line. Lee teaches the protective circuit being electrically connected to the power supply line (Fig. 6, electrostatic protection circuit PC, first and second power lines ELVDL and ELVSL; ¶117). Cho and Lee are analogous art as they are in the same field of endeavor of display devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Cho to incorporate the teachings of Lee to have the protective circuits be electrically connected to the power supply line. For the purpose of preventing electrostatic discharge related to the power supply line from damaging the display device. However, Cho in view of Moon and Lee does not explicitly teach the protective semiconductor layer. Kwak teaches the protective circuits having a protective semiconductor layer (Figs. 3A & 3B, semiconductor layer 320; Col. 5, line 7 – Col. 6, line 32). Cho, Kwak, and Lee are all analogous are as they are in the same field of display devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Cho in view of Moon and Lee to incorporate the teachings of Kwak to have a protective semiconductor layer such that one end of the protective semiconductor layer of each of the plurality of protective circuits be electrically connected to the power supply line, and another end of the protective semiconductor layer be electrically connected to the corresponding spider line through a bridge line. For the purpose of protecting the display device from electrostatic discharge. Regarding claim 8, Cho further teaches the power supply line including a plurality of through holes corresponding to the plurality of protective circuits, and wherein, in a plan view, the bridge line is located inside a corresponding through hole from among the plurality of through holes (Figs. 17, 18, 20, & 22, bridge 250, power supply line 172, GAP1, GAP2, contact holes C; ¶100, 159-160). PNG media_image4.png 636 651 media_image4.png Greyscale Regarding claim 9, Cho further teaches the bridge line and the power supply line being at the same layer as each other (Fig. 22, power supply line 172, bridge 250; ¶159). Regarding claim 10, Cho further teaches each of the plurality of spider lines including a portion located at the same layer as that of a bottom conductive layer (Fig. 6A, insulation surface 120, sections 212, third insulating layer 332; ¶102 and 144). However, Cho does not teach the bottom conductive layer being located between the substrate and a first protective gate electrode of each of the plurality of protective circuits. Lee teaches the bottom conductive layer being located between the substrate and the first protective gate electrode of each of the plurality of protective circuits (Fig. 8, first conductive layer 120, first upper gate electrode GE1, ¶124-129). Cho, Moon, Lee, and Kwak are all analogous are as they are in the same field of endeavor of display devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Cho to incorporate the teachings of Lee to have the bottom conductive layer located between the substrate and the first protective gate electrode of each of the plurality of protective circuits. For the purpose of protecting the display device from electrostatic discharge. Regarding claim 16, Cho teaches the protective circuit being electrically connected to the corresponding spider line through a bridge line (Figs. 5A, 5B, 6A, & 6B, section 212, bridge 250; ¶100-103). However, Cho does not explicitly teach one end of a protective semiconductor layer of each of the plurality of protective circuits being electrically connected to the power supply line. Lee teaches the protective circuit being electrically connected to the common voltage line (Fig. 6, electrostatic protection circuit PC, first and second power lines ELVDL and ELVSL; ¶117). Cho and Lee are analogous art as they are in the same field of endeavor of display devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Cho to incorporate the teachings of Lee to have the protective circuits be electrically connected to the common voltage line. For the purpose of preventing electrostatic discharge related to the common voltage line from damaging the display device. However, Cho in view of Moon and Lee does not explicitly teach the protective semiconductor layer. Kwak teaches the protective circuits having a protective semiconductor layer (Figs. 3A & 3B, semiconductor layer 320; Col. 5, line 7 – Col. 6, line 32). Cho, Kwak, and Lee are all analogous are as they are in the same field of display devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Cho in view of Moon and Lee to incorporate the teachings of Kwak to have a protective semiconductor layer such that one end of the protective semiconductor layer of each of the plurality of protective circuits be electrically connected to the common voltage line, and another end of the protective semiconductor layer be electrically connected to the corresponding spider line through a bridge line. For the purpose of protecting the display device from electrostatic discharge. Regarding claim 17, Cho further teaches the common voltage line including a plurality of through holes corresponding to the plurality of protective circuits, and wherein, in a plan view, the bridge line is located inside a corresponding through hole from among the plurality of through holes (Figs. 17, 18, 20, & 22, bridge 250, power supply line 172, GAP1, GAP2, contact holes C; ¶100, 159-160). Regarding claim 18, Cho further teaches the bridge line and the common voltage line being at the same layer as each other (Fig. 22, power supply line 172, bridge 250; ¶159). Regarding claim 19, Cho further teaches each of the plurality of spider lines including a portion located at the same layer as that of a bottom conductive layer (Fig. 6A, insulation surface 120, sections 212, third insulating layer 332; ¶102 and 144). However, Cho does not teach the bottom conductive layer being located between the substrate and a first protective gate electrode of each of the plurality of protective circuits. Lee teaches the bottom conductive layer being located between the substrate and the first protective gate electrode of each of the plurality of protective circuits (Fig. 8, first conductive layer 120, first upper gate electrode GE1, ¶124-129). Cho, Moon, Lee, and Kwak are all analogous are as they are in the same field of endeavor of display devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Cho to incorporate the teachings of Lee to have the bottom conductive layer located between the substrate and the first protective gate electrode of each of the plurality of protective circuits. For the purpose of protecting the display device from electrostatic discharge . 07-22-aia AIA Claim (s) 11-12 and 20-21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cho in view of Moon, Lee, and Kwak as applied to claim s 8, 10, and 17 above, and further in view of Cho et al. (Pub. No. US 20210273035 A1), hereinafter referred to as Cho 2021 . Regarding claim 11, Cho in view of Moon, Lee, and Kwak does not explicitly teach each of the plurality of spider lines including a portion located at the same layer as that of a first protective gate electrode of each of the plurality of protective circuits. Cho 2021 teaches the plurality of spider lines including a portion located at the same layer as that of a first gate electrode (first data spider line, gate electrode; ¶21). Cho, Moon, Lee, Kwak, and Cho 2021 are all analogous are as they are in the same field of endeavor of display devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Cho in view of Moon, Lee, and Kwak to incorporate the teachings of Cho 2021 to have the plurality of spider lines include a portion located at the same layer as that of a first protective gate electrode of each of the plurality of protective circuits. For the purpose of reducing the width of the peripheral area outside of the display area, as recognized by Cho 2021, and to protect the display device from electrostatic discharge. Regarding claim 12, Cho in view of Moon, Lee and Kwak further teaches each of the plurality of spider lines including a first portion and a section portion (Cho: Fig. 5A, sections 212; ¶100), wherein the second portion is located at the same layer as that of a bottom conductive layer located between the first protective gate electrode and the substrate (Cho: Fig. 6A, insulation surface 120, sections 212, third insulating layer 332; ¶102 and 144; and Lee: Fig. 8, first conductive layer 120, first upper gate electrode GE1, ¶124-129; see claim 10 above for further detail), and wherein the first portion is electrically connected to the second portion (Cho: Fig. 5A, bridge 250, sections 212; ¶100). However, Cho in view of Moon, Lee, and Kwak does not explicitly teach the first portion being located at the same layer as that of a first protective gate electrode of each of the plurality of protective circuits. Cho 2021 teaches the first portion being located at the same layer as that of a gate electrode (first data spider line, gate electrode; ¶21). Cho, Moon, Lee, Kwak, and Cho 2021 are all analogous are as they are in the same field of endeavor of display devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Cho in view of Moon, Lee, and Kwak to incorporate the teachings of Cho 2021 to have the plurality of spider lines include a first portion located at the same layer as that of a first protective gate electrode of each of the plurality of protective circuits. For the purpose of reducing the width of the peripheral area outside of the display area, as recognized by Cho 2021, and to protect the display device from electrostatic discharge. Regarding claim 20, Cho in view of Moon, Lee, and Kwak does not explicitly teach each of the plurality of spider lines including a portion located at the same layer as that of a first protective gate electrode of each of the plurality of protective circuits. Cho 2021 teaches the plurality of spider lines including a portion located at the same layer as that of a first gate electrode (first data spider line, gate electrode; ¶21). Cho, Moon, Lee, Kwak, and Cho 2021 are all analogous are as they are in the same field of endeavor of display devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Cho in view of Moon, Lee, and Kwak to incorporate the teachings of Cho 2021 to have the plurality of spider lines include a portion located at the same layer as that of a first protective gate electrode of each of the plurality of protective circuits. For the purpose of reducing the width of the peripheral area outside of the display area, as recognized by Cho 2021, and to protect the display device from electrostatic discharge. Regarding claim 21, Cho in view of Moon, Lee and Kwak further teaches each of the plurality of spider lines including a first portion and a section portion (Cho: Fig. 5A, sections 212; ¶100), wherein the second portion is located at the same layer as that of a bottom conductive layer located between the first protective gate electrode and the substrate (Cho: Fig. 6A, insulation surface 120, sections 212, third insulating layer 332; ¶102 and 144; and Lee: Fig. 8, first conductive layer 120, first upper gate electrode GE1, ¶124-129; see claim 10 above for further detail), and wherein the first portion is electrically connected to the second portion (Cho: Fig. 5A, bridge 250, sections 212; ¶100). However, Cho in view of Moon, Lee, and Kwak does not explicitly teach the first portion being located at the same layer as that of a first protective gate electrode of each of the plurality of protective circuits. Cho 2021 teaches the first portion being located at the same layer as that of a gate electrode (first data spider line, gate electrode; ¶21). Cho, Moon, Lee, Kwak, and Cho 2021 are all analogous are as they are in the same field of endeavor of display devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Cho in view of Moon, Lee, and Kwak to incorporate the teachings of Cho 2021 to have the plurality of spider lines include a first portion located at the same layer as that of a first protective gate electrode of each of the plurality of protective circuits. For the purpose of reducing the width of the peripheral area outside of the display area, as recognized by Cho 2021, and to protect the display device from electrostatic discharge . 07-22-aia AIA Claim (s) 13 and 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cho in view of Moon, Lee, Kwak, and Cho 2021 as applied to claim s 12 and 21 above, and further in view of Jeong et al (Pub. No. US 20210173244 A1), hereinafter referred to as Jeong . Regarding claim 13, Cho in view of Moon, Lee, Kwak, and Cho 2021 teaches the plurality of protective circuits including a first protective gate electrode (see claim 12 above). However, Cho in view of Moon, Lee, Kwak, and Cho 2021 do not explicitly teach each of the plurality of protective circuits including a second protective gate electrode, wherein the second protective gate electrode overlaps with the first protective gate electrode, is located at the same layer as that of the bottom conductive layer and is electrically connected to the first protective gate electrode. Jeong teaches the plurality of protective circuits including a second protective gate electrode (¶79, 126, 184), wherein the second protective gate electrode overlaps with the first gate electrode (Fig. 2, second gate electrode GE2, first gate electrode GE1; ¶74), is located at the same layer as that of the bottom conductive layer (¶88), and is electrically connected to the first protective gate electrode (¶83). Cho, Moon, Lee, Kwak, Cho 2021, and Jeong are all analogous are as they are in the same field of endeavor of display devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Cho in view of Moon, Lee, Kwak, and Cho 2021 to incorporate the teachings of Jeong to have each of the plurality of protective circuits includes a second protective gate electrode, and wherein the second protective gate electrode overlaps with the first protective gate electrode, is located at the same layer as that of the bottom conductive layer, and is electrically connected to the first protective gate electrode. For the purpose of having the transistors in the protective circuit be double gate transistors and protecting the display device from electrostatic discharge. Regarding claim 22, Cho in view of Moon, Lee, Kwak, and Cho 2021 teaches the plurality of protective circuits including a first protective gate electrode (see claim 21 above). However, Cho in view of Moon, Lee, Kwak, and Cho 2021 do not explicitly teach each of the plurality of protective circuits including a second protective gate electrode, wherein the second protective gate electrode overlaps with the first protective gate electrode, is located at the same layer as that of the bottom conductive layer and is electrically connected to the first protective gate electrode. Jeong teaches the plurality of protective circuits including a second protective gate electrode (¶79, 126, 184), wherein the second protective gate electrode overlaps with the first gate electrode (Fig. 2, second gate electrode GE2, first gate electrode GE1; ¶74), is located at the same layer as that of the bottom conductive layer (¶88), and is electrically connected to the first protective gate electrode (¶83). Cho, Moon, Lee, Kwak, Cho 2021, and Jeong are all analogous are as they are in the same field of endeavor of display devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify Cho in view of Moon, Lee, Kwak, and Cho 2021 to incorporate the teachings of Jeong to have each of the plurality of protective circuits includes a second protective gate electrode, and wherein the second protective gate electrode overlaps with the first protective gate electrode, is located at the same layer as that of the bottom conductive layer, and is electrically connected to the first protective gate electrode. For the purpose of having the transistors in the protective circuit be double gate transistors and protecting the display device from electrostatic discharge . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Kang et al. (Pub. No. US 20190324332 A1), Jung et al (US Patent No. 9,153,192 B2), and Kim (Pub. No. US 20200365576 A1) .. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ETHAN ALEXANDER TUTTLE whose telephone number is (571)272-7055. The examiner can normally be reached Monday - Friday, 9 am - 5 pm ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo can be reached at 571-272-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897 /E.A.T./ Examiner, Art Unit 2897 Application/Control Number: 18/419,436 Page 2 Art Unit: 2897 Application/Control Number: 18/419,436 Page 3 Art Unit: 2897 Application/Control Number: 18/419,436 Page 4 Art Unit: 2897 Application/Control Number: 18/419,436 Page 5 Art Unit: 2897 Application/Control Number: 18/419,436 Page 6 Art Unit: 2897 Application/Control Number: 18/419,436 Page 7 Art Unit: 2897 Application/Control Number: 18/419,436 Page 9 Art Unit: 2897 Application/Control Number: 18/419,436 Page 10 Art Unit: 2897 Application/Control Number: 18/419,436 Page 11 Art Unit: 2897 Application/Control Number: 18/419,436 Page 12 Art Unit: 2897 Application/Control Number: 18/419,436 Page 13 Art Unit: 2897 Application/Control Number: 18/419,436 Page 14 Art Unit: 2897 Application/Control Number: 18/419,436 Page 15 Art Unit: 2897 Application/Control Number: 18/419,436 Page 16 Art Unit: 2897 Application/Control Number: 18/419,436 Page 17 Art Unit: 2897 Application/Control Number: 18/419,436 Page 18 Art Unit: 2897
