Prosecution Insights
Last updated: October 25, 2026
Application No. 18/419,445

MECHANICAL STIFFENER FOR INTEGRATED CIRCUIT PACKAGE WITH VARYING HEAT DISSIPATION MODES

Non-Final OA §103§112
Filed
Jan 22, 2024
Priority
Jan 24, 2023 — provisional 63/440,883
Examiner
MCCALL SHEPARD, SONYA D
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Marvell Asia Pte. Ltd.
OA Round
3 (Non-Final)
93%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
96%
With Interview

Examiner Intelligence

Grants 93% — above average
93%
Career Allowance Rate
1114 granted / 1200 resolved
+24.8% vs TC avg
Minimal +4% lift
Without
With
+3.5%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 0m
Avg Prosecution
36 currently pending
Career history
1234
Total Applications
across all art units

Statute-Specific Performance

§101
0.7%
-39.3% vs TC avg
§103
49.8%
+9.8% vs TC avg
§102
33.5%
-6.5% vs TC avg
§112
13.6%
-26.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1200 resolved cases

Office Action

§103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 09/14/2026 has been entered. Claim Objections Claim 25 is objected to because of the following informalities: 25. (New) . Appropriate correction is required. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 14-16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Regarding claim 14, the metes and bounds of the claimed invention are vague and ill-defined as a result of uncertainty in the different boundaries and new limitations “at least partially exposing, through an opening in the stiffener”. The claim is indefinite because it is not clear if the opening in the stiffener exposing a surface of the second integrated circuit die is the same as the opening corresponding to a position of the at least one electronic device mounted to the substrate as recited in claim 13. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1, 5-7, 9, 13, 17-19, 21, 25 and 26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lai et al. US 2021/0305122. PNG media_image1.png 631 505 media_image1.png Greyscale PNG media_image2.png 485 802 media_image2.png Greyscale Regarding claim 1, Lai et al. in Figs. 9 and 10 and [0012]-[0028] disclose an integrated circuit device package 50C comprising: a substrate 200; at least two integrated circuit dies 110, 120, 130 [0012] mounted to the substrate 200; at least one electronic device 140, 150 [0012] mounted to the substrate 200; a thermally conductive stiffener 300 [0016] (e.g. frame) attached to the substrate 200; and an electrically conductive adhesive 302 [0016] disposed between the thermally conductive stiffener 300 and the substrate 200 for attaching the stiffener 300 to the substrate 200, the adhesive 302 and the stiffener 300 being configured to form a shielding enclosure to shield one or more of the at least two integrated circuit dies from electromagnetic interference ([0016] states In some embodiments, the frame structure 300 may be electrically connected with the circuit substrate 200 and further function as a shielding structure (e.g. EMI shielding) when the adhesive 302 includes an electrically conductive adhesive.), the stiffener: having a first portion (Fig. 10, annotated above) in a thermally conductive relationship ([0017] 136, thermal conductive adhesive) with a surface of a first integrated circuit die 130 among the at least two integrated circuit dies 110, 120, 130 to provide a first heat dissipation mode (e.g. [0017], 136, thermally conductive adhesive formed on top surfaces of the dies with heat sink lid 400), for the first integrated circuit die 130, and having a second portion (Fig. 10, annotated above), different from the first portion (i.e. separate from one another and not a whole), the second portion configured to provide a second heat dissipation mode (e.g. [0017] 126, thermally conductive adhesive formed on top surfaces of the dies with heat sink lid 400), different from the first heat dissipation mode (i.e. separate from one another and not a whole), for a second integrated circuit die 120 among the at least two integrated circuit dies 110, 120, 130, wherein the stiffener ([0016] e.g. 300A and 300B) at least partially defines at least one opening corresponding to a position of the at least one electronic device 140, 150 mounted to the substrate 200. Lai et al. do not expressly disclose the stiffener (e.g. frame 300, support) attached to the substrate 200 to counteract warping of the substrate 200. However, the claim limitation “a thermally conductive stiffener attached to the substrate to counteract warping of the substrate”, is drawn to a method of use or a device under test. The intended use and other types of functional language must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim. In re Casey,152 USPQ 235 (CCPA 1967); In re Otto, 136 USPQ 458, 459 (CCPA 1963). In this case, the structure is capable of performing this use. Regarding claim 5, Lai et al. in Figs. 9 and 10 and [0012]-[0028] teach the device package 50C of claim 1, further comprising a heat sink 400 disposed in a thermally conductive relationship with the stiffener 300, the heat sink 400 being configured to dissipate heat from the first integrated circuit die 130 among the at least two integrated circuit dies 110, 120, 130. Regarding claim 6, Lai et al. in Figs. 9 and 10 and [0012]-[0028] teach the device package 50C of claim 1, further comprising a thermal interface material (TIM) 136 [0017] disposed between the first portion of the stiffener (e.g. including elements 300 and 400) and the surface of the first integrated circuit die 130 among the at least two integrated circuit dies 110, 120, 130, the TIM 136 [0017] thermally coupling the first portion of the stiffener 300 to the first integrated circuit die 130 among the at least two integrated circuit dies 110, 120, 130. Regarding claim 7, Lai et al. in Figs. 9 and 10 and [0012]-[0028] teach the device package 50C of claim 6, wherein the TIM 136 [0017] comprises a thermally-conductive polymer. Regarding claim 9, Lai et al. in Figs. 9 and 10 and [0012]-[0028] teach the device package 50C of claim 1, wherein the stiffener 300 comprises at least one of stainless steel [0016] or nickel-coated copper. Regarding claim 13, Lai et al. in Figs. 9 and 10 and [0012]-[0028] disclose a method for packaging an integrated circuit comprising a substrate 200 [0012], at least one electronic device 140, 150 [0012] mounted to the substrate 200, and at least two integrated circuit dies 110, 120, 130 [0012] mounted to the substrate 200, the method comprising: attaching a thermally conductive stiffener 300 [0016] (e.g. frame) to the substrate 200 with an electrically conductive adhesive 302 [0016] disposed between the thermally conductive stiffener 300 and the substrate 200, and to form a shielding enclosure to shield one or more of the at least two integrated circuit dies 110, 120, 130 from electromagnetic interference ([0016] states In some embodiments, the frame structure 300 may be electrically connected with the circuit substrate 200 and further function as a shielding structure (e.g. EMI shielding) when the adhesive 302 includes an electrically conductive adhesive.), the stiffener 300 at least partially defining at least one opening 300A and 300B corresponding to a position of the at least one electronic device 140, 150 mounted to the substrate 200; arranging a first portion of the stiffener in a thermally conductive relationship with a surface of a first integrated circuit die 130 among the at least two integrated circuit dies to provide a first heat dissipation mode for the first integrated circuit die (e.g. [0017], 136, thermally conductive adhesive formed on top surfaces of the dies with heat sink lid 400) among the at least two integrated circuit dies; and arranging a second portion of the stiffener, different from the first portion (i.e. separate from one another and not a whole), to provide a second heat dissipation mode (e.g. [0017], 126, thermally conductive adhesive formed on top surfaces of the dies with heat sink lid 400), different from the first heat dissipation mode, for a second integrated circuit die 120 among the at least two integrated circuit dies. Lai et al. do not expressly disclose the stiffener (e.g. frame 300, support) attached to the substrate 200 to counteract warping of the substrate 200. However, the claim limitation “attaching a thermally conductive stiffener to the substrate, to counteract warping of the substrate”, is drawn to a method of use or a device under test. The intended use and other types of functional language must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim. In re Casey,152 USPQ 235 (CCPA 1967); In re Otto, 136 USPQ 458, 459 (CCPA 1963). In this case, the structure is capable of performing this use. Regarding claim 17, Lai et al. in Figs. 9 and 10 and [0012]-[0028] teach the method according to claim 13 for packaging an integrated circuit, further comprising a heat sink 400 disposed in a thermally conductive relationship 126, 136 [0017] with the stiffener 300, the heat sink 400 being configured to dissipate heat from the first integrated circuit die 130 among the at least two integrated circuit dies 110, 120, 130. Regarding claim 18, Lai et al. in Figs. 9 and 10 and [0012]-[0028] teach the method according to claim 13 for packaging an integrated circuit, further comprising disposing a thermal interface material (TIM) 136 [0017] between the first portion of the stiffener 300A and the surface of the first integrated circuit die 130 among the at least two integrated circuit dies 110, 120, 130, the TIM 136 [0017] thermally coupling the first portion of the stiffener 300 to the first integrated circuit die 130 among the at least two integrated circuit dies 110, 120, 130. Regarding claim 19, Lai et al. in Figs. 9 and 10 and [0012]-[0028] teach the method according to claim 18 for packaging an integrated circuit, wherein disposing the TIM comprises disposing a heat-dissipating polymer 136 [0017]. Regarding claim 21, Lai et al. in Figs. 9 and 10 and [0012]-[0028] teach the method according to claim 13 for packaging an integrated circuit, wherein attaching the stiffener 300 comprises attaching a stiffener comprising at least one of stainless steel [0016] or nickel-coated copper. Regarding claim 25, Lai et al. in Figs. 9 and 10 and [0012]-[0028] teach the method according to claim 13 for packaging an integrated circuit, wherein: the stiffener 300 includes an outer perimeter 300A Fig. 9; and the at least one opening corresponding to the position of the at least one electronic device 140, 150 is disposed at the outer perimeter Fig. 9. Regarding claim 26, Lai et al. in Figs. 9 and 10 and [0012]-[0028] teach the device package of claim 1, wherein: the stiffener 300 includes an outer perimeter 300A Fig. 9; and the at least one opening corresponding to the position of the at least one electronic device 140, 150 is disposed at the outer perimeter Fig. 9. Claim(s) 8 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lai et al. as applied to claims 6 and 18 above, and further in view of Chen et al. US 2015/0162307. Regarding claim 8, Lai et al. in Figs. 9 and 10 and [0012]-[0028] teach the device package of claim 6, but do not expressly teach wherein the TIM is a metallic TIM comprising at least one of indium or gallium. Chen et al. in Fig. 1E and [0019] teach a thermal interface material TIM 58 may be a polymer, including thermal conductive fillers such as indium that increase the effective Tk of the TIM. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings Chen et al. in the device package of Lai et al. for the purpose of increasing the effective thermal conductivity of the thermal interface material. Regarding claim 20, Lai et al. in Figs. 9 and 10 and [0012]-[0028] teach the method according to claim 18 for packaging an integrated circuit, but do not expressly teach wherein disposing the TIM comprises disposing a metallic TIM comprising at least one of indium or gallium. Chen et al. in Fig. 1E and [0019] teach a thermal interface material TIM 58 may be a polymer, including thermal conductive fillers such as indium that increase the effective Tk of the TIM. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings Chen et al. in the method of Lai et al. for the purpose of increasing the effective thermal conductivity of the thermal interface material. Claim(s) 12 and 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lai et al. as applied to claims 1 and 13 above, and further in view of Kuan et al. US 2023/0124098. Regarding claim 12, Lai et al. in Figs. 9 and 10 and [0012]-[0028] teach the device package of claim 1, but do not expressly disclose wherein the adhesive is electrically grounded. Kuan et al. in [0038] teach a semiconductor package 500 using an electrically conductive adhesive 550 can be disposed such that the adhesive 550 will be in contact with ground contact pads 590 on the package substrate 510 and the stiffener 530 to ground the stiffener and thereby enable the stiffener 530 to provide electromagnetic interference or radio-frequency interference shielding benefits when the stiffener 530 is made of an electrically conductive material. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Kuan et al. in the device package of Lai et al. for the purpose of protecting the device package from electromagnetic interference or radio-frequency interference. Regarding claim 24, Lai et al. in Figs. 9 and 10 and [0012]-[0028] teach the method according to claim 13 for packaging an integrated circuit, but do not expressly disclose further comprising electrically grounding the adhesive. Kuan et al. in [0038] teach a semiconductor package 500 using an electrically conductive adhesive 550 can be disposed such that the adhesive 550 will be in contact with ground contact pads 590 on the package substrate 510 and the stiffener 530 to ground the stiffener and thereby enable the stiffener 530 to provide electromagnetic interference or radio-frequency interference shielding benefits when the stiffener 530 is made of an electrically conductive material. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Kuan et al. in the method of Lai et al. for the purpose of protecting the device package from electromagnetic interference or radio-frequency interference. Allowable Subject Matter Claims 2-4 and 14-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: the prior art neither anticipates nor renders obvious, in the context of the claims, Regarding claim 2, wherein the at least one opening is a first opening and the stiffener is configured to: overlay the first integrated circuit die among the at least two integrated circuit dies; and define a second opening at least partially exposing a surface of the second integrated circuit die among the at least two integrated circuit dies to provide the second heat dissipation mode for the second integrated circuit die among the at least two integrated circuit dies. Claims 3 and 4 directly or indirectly depend on claim 2. Regarding claim 14, configuring the stiffener to overlay the first integrated circuit die among the at least two integrated circuit dies; and at least partially exposing, through an opening in the stiffener, a surface of the second integrated circuit die among the at least two integrated circuit dies to provide the second heat dissipation mode for the second integrated circuit die among the at least two integrated circuit dies. Claims 15 and 16 directly or indirectly depend on claim 14. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SONYA D MCCALL-SHEPARD whose telephone number is (571)272-9801. The examiner can normally be reached M-F: 8:30 AM-5:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio J. Maldonado can be reached at (571)272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Sonya McCall-Shepard/Primary Examiner, Art Unit 2898
Read full office action

Prosecution Timeline

Show 3 earlier events
Jul 07, 2026
Final Rejection mailed — §103, §112
Aug 21, 2026
Interview Requested
Aug 31, 2026
Applicant Interview (Telephonic)
Aug 31, 2026
Examiner Interview Summary
Sep 01, 2026
Response after Non-Final Action
Sep 14, 2026
Request for Continued Examination
Sep 17, 2026
Response after Non-Final Action
Sep 28, 2026
Non-Final Rejection mailed — §103, §112 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
93%
Grant Probability
96%
With Interview (+3.5%)
2y 0m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 1200 resolved cases by this examiner. Grant probability derived from career allowance rate.

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