DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
For Examiner’s Interview fill out the online Automated Interview Request (AIR) form (http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html).
Status of claim(s) to be treated in this office action:
Independent: 1, 11 and 16.
Pending: 1-20.
Withdrawn: 11-20.
Election/Restrictions
Applicant’s election without traverse of Species I fig. 1-6, claim 1-10 in the reply filed on 4/23/2026 is acknowledged.
Specification
The disclosure is objected to because of the following informalities:
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: SEMICONDUCTOR PACKAGE STRUCTURE INCLUDING CONDUCTIVE SPACERS BETWEEN A CHIP AND A LEAD FRAME.
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 5-7 and 9 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Shen et al., US Patent 9324626 B2; in view of Hanke et al., US PG pub. 20100033273 A1.
Re: Independent Claim 1, Shen discloses a conductive substrate (540, fig. 5k) having a chip-bonding surface and a heat-dissipation surface that is opposite to the chip-bonding surface;
a first chip (110E, fig. 5k) disposed on the chip-bonding surface of the conductive substrate (540, fig. 5k) and having a plurality of first connection pads (110E’s 112, fig. 5k) that are arranged away from the conductive substrate (540, fig. 5k);
a second chip (110D, fig. 5k) disposed on one of the first connection pads (110E’s 112, fig. 5k) of the first chip (110E, fig. 5k) and having a plurality of second connection pads (110D’s 112, fig. 5k) that are arranged away from the conductive substrate (540, fig. 5k);
a plurality of conductive spacers including a first conductive via (520.1 and 520.2 connected to 110E) disposed on another of the first connection pads (110E’s 112, fig. 5k) and a plurality of second conductive vias (520.1 connected to 110D, fig. 5k) that are respectively disposed on the second connection pads (110D’s 112, fig. 5k), wherein a thickness of the first conductive via (520.1 and 520.2 connected to 110E) is greater than a thickness (thickness of 520.1 and 520.2 is greater than single 520.1) of each of the second conductive vias (520.1 connected to 110D, fig. 5k), and an end of the first conductive via (520.1 and 520.2 connected to 110E) and ends of the second conductive vias (520.1 connected to 110D, fig. 5k) are arranged away from the conductive substrate (540, fig. 5k) and are coplanar with each other (both conductive spacer stopped at coplanar level 520.0, fig. 5k);
a lead frame (518, 510.2 and 520S, fig. 5k and 8b) connected to the end of the first conductive via (520.1 and 520.2 connected to 110E) and the ends of the second conductive vias (520.1 connected to 110D, fig. 5k) in a flip-chip manner and having an exposed surface; and
an encapsulant (524, fig. 5k) covering the conductive substrate (540, fig. 5k), the first chip (110E, fig. 5k), the second chip (110D, fig. 5k), the first conductive via (520.1 and 520.2 connected to 110E), the second conductive vias (520.1 connected to 110D, fig. 5k), and the lead frame (518, 510.2 and 520S, fig. 5k and 8b), wherein the exposed surface and the heat-dissipation surface are exposed from the encapsulant (524, fig. 5k).
Shen is silent regarding: the conductive spacer instead Shen teaches conductive vias.
Hanke discloses a through via can be interchangeable as a conductive spacer (¶0059).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a conductive spacer instead of a conductive via since a conductive spacer can provide a better structure stability to the chip stacking structure than a via structure.
Re: Claim 2, Shen and Hanke discloses all the limitations of claim 1 on which this claim depends. Shen further discloses: wherein the exposed surface and the heat-dissipation surface are flush (the heat spreader 540 are flush with an outer surface of encapsulation 524 with surface of 518 of the frame structure) with an outer surface of the encapsulant (524, fig. 5k).
Re: Claim 5, Shen and Hanke discloses all the limitations of claim 1 on which this claim depends. Shen further discloses: a plurality of conductive bonding layers (conductive gold electroplated between 110E and 110D), wherein any two of the conductive substrate (540, fig. 5k), the first chip (110E, fig. 5k), the second chip (110D, fig. 5k), the conductive spacers, and the lead frame (518, 510.2 and 520S, fig. 5k and 8b) connected to each other are connected through one of the conductive bonding layers (conductive gold electroplated between 110E and 110D).
Re: Claim 6, Shen and Hanke discloses all the limitations of claim 5 on which this claim depends. Shen further discloses: wherein the semiconductor package structure does not have any soldering structure covered (package structure the soldering structure are covered by die 110 and connecting plate 112) by the encapsulant (524, fig. 5k).
Re: Claim 7, Shen and Hanke discloses all the limitations of claim 1 on which this claim depends. Shen further discloses: wherein the semiconductor package structure does not have any wiring structure covered by the encapsulant (524, fig. 5k).
Re: Claim 9, Shen and Hanke discloses all the limitations of claim 1 on which this claim depends. Shen further discloses: wherein the conductive substrate (540, fig. 5k) has a half-etching slot that surrounds the heat-dissipation surface and that is fully filled with the encapsulant (524, fig. 5k).
Claim(s) 3 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Shen et al., US Patent 9324626 B2; in view of Hanke et al., US PG pub. 20100033273 A1; further in view of Fillion et al., US PG pub. 20080305582 A1.
Re: Claim 3, Shen and Hanke discloses all the limitations of claim 1 on which this claim depends. Shen and Hanke are silent regarding: wherein each of the conductive spacers has a coefficient of thermal expansion (CTE) that is less than 10.
Fillion teaches that a conductive spacer can use material with a coefficient of thermal expansion of less than 10 for example material such as Titanium or Tungsten (¶0091).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a conductive spacer with a lower coefficient of thermal expansion since semiconductor dies have an intrinsically low CTE, metal like copper or aluminum have much higher CTE which can cause stress and cracking in the semiconductor device by having a lower CTE that is closer to a semiconductor die can prevent cracking or prevent warpage of the semiconductor package device.
Claim(s) 4 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Shen et al., US Patent 9324626 B2; in view of Hanke et al., US PG pub. 20100033273 A1; further in view of Li US Patent 9054482 B1.
Re: Claim 4, Shen and Hanke discloses all the limitations of claim 1 on which this claim depends. Shen and Hanke are silent regarding: wherein a CTE of each of the conductive spacers is less than two times of a CTE of the first chip (110E, fig. 5k) and is less than two times of a CTE of the second chip (110D, fig. 5k).
Li teaches wherein a CTE of each of the conductive spacers is less than two times of a CTE of the first chip and CTE of the second chip (column 7, lines 52-61).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a conductive spacer with a lower coefficient of thermal expansion since a silicon dies have an intrinsically low, using CTE material that can matches matier such as GaAs with a 6.86ppm/K can prevent cracking or prevent warpage of the silicon die.
Claim(s) 8 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Shen et al., US Patent 9324626 B2; in view of Hanke et al., US PG pub. 20100033273 A1; further in view of Roberts et al., US PG pub. 20140175454 A1.
Re: Claim 8, Shen and Hanke discloses all the limitations of claim 1 on which this claim depends. Shen and Hanke are silent regarding: wherein a size of the first chip (110E, fig. 5k) is greater than a size of the second chip (110D, fig. 5k), the first chip (110E, fig. 5k) is a silicon carbide (SiC) chip or a gallium nitride (GaN) chip, and the second chip (110D, fig. 5k) is a metal oxide semiconductor field effect transistor (MOSFET) chip.
Roberts discloses a GaN die and a CMOS die can be stacked as in a flip-chip configuration provide a direction interconnection between drain and driver MOSFET and source of the GaN HEMT and between the source driver MOSFET and the gate of the GaN HEMT (¶0025).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have a GaN die stack on to a MOSFET chip since this can reduce thermal resistance, and improve heat dissipation, and the packaging arrangement (¶0081).
Prior art made of record and not relied upon are considered pertinent to current application disclosure.
* (“You et al., US Patent 12028006 B2”) Discloses an embodiment is power module including a plurality of first switching elements of a first type semiconductor on a first substrate, a plurality of second switching elements of a second type semiconductor and a third switching element of the first type semiconductor or the second type semiconductor on a second substrate, wherein the first substrate has a different thermal conductivity than the second substrate, and a connection spacer configured to electrically connect the first substrate and the second substrate..
* (“Lee et al., US patent 11289456 B2”) discloses a semiconductor package includes a frame having a through-opening, a first semiconductor chip disposed in the through-opening and having a first active surface on which a first connection pad is disposed and a first inactive surface opposing the first active surface, a second semiconductor chip disposed on the first semiconductor chip and having a second active surface on which a second connection pad is disposed and a second inactive surface opposing the second active surface, first and second bumps electrically connected to the first and second connection pads, respectively, first and second dummy bumps disposed on a same level as levels of the first and second bumps, respectively, first and second posts electrically connected to the first and second bumps, respectively, a connection member including a redistribution layer electrically connected to each of the first and second posts, and a dummy post disposed between the frame and the connection member.
* (“Lin et al., US PG pub. 20190341332 A1”) Discloses a dual-side cooling package includes a first semiconductor die and a second semiconductor die disposed between a first direct bonded metal (DBM) substrate and a second DBM substrate. A metal surface of the first DBM substrate defines a first outer surface of a package and a metal surface of the second DBM substrate defines a second outer surface of the package. The first semiconductor die is thermally coupled to the first DBM substrate. A first conductive spacer thermally couples the first semiconductor die to the second DBM substrate. The second semiconductor die is thermally coupled to a second conductive spacer. Further, one of the second semiconductor die and the second conductive spacer is thermally coupled to the first DMB substrate and the other of the second semiconductor die and the second conductive spacer is thermally coupled to the second DBM substrate.
* (“Lin et al., US PG pub. 20250174515 A1”) discloses a package includes a semiconductor die disposed between a first high voltage isolation carrier and a second high voltage isolation carrier. The semiconductor die is thermally coupled to the first high voltage isolation carrier. The package also includes a molding material disposed in a space between the semiconductor die and the first high voltage isolation carrier, and a conductive spacer disposed between the semiconductor die and the second high voltage isolation carrier. The conductive spacer is thermally coupled to semiconductor die and to the second high voltage isolation carrier. A longitudinal dimension of the conductive spacer is greater than a longitudinal dimension of the semiconductor die. The molding material encapsulates the semiconductor die and the conductive spacer.
* (“Law et al., US PG pub. 20120025388 A1”) Discloses a three dimensional (3D) integrated circuit (IC) structure having improved power and thermal management is described. The 3D IC structure includes at least first and second dies. Each of the first and second dies has at least one power through silicon via (TSV) and one signal TSV. The at least one power and signal TSVs of the first die are connected to the at least one power and signal TSVs of the second die, respectively. The 3D IC structure also includes one or more peripheral TSV structures disposed adjacent to one or more sides of the first and/or the second die. The peripheral TSV structures supply at least power and/or signals.
* (“Jeon US Patent 9390996 B2”) discloses a double-sided cooling power module may include a lower-end terminal, at least one pair of power semiconductor chips mounted on the lower-end terminal, at least one pair of horizontal spacers mounted on the at least one pair of power semiconductor chips, an upper-end terminal mounted on the at least one pair of horizontal spacers, and at least one pair of vertical spacers disposed between the upper-end terminal and the lower-end terminal.
* (“Hoegerl et al., US Patent 9349709 B2”) Discloses an electronic component comprising an electrically conductive chip carrier comprising an electrically insulating core structure at least partially covered with electrically conductive material, at least one electronic chip each having a first main surface attached to the chip carrier, and a sheet-like redistribution structure attached to a second main surface of the at least one electronic chip and configured for electrically connecting the second main surface of the at least one electronic chip with the chip carrier.
* (“Fang et al., US Patent 9825010 B2”) discloses a stacked chip package structure includes a first chip, pillar bumps, a first encapsulant, a first redistribution layer, a second chip, a second encapsulant, a second redistribution layer and a through via. The pillar bumps are disposed on a plurality of first pads of the first chip respectively. The first encapsulant encapsulates the first chip and exposes the pillar bumps. The first redistribution layer is disposed on the first encapsulant and electrically connects the first chip. The second chip is disposed on the first redistribution layer. The second encapsulant encapsulates the second chip. The second redistribution layer is disposed on the second encapsulant and electrically coupled to the second chip. The through via penetrates the second encapsulant and electrically connects the first redistribution layer and the second redistribution layer.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TSZ CHIU whose telephone number is 571-272-8656. The examiner can normally be reached on M-F, 9:00AM to 5:00PM (EST).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at https://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached on 571-270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TSZ K CHIU/Examiner, Art Unit 2898 Tsz.Chiu@uspto.gov
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
Prosecution Insights