DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
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Status of claim(s) to be treated in this office action:
Independent: 1, 11 and 16.
Pending: 1-20.
Withdrawn: 11-20.
Response to Arguments
Applicant's arguments filed 7/28/2026 have been fully considered but they are not persuasive. Applicant argues that Shen fails to teach “a first chip disposed on the chip-bonding surface of the conductive substrate.” Examiner disagrees, as shown in fig. 5k of Shen, the first chip 110E is disposed on the chip-bonding surface of the conductive substrate 540. In particular, the chip-bonding surface corresponds to the surface area identified as 524.4, which includes the bonding bumps. Accordingly, Shen teaches a first chip disposed on the chip-bonding surface of the conductive substrate, as recited in the claim. Applicant further argues that Shen fails to teach “a lead frame connected to the end of the first conductive spacer and the ends of the second conductive spacers in a flip-chip manner.” The Examiner respectfully disagrees. As shown in Fig. 5k of Shen, the lead frame 520S is connected to the ends of the first and second conductive elements 520.1 and 520.2, which, in turn, are connected to chips 110D and 110E, respectively. Because chips 110D and 110E are oriented with their connection surfaces facing downward and are connected to the lead frame 520S through the respective conductive elements 520.1 and 520.2, the illustrated arrangement constitutes a flip-chip connection. Therefore, Shen, alone in view of Hanke, teaches the above-identified claim limitations. Accordingly, Applicant’s arguments do not overcome the rejection.
Applicant also pointed out that claim 10 had not been rejected. Examiner explained that claim 10 was intended to be objected to, but the objection was inadvertently omitted from the form paragraph indicating the allowable claims. Examiner agreed that claim 10 would be allowable if rewritten in independent form to incorporate all of limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 5-7 and 9 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Shen et al., US Patent 9324626 B2; in view of Hanke et al., US PG pub. 20100033273 A1.
Re: Independent Claim 1, Shen discloses a conductive substrate (540, fig. 5k) having a chip-bonding surface and a heat-dissipation surface that is opposite to the chip-bonding surface;
a first chip (110E, fig. 5k) disposed on the chip-bonding surface of the conductive substrate (540, fig. 5k) and having a plurality of first connection pads (110E’s 112, fig. 5k) that are arranged away from the conductive substrate (540, fig. 5k);
a second chip (110D, fig. 5k) disposed on one of the first connection pads (110E’s 112, fig. 5k) of the first chip (110E, fig. 5k) and having a plurality of second connection pads (110D’s 112, fig. 5k) that are arranged away from the conductive substrate (540, fig. 5k);
a plurality of conductive spacers including a first conductive via (520.1 and 520.2 connected to 110E) disposed on another of the first connection pads (110E’s 112, fig. 5k) and a plurality of second conductive vias (520.1 connected to 110D, fig. 5k) that are respectively disposed on the second connection pads (110D’s 112, fig. 5k), wherein a thickness of the first conductive via (520.1 and 520.2 connected to 110E) is greater than a thickness (thickness of 520.1 and 520.2 is greater than single 520.1) of each of the second conductive vias (520.1 connected to 110D, fig. 5k), and an end of the first conductive via (520.1 and 520.2 connected to 110E) and ends of the second conductive vias (520.1 connected to 110D, fig. 5k) are arranged away from the conductive substrate (540, fig. 5k) and are coplanar with each other (both conductive spacer stopped at coplanar level 520.0, fig. 5k);
a lead frame (518, 510.2 and 520S, fig. 5k and 8b) connected to the end of the first conductive via (520.1 and 520.2 connected to 110E) and the ends of the second conductive vias (520.1 connected to 110D, fig. 5k) in a flip-chip manner and having an exposed surface; and
an encapsulant (524, fig. 5k) covering the conductive substrate (540, fig. 5k), the first chip (110E, fig. 5k), the second chip (110D, fig. 5k), the first conductive via (520.1 and 520.2 connected to 110E), the second conductive vias (520.1 connected to 110D, fig. 5k), and the lead frame (518, 510.2 and 520S, fig. 5k and 8b), wherein the exposed surface and the heat-dissipation surface are exposed from the encapsulant (524, fig. 5k).
Shen is silent regarding: the conductive spacer instead Shen teaches conductive vias.
Hanke discloses a through via can be interchangeable as a conductive spacer (¶0059).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a conductive spacer instead of a conductive via since a conductive spacer can provide a better structure stability to the chip stacking structure than a via structure.
Re: Claim 2, Shen and Hanke discloses all the limitations of claim 1 on which this claim depends. Shen further discloses: wherein the exposed surface and the heat-dissipation surface are flush (the heat spreader 540 are flush with an outer surface of encapsulation 524 with surface of 518 of the frame structure) with an outer surface of the encapsulant (524, fig. 5k).
Re: Claim 5, Shen and Hanke discloses all the limitations of claim 1 on which this claim depends. Shen further discloses: a plurality of conductive bonding layers (conductive gold electroplated between 110E and 110D), wherein any two of the conductive substrate (540, fig. 5k), the first chip (110E, fig. 5k), the second chip (110D, fig. 5k), the conductive spacers, and the lead frame (518, 510.2 and 520S, fig. 5k and 8b) connected to each other are connected through one of the conductive bonding layers (conductive gold electroplated between 110E and 110D).
Re: Claim 6, Shen and Hanke discloses all the limitations of claim 5 on which this claim depends. Shen further discloses: wherein the semiconductor package structure does not have any soldering structure covered (package structure the soldering structure are covered by die 110 and connecting plate 112) by the encapsulant (524, fig. 5k).
Re: Claim 7, Shen and Hanke discloses all the limitations of claim 1 on which this claim depends. Shen further discloses: wherein the semiconductor package structure does not have any wiring structure covered by the encapsulant (524, fig. 5k).
Re: Claim 9, Shen and Hanke discloses all the limitations of claim 1 on which this claim depends. Shen further discloses: wherein the conductive substrate (540, fig. 5k) has a half-etching slot that surrounds the heat-dissipation surface and that is fully filled with the encapsulant (524, fig. 5k).
Claim(s) 3 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Shen et al., US Patent 9324626 B2; in view of Hanke et al., US PG pub. 20100033273 A1; further in view of Fillion et al., US PG pub. 20080305582 A1.
Re: Claim 3, Shen and Hanke discloses all the limitations of claim 1 on which this claim depends. Shen and Hanke are silent regarding: wherein each of the conductive spacers has a coefficient of thermal expansion (CTE) that is less than 10.
Fillion teaches that a conductive spacer can use material with a coefficient of thermal expansion of less than 10 for example material such as Titanium or Tungsten (¶0091).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a conductive spacer with a lower coefficient of thermal expansion since semiconductor dies have an intrinsically low CTE, metal like copper or aluminum have much higher CTE which can cause stress and cracking in the semiconductor device by having a lower CTE that is closer to a semiconductor die can prevent cracking or prevent warpage of the semiconductor package device.
Claim(s) 4 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Shen et al., US Patent 9324626 B2; in view of Hanke et al., US PG pub. 20100033273 A1; further in view of Li US Patent 9054482 B1.
Re: Claim 4, Shen and Hanke discloses all the limitations of claim 1 on which this claim depends. Shen and Hanke are silent regarding: wherein a CTE of each of the conductive spacers is less than two times of a CTE of the first chip (110E, fig. 5k) and is less than two times of a CTE of the second chip (110D, fig. 5k).
Li teaches wherein a CTE of each of the conductive spacers is less than two times of a CTE of the first chip and CTE of the second chip (column 7, lines 52-61).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a conductive spacer with a lower coefficient of thermal expansion since a silicon dies have an intrinsically low, using CTE material that can matches matier such as GaAs with a 6.86ppm/K can prevent cracking or prevent warpage of the silicon die.
Claim(s) 8 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Shen et al., US Patent 9324626 B2; in view of Hanke et al., US PG pub. 20100033273 A1; further in view of Roberts et al., US PG pub. 20140175454 A1.
Re: Claim 8, Shen and Hanke discloses all the limitations of claim 1 on which this claim depends. Shen and Hanke are silent regarding: wherein a size of the first chip (110E, fig. 5k) is greater than a size of the second chip (110D, fig. 5k), the first chip (110E, fig. 5k) is a silicon carbide (SiC) chip or a gallium nitride (GaN) chip, and the second chip (110D, fig. 5k) is a metal oxide semiconductor field effect transistor (MOSFET) chip.
Roberts discloses a GaN die and a CMOS die can be stacked as in a flip-chip configuration provide a direction interconnection between drain and driver MOSFET and source of the GaN HEMT and between the source driver MOSFET and the gate of the GaN HEMT (¶0025).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have a GaN die stack on to a MOSFET chip since this can reduce thermal resistance, and improve heat dissipation, and the packaging arrangement (¶0081).
Allowable Subject Matter
Claim(s) 10 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Re: Claim 10, the prior art of record do not disclose or suggest, in combination with all other limitations in the claim: wherein the lead frame includes: a first frame connected to the end of the first conductive spacer and having a part of the exposed surface that is defined as a first exposed surface, wherein the first frame has a first half-etching slot that surrounds the first exposed surface and that is fully filled with the encapsulant; and a plurality of second frames connected to the ends of the second conductive spacers and each having another part of the exposed surface that is defined as a second exposed surface, wherein each of the second frames has a second half-etching slot that surrounds the second exposed surface thereof and that is fully filled with the encapsulant.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TSZ CHIU whose telephone number is 571-272-8656. The examiner can normally be reached on M-F, 9:00AM to 5:00PM (EST).
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/TSZ K CHIU/Examiner, Art Unit 2898 Tsz.Chiu@uspto.gov
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
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