Prosecution Insights
Last updated: April 19, 2026
Application No. 18/419,533

TRANSISTOR DISPLAY PANEL, MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE INCLUDING THE SAME

Non-Final OA §103
Filed
Jan 22, 2024
Examiner
ANDUJAR, LEONARDO
Art Unit
3991
Tech Center
3900
Assignee
Samsung Display Co., Ltd.
OA Round
1 (Non-Final)
75%
Grant Probability
Favorable
1-2
OA Rounds
3y 7m
To Grant
75%
With Interview

Examiner Intelligence

Grants 75% — above average
75%
Career Allow Rate
142 granted / 189 resolved
+15.1% vs TC avg
Minimal -0% lift
Without
With
+-0.5%
Interview Lift
resolved cases with interview
Typical timeline
3y 7m
Avg Prosecution
11 currently pending
Career history
200
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
54.9%
+14.9% vs TC avg
§102
25.7%
-14.3% vs TC avg
§112
11.3%
-28.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 189 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 9,954,0431). Regarding claim 12, Park (e.g. figs. 1 and 5a; col. 1/ll. 35-64) teaches a display device. PNG media_image1.png 465 507 media_image1.png Greyscale The device display comprises: a driving voltage line L1 and a first electrode BS disposed on a substrate SUB; a semiconductor disposed on the substrate and overlapping the first electrode (ST); and an electrode layer (SS, SG, SD) overlapping the semiconductor, the electrode layer comprising a drain electrode, a gate electrode, and a source electrode; PNG media_image2.png 85 109 media_image2.png Greyscale wherein the semiconductor includes a source region, a drain region, and a channel region (TFT ST); the source region, the drain region, and the channel region are disposed above and overlap the first electrode SUB in a direction perpendicular to the substrate; the first electrode and the semiconductor are connected through the source electrode BS; PNG media_image3.png 150 242 media_image3.png Greyscale the first electrode is disposed between the substrate and the semiconductor; and the first electrode and the driving voltage line are disposed in a same layer. Regarding the claim limitation of “simultaneously formed by the same process”, it is considered a “product by process limitation” [MPEP 2113]. The limitation that the first electrode and the driving voltage line are “simultaneously formed by the same process” is interpreted as requiring that these elements are formed from the same conductive layer and share a common structural level. This result in a structure in which the first electrode and the driving voltage line are coplanar features. Park discloses conducive elements corresponding to the first electrode and driving voltage line disposed in a same layer, as evidenced by their coplanar arrangement (col. 9/ll. 13-35). Moreover, Park teaches that the conductive elements may be formed of the same material (col. 9/ll. 13-35). It would have been obvious to form the first electrode and the driving voltage line form a same conductive layer using a common deposition and patterning process, since elements formed from the same material are routinely fabricated in a single layer to reduce process complexity and the number of photolithography steps. Conclusion Attached is a copy and a translation of KR-10-2015-0189675[US 9,954,043, priority document}. Any inquiry concerning this communication or earlier communications from the examiner should be directed to LEONARDO ANDUJAR whose telephone number is (571)272-1912. The examiner can normally be reached Monday to Thursday 10 AM to 8 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Patricia L Engle can be reached at (571)272-6660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Leonardo Andujar/ Primary Examiner Art Unit 3991 CRU Conferees: /LEE E SANDERSON/Reexamination Specialist, Art Unit 3991 /Patricia L Engle/SPRS, Art Unit 3991 1 The reference is relied upon as prior art as of at least its U.S. filing date. The Examiner notes that the reference may be entitle to an earlier foreign priority date under 35 U.S.C 119, provided that the relied upon subject matter is disclosed in the prior application [MPEP 2163.03].
Read full office action

Prosecution Timeline

Jan 22, 2024
Application Filed
Jan 22, 2024
Response after Non-Final Action
Mar 27, 2026
Non-Final Rejection — §103 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
75%
Grant Probability
75%
With Interview (-0.5%)
3y 7m
Median Time to Grant
Low
PTA Risk
Based on 189 resolved cases by this examiner. Grant probability derived from career allow rate.

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