DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of claims 1-20 in the reply filed on 5/26/26 is acknowledged. The traversal is on the ground(s) that see election dated 5/26/26. This is not found persuasive because the search and consideration of patentably distinct inventions are note co-extensive.
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-16 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Imai (US pub 20060008974).
With respect to claim 1, Imai teaches a semiconductor device comprising (see figs. 1-22, particularly figs. 12 and 14 and associated text):
a stack structure having a plurality of semiconductor chips 70, each of the plurality of semiconductor chips having an interlayer insulating layer 16, 40 disposed over or on a substrate 70, a chip top interconnection (lateral part of 52) over or on the interlayer insulating layer and a chip top insulating layer 72 over or on the chip top interconnection;
a side interconnection (90 and vertical part of 52) disposed over or on a side surface of the stack structure, the side interconnection being connected to the chip top interconnection; and
a plurality of insulating patterns 40 disposed between the stack structure and the side interconnection, wherein each of the plurality of insulating patterns directly contacts a side surface of the substrate and the interlayer insulating layer of an adjacent one among the plurality of the semiconductor chips.
With respect to claim 2, Imai teaches the side interconnection directly contacts the plurality of insulating patterns, the interlayer insulating layer and the chip top insulating layer. See figs. 12 and 14 and associated text.
With respect to claim 3, Imai teaches the plurality of semiconductor chips comprise first to third semiconductor chips which are sequentially stacked, and one of the plurality of insulating patterns of the second semiconductor chip is aligned with a side surface of the substrate of the second semiconductor chip. See figs. 12 and 14 and associated text.
With respect to claim 4, Imai teaches one of the plurality of insulating patterns of the second semiconductor chip directly contacts a side surface of the substrate of the second semiconductor chip, a bottom surface of the interlayer insulating layer of the second semiconductor chip and a top surface of the chip top insulating layer of the first semiconductor chip. See figs. 12 and 14 and associated text.
With respect to claim 5, Imai teaches a lowermost end of one of the plurality of insulating patterns is limited to a level higher than an uppermost end of the chip top interconnection of the first semiconductor chip, and an uppermost end of one of the plurality of insulating patterns is limited to a level lower than a lowermost end of the chip top interconnection of the second semiconductor chip. See figs. 12 and 14 and associated text.
With respect to claim 6, Imai teaches the substrate of the second semiconductor chip directly contacts the chip top insulating layer of the first semiconductor chip, and the substrate of the third semiconductor chip directly contacts the chip top insulating layer of the second semiconductor chip. See figs. 12 and 14 and associated text.
With respect to claim 7, Imai teaches one of the plurality of insulating patterns protrudes out of the interlayer insulating layer adjacent thereto. See figs. 12 and 14 and associated text.
With respect to claim 8, Imai teaches the substrate comprises an active region (middle) and an outer region (edge) which is continuous and covers a side edge of the active region, and the chip top interconnection extends from the active region onto the outer region. See figs. 12 and 14 and associated text.
With respect to claim 9, Imai teaches a guard ring 14 disposed in the interlayer insulating layer over the active region adjacent to the outer region, wherein the chip top interconnection crosses the guard ring. See figs. 12 and 14 and associated text.
With respect to claim 10, Imai teaches a conductive plug (right end or edge of 52) disposed between the chip top interconnection and the side interconnection, and having substantially the same thickness as the chip top interconnection. See figs. 12 and 14 and associated text.
With respect to claim 11, Imai teaches the conductive plug is disposed between the interlayer insulating layer and the chip top insulating layer over the outer region. See figs. 12 and 14 and associated text.
With respect to claim 12, Imai teaches a capping layer 88 disposed in the interlayer insulating layer over the outer region, and directly contacting the side interconnection. See figs. 12 and 14 and associated text.
With respect to claim 13, Imai teaches the chip top insulating layer completely covers a top surface of the chip top interconnection, and the chip top insulating layer includes a planarized top surface. See figs. 12 and 14 and associated text.
With respect to claim 14, Imai teaches a protective insulating layer 88 (middle and top part of 88) disposed over or on the stack structure, the plurality of insulating patterns and the side interconnection. See figs. 12 and 14 and associated text.
With respect to claim 15, Imai teaches the side interconnection comprises an external connection terminal (lateral 52, vertical 52 and 90 of the top chip) which extends over or on the stack structure, and the external connection terminal is exposed through an opening which passes through the protective insulating layer. See figs. 12 and 14 and associated text.
With respect to claim 16, Imai teaches the protective insulating layer covers a lowermost end of the side interconnection. See figs. 12 and 14 and associated text.
Claim(s) 17 and 18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Imai (US pub 20060008974).
With respect to claim 17, Imai teaches a semiconductor device comprising (see figs. 1-22, particularly figs. 12 and 14 and associated text):
a stack structure having a plurality of semiconductor chips 70, each of the plurality of semiconductor chips having an interlayer insulating layer 16,40 disposed over or on a substrate 70, a chip top interconnection (lateral part of 52) disposed over or on the interlayer insulating layer and a chip top insulating layer 72 disposed over or on the chip top interconnection;
a side interconnection (90 and vertical part of 52) disposed over or on a side surface of the stack structure, and connected to the chip top interconnection; and
a plurality of insulating patterns 40 disposed between the stack structure and the side interconnection, each of the plurality of insulating patterns being aligned with a side surface of the substrate.
With respect to claim 18, Imai teaches the side interconnection directly contacts the plurality of insulating patterns, the interlayer insulating layer and the chip top insulating layer. See figs. 12 and 14 and associated text.
Claim(s) 19 and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Imai (US pub 20060008974).
With respect to claim 19, Imai teaches a semiconductor device comprising (see figs. 1-22, particularly figs. 12 and 14 and associated text):
a stack structure having a plurality of semiconductor chips 70, each of the plurality of semiconductor chips having an interlayer insulating 16,40 disposed over or on a substrate 70, a chip top interconnection (lateral part of 52) disposed over or on the interlayer insulating layer and a chip top insulating layer 72 disposed over or on the chip top interconnection;
a side interconnection (90 and vertical part of 52) disposed over or on a side surface of the stack structure, and connected to the chip top interconnection; and
an insulating pattern 40 between the stack structure and the side interconnection, wherein the insulating pattern directly contacts side surfaces of the substrate, the interlayer insulating layer and the chip top insulating layer.
With respect to claim 20, Imai teaches the side interconnection is connected to the chip top interconnection through the insulating pattern. See figs. 12 and 14 and associated text.
Examiner’s Cited References
The cited references generally show the similar or related structure having stacked chips, each chip having a substrate, an interlayer insulating layer, a lateral connector, and a top insulating layer, having a side interconnect separated from the substrate and connected to the lateral connector as presently claimed by applicant.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LONG PHAM whose telephone number is (571)272-1714. The examiner can normally be reached Mon-Friday.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469-295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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LONG . PHAM
Examiner
Art Unit 2823
/LONG PHAM/Primary Examiner, Art Unit 2897
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