Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim (s) 1 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Gulachenski et al. (US 6943454 B1) hereinafter Gulach.
Regarding claim 1,Gulach discloses an embedded dual in-line memory module (Fig.3) comprising: a printed circuit board (13) which includes a first surface (top surface 13), a second surface (bottom of 13) opposite to the first surface, a first circuit layer (circuit layer on top surface 13) on the first surface, a second circuit layer (circuit layer on bottom layer of 13) on the second surface, and a conductive contact (19) used for electrical connection to a motherboard of an external electronic device ( 19 is used to connect to a motherboard) ; a first memory chip set composed of a plurality of memory chips (see top set of 23s) each of which is arranged and electrically connected to the first circuit layer on the first surface of the PCB by flip chip (see flip chip mounting of 23 with solder bumps 51) correspondingly; and a second memory chip set ( bottom set of 23s) provided with a plurality of memory chips each of which is electrically disposed and connected to the second circuit layer on the second surface of the PCB by flip chip correspondingly ( bottom set of 23s are connected by solder bumps 51);wherein the respective memory chips on the memory module are directly disposed on the PCB by flip chip so that the memory module has a condition that there is no metal wire for electrical connection generated by wire bonding ( all 23 are mounted onto 13 by solder bump connections; see Fig.3).
It is noted that the limitations of the method steps recited in claim 1 “wherein a method of manufacturing the memory module comprising the following steps of: Step S1: providing a printed circuit board (PCB). The PCB consists of a first surface, a second surface opposite to the first surface, a first circuit layer on the first surface, a second circuit layer on the second surface, and a conductive contact; Step S2: arranging and electrically connecting a first memory chip set to the first circuit layer on the first surface of the PCB by flip chip; wherein the first memory chip set includes a plurality of memory chips; and Step S3: arranging and electrically connecting a second chip memory chip set to the second circuit layer on the second surface of the PCB by flip chip so that manufacturing of a memory module is completed; wherein the second chip memory chip set includes a plurality of memory chips.” are process limitations in a product claim and is treated in accordance with MPEP 2113. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process". In re Thorpe, 777Fo 2d 695,698 USPQ 964, 966 (Fed. Cir.1985). See also MPEP 2113.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim (s) 2-3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gulach as applied to claim 1 above, and further in view of Prince et al. (US 5877545) hereinafter Prince.
Regarding claim 2, Gulach is silent with respect to wherein the memory module further includes a sealing film layer which is covering the memory module by injection molding but the conductive contact on the PCB of the memory module is exposed.
Prince discloses wherein the memory module (23,24,25; Fig.3-4) further includes a sealing film layer (37) which is covering the memory module by molding (37 is molded on to the printed circuit board (21) but the conductive contact on the PCB of the memory module is exposed( printed circuit board 21 has exposed electrical contacts that is not covered by 37).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of claimed invention to use the teachings of Prince to modify the printed circuit board of Gulach in order to provide mechanical protection and prevent damaging of components on the printed circuit board.
It is noted that the limitations of the method steps recited in claim 2“injection molding
” are process limitations in a product claim and is treated in accordance with MPEP 2113. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process". In re Thorpe, 777Fo 2d 695,698 USPQ 964, 966 (Fed. Cir.1985). See also MPEP 2113.
Regarding claim 3, Gulach is silent with respect to wherein the sealing film layer further includes a flat first surface and a flat second surface opposite to each other; wherein the first surface is located outside the first memory chip set while the second surface is located outside the second memory chip set.
Prince discloses wherein the sealing film layer (37;Fig.4) further includes a flat first surface (see top most outer surface of 37) and a flat second surface (see bottom most outer surface of 37) opposite to each other; wherein the first surface is located outside the first memory chip set ( see top surface of 37 above 23,24,25) while the second surface is located outside the second memory chip set (see bottom surface of 37 below 30,31,and 32).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of claimed invention to use the teachings of Prince to modify the printed circuit board of Gulach in order to provide mechanical protection and prevent damaging of components on the printed circuit board.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETE LEE whose telephone number is (571) 270-5921. The examiner can normally be reached on Monday-Friday (2nd & 4th Friday Off). If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Timothy Dole can be reached at (571) 272-2229 The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
/PETE T LEE/Primary Examiner, Art Unit 2847
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